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Messages from 56875

Article: 56875
Subject: Re: An All Digital Phase Lock Loop
From: nagaraj_c_s@yahoo.com (Nagaraj)
Date: 17 Jun 2003 22:14:33 -0700
Links: << >>  << T >>  << A >>
Hi,
   I had worked on DPLL some time back. I had implemented a Successive
approximation based DPLL in VHDL (similar to CD74HC297). It is not
very difficult to do that. I am giving refernce of a paper which I had
followed.
S. Walters and T. Troudet, &#8220;Digital Phase-Locked Loop with
Jitter Bounded,&#8221;
IEEE Transactions on Circuits and Systems , Vol 36, No. 7, July 1989.

Regards,
Nagaraj CS

"Jason Berringer" <look_at_bottom_of@email.com> wrote in message news:<BUOHa.62$%91.16339@news20.bellglobal.com>...
> Thanks to all that have responded and given me a great place to start.
> 
> Jason
> 
> "Jason Berringer" <jberringer@trace-logic.com.delete> wrote in message
> news:YbtHa.3279$ca4.296525@news20.bellglobal.com...
> > Hello guru's
> >
> > I was wondering if anyone has ever attempted a phase lock loop in digital
> > before (specifically VHDL). I'm looking for some examples or pointers on
> > trying to build one for a low frequency range of 200 Hz to 200 kHz. I
>  would
> > appreciate any comments or suggestions. Google didn't get me very far, so
>  if
> > you know of any app notes, etc. please let me know.
> >
> > Thanks,
> >
> > Jason
> >
> >

Article: 56876
Subject: FPGA to Custom ASIC ??
From: nagaraj_c_s@yahoo.com (Nagaraj)
Date: 17 Jun 2003 22:21:03 -0700
Links: << >>  << T >>  << A >>
Hello all,
I have my prototype design in Spartan IIE 400K -7 device (package
FT256). As our high volume application is power,size and cost
oriented, we have to migrate to ASIC.
Because of time crunch, we are not in a position to follow the entire
ASIC design flow.
I want you to suggest some alternatives. One alternative I have in
mind is this. If Xilinx or 3rd party can take our FPGA design and map
it to a one-to-one customized ASIC, we can save the time on ASIC flow
and ASIC verification. What I mean is that start with the FPGA device
and do these things:
1. Remove the unused dedicated resources as well as logic/routing
resources (for example we are using only 5% of BRAMs. So all other
BRAMs can be removed)
2. Remove IOBs of unused pins and keep only those pins which are in
use (we are using only 30% of I/O pins.)
3. Change the packaging if possible.

My question is whether this kind of service is available with XILINX
or any other 3rd parties?
If not could you suggest some other alternative?

Regards,
Nagaraj CS

Article: 56877
Subject: Re: Automatic FPGA testing
From: gilad_coh@walla.co.il (Gilad Cohen)
Date: 17 Jun 2003 23:43:11 -0700
Links: << >>  << T >>  << A >>
Hello Mike.
I did try to run the simulation on a different computer. Perhaps the
problem is in my simulator.

It was quite a long simulation (ran over a weekend).

Anyway, the concept of a VHDL simulation is about "remembering" the
entire history of the simulation. After a very long time, even if the
simulator clears the RAM and writes the history to the hard disk, the
simulation will be slow and heavy.

Gilad



Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3EEF433A.2060702@flukenetworks.com>...
> Gilad Cohen wrote:
> 
> > Every time I ran an exceptionally long VHDL simulation, my computer
> > crashed.
> > I'm using quite a strong server, so I don't think the problem is in
> > the computer.
> > I'm assuming that the long VHDL simulation simply "ate up" all of my
> > system's memory.
> 
> Unless your testbench is using pointers or access types,
> it can not "eat up" memory.
> 
> > The only solution I can see, is to implement the input generation and
> > output examination in software, and call the VHDL simulator on each
> > test at a time.
> > 
> > Does anyone know a better solution to the long VHDL simulation
> > problem?
> 
> 
> Consider trying the testbench on a different computer
> and/or a different simulator.
> 
>     -- Mike Treseler

Article: 56878
Subject: Re: PC-104 dev Boards
From: H. Peter Anvin <hpa@zytor.com>
Date: 17 Jun 2003 23:54:22 -0700
Links: << >>  << T >>  << A >>
Followup to:  <pan.2003.06.10.14.57.31.384036.42674@karpy.com>
By author:    Peter Wallace <pcw@karpy.com>
In newsgroup: comp.arch.fpga
>  
> Actually I would like to use the latest chips but since the PC/104 bus
> is 5V that does limit your choices. Sure you can add resistors, CPLDS or
> other mickey-mousery but that adds cost and complexity. 
> 
> This 5V trouble is also true of PCI cards. There are still _many_ 5V PCI cards
> around. All you need is one 5V card in a backplane and your 3.3V limited 
> FPGA card is in trouble...
> 

Quickswitches is the way to deal with that.  They aren't very
expensive and they handle 5.0<->3.3 V PCI just fine.

	-hpa

-- 
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64

Article: 56879
Subject: Re: Configuring Virtex with rbt files
From: "Peter Seng" <p.seng@seng.de>
Date: Wed, 18 Jun 2003 09:04:08 +0200
Links: << >>  << T >>  << A >>

"PanJuHwa" <panjuhwa_fpga@yahoo.com> schrieb im Newsbeitrag
news:89e30c0c.0306171856.44a334a1@posting.google.com...
> Can we actually do that, and how?
> Will a larger time be incurred in configuring with rbt, since each bit
> is represented by 1 byte in ascii? Can we convert *.rbt back to *.bit?
>
> Thanks!


You can use the *.rbt file but it is ASCII code and so it is large, we
prefer using the binary *.bit file directly, generated as standard by the
XILINX tools.
Hint:  bit order in data byte of *.bit file is in different order (see
XILINX Answer Record # 7112), and has to be changed. Append some (ca. 16)
dummy write cycles at end of *.bit data stream, cause cclk has to toggle a
few times after end of data stream.

with best regards,

Peter Seng


#############################
SENG digitale Systeme GmbH
Im Bruckwasen 35
D 73037 Göppingen
Germany
tel  +7161-75245
fax  +7161-72965
eMail  p.seng@seng.de
net  http://www.seng.de
#############################



Article: 56880
Subject: Cyclone vs. Acex consumption?
From: "Iode" <d_demaio@hotmail.com>
Date: Wed, 18 Jun 2003 09:08:54 +0200
Links: << >>  << T >>  << A >>

Hi to everyone,



Has anyone had experience porting a design from Acex to Cyclone? What should
I expect from the point of view of power consumption? Using the calculator
tools give worrying results: comparing a c30 with a 1k50 I have 33.5mA of
standby current for Cyclone, 5 mA for Acex; I/Os consumption also seems to
be higher in Cyclone; core consumption seems to be less but, all in all, am
I going to need more or less power using Cyclone?

Perhaps less power while the clock is running but more power when in
stand-by?



Thank you.

Iode




Article: 56881
Subject: Re: Configuring Virtex with rbt files
From: Philip Freidin <philip@fliptronics.com>
Date: Wed, 18 Jun 2003 07:10:07 GMT
Links: << >>  << T >>  << A >>
On 17 Jun 2003 19:56:26 -0700, panjuhwa_fpga@yahoo.com (PanJuHwa) wrote:
>Can we actually do that, and how?
>Will a larger time be incurred in configuring with rbt, since each bit
>is represented by 1 byte in ascii? Can we convert *.rbt back to *.bit?
>Thanks!

While you probably could conver an RBT to BIT, you probably
don't need to.

The advantage of RBT is that it is human readable, so it is easy to
look at with an editor, and see how it is laid out, and what to
look for when parsing it (in a program you might write).

Look here for some examples:

   http://www.fpga-faq.com/archives/33100.html#33108

The time it takes you to configure is typically not limited by
the file format. It is limited by how your configuration device
talks to the FPGA.

If you are configuring from a PROM, then the configuration clock
and the PROM (EPROM, FLASH, EEPROM, SerialEPROM, .....) access
time will set the speed.

If you are configuring with a local processor, then the time
taken depends on the interface, and the speed of the configuration
routine.

If you are configuring via a host computer via a download cable
connected to the parallel (printer) port, in current technology
computers, you are limited by the speed of the processor talking
to the parallel port, which is about 500K updates per second,
regardless of whether it is a 25MHz 80486, or a 2GHz Pentia/Athalon.

In the end it is just bits.

If you are storing the bitstream in a PROM, or using a local
processor for configuration, you need to get it into the
right format. Neither the RBT or BIT files are exactly right.

Either use a PROM formatting progam that reads these files and
formats it appropriately, or write your own.

Getting back to your original question: The difference in speed
of the two file formats is how long it takes you to read the file,
which is about 8:1 . Depending on environment, this is irrelevant.

Philip Freidin




Philip Freidin
Fliptronics

Article: 56882
Subject: Fuse Map for Xilinx XPLA3
From: Martin Sauer <msau@displaign.de>
Date: Wed, 18 Jun 2003 09:18:42 +0200
Links: << >>  << T >>  << A >>
Hello,

I read in the Xilinx Programmer Qualification Spec. that there is a 
Excel file for the XPLA3 fuse map available. Can you tell me, where I 
can find this file?

Thank you very much.

best wishes

martin sauer


Article: 56883
Subject: Re: Automatic FPGA testing
From: Allan Herriman <allan_herriman.hates.spam@agilent.com>
Date: Wed, 18 Jun 2003 17:43:18 +1000
Links: << >>  << T >>  << A >>
On 17 Jun 2003 23:43:11 -0700, gilad_coh@walla.co.il (Gilad Cohen)
wrote:

>Hello Mike.
>I did try to run the simulation on a different computer. Perhaps the
>problem is in my simulator.
>
>It was quite a long simulation (ran over a weekend).
>
>Anyway, the concept of a VHDL simulation is about "remembering" the
>entire history of the simulation. 

I believe your understanding is flawed.
A simulator will only log state if you tell it to.  

Are you displaying waveforms?  This will cause the simulator to log
state.

Regards,
Allan.

>After a very long time, even if the
>simulator clears the RAM and writes the history to the hard disk, the
>simulation will be slow and heavy.
>
>Gilad

Article: 56884
Subject: Re: FPGA to Custom ASIC ??
From: "Ansgar Bambynek" <a.bambynek_xxx_@avm.de>
Date: Wed, 18 Jun 2003 09:43:21 +0200
Links: << >>  << T >>  << A >>
Hi

there are some vendors who offer this kind of service, i.e. you provide them
with a XC netlist and they do the conversion.
Google may help to get some more infos:
http://www.google.de/search?q=fpga+%22design+conversion%22+%22gate+array%22&
hl=de&lr=&ie=UTF-8&oe=UTF-8&start=10&sa=N

BTW I don't have any experience with this kind of service so I can't comment
on the flow nore can I recommend any vendor.

HTH

Ansgar

--
Attention please, reply address is invalid, please remove "_xxx_" ro reply


"Nagaraj" <nagaraj_c_s@yahoo.com> schrieb im Newsbeitrag
news:91710219.0306172121.37274fb1@posting.google.com...
> Hello all,
> I have my prototype design in Spartan IIE 400K -7 device (package
> FT256). As our high volume application is power,size and cost
> oriented, we have to migrate to ASIC.
> Because of time crunch, we are not in a position to follow the entire
> ASIC design flow.
> I want you to suggest some alternatives. One alternative I have in
> mind is this. If Xilinx or 3rd party can take our FPGA design and map
> it to a one-to-one customized ASIC, we can save the time on ASIC flow
> and ASIC verification. What I mean is that start with the FPGA device
> and do these things:
> 1. Remove the unused dedicated resources as well as logic/routing
> resources (for example we are using only 5% of BRAMs. So all other
> BRAMs can be removed)
> 2. Remove IOBs of unused pins and keep only those pins which are in
> use (we are using only 30% of I/O pins.)
> 3. Change the packaging if possible.
>
> My question is whether this kind of service is available with XILINX
> or any other 3rd parties?
> If not could you suggest some other alternative?
>
> Regards,
> Nagaraj CS



Article: 56885
Subject: Re: FPGA GPU (Spartan IIe 300K)
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Wed, 18 Jun 2003 10:44:31 +0200
Links: << >>  << T >>  << A >>

"Bazaillion" <nospam@nospam.org> schrieb im Newsbeitrag
news:kjcvevsik67eb2nhs2vdkl4bbgi1084gm3@4ax.com...
> I forgot to add "With exteral Ram for the Video."

www.fpgaarcade.com

I rebuilded these pacman with a 200k Spartan-II. What it needs are two
external FLASH memories for program and character storage. But if you have
plenty of BRAMS, you can integrate at least on of the two ROMs.
You also need some small adaptors for VGA, audio and joystick. But this is
just some bell wire on a breadboard.

--
Regards
Falk




Article: 56886
Subject: User Electronic Signature in Xilinx XPLA3
From: Martin Sauer <msau@displaign.de>
Date: Wed, 18 Jun 2003 11:31:28 +0200
Links: << >>  << T >>  << A >>
Hello,

do anyone know, which mean the bits in the UES in a Xilinx XPLA3 device 
and how is the text encoded?

Thank you for your answer.

best wishes

martin sauer


Article: 56887
Subject: Tristate
From: kalimuddin@hotmail.com (Muhammad Khan)
Date: 18 Jun 2003 03:15:21 -0700
Links: << >>  << T >>  << A >>
HI Fellows,
The process given below is to read and write to Vertex device ( only
vhdl part is shown here not C ). I want to tristate SR_DATA_IO_int
when not driven as read.
First of all the code below for write and read is correct or not!!!!
SR_DATA_IO_int pins ( which are 32 , I am using upper 7 bits only )
will be acting as bi directional pins. While writing these will take
bits from PCI interface to device and while reading they will exactly
opposite. But while writing I have to tristate SR_DATA_IO_int so as to
avoid short circuiting. Any help on tristate will be highly
appreciated.

process(CLK_2X,SR_ADDR_IO_int,SR_DATA_IO_int,SR_IRD_int,SR_IWR_int,SR_IVCS_V3_int)
begin
if RISING_EDGE(CLK_2X) then
 if SR_IVCS_V3_int = '0' then
  if SR_IWR_int = '0' then
     if SR_ADDR_IO_int = "001100" then
       RESULT <= SR_DATA_IO_int(6 downto 0);
     End if ;
  Elsif  SR_IRD_int = '0' then
    if SR_ADDR_IO_int = "001101" then       
     SR_DATA_IO_int(6 downto 0)<=RESULT ;
    End if;
  End if;
End if;
End if;

Article: 56888
Subject: BCH or Hamming Code
From: vhdl_uk@yahoo.co.uk (MACEI'S)
Date: 18 Jun 2003 03:28:12 -0700
Links: << >>  << T >>  << A >>
Helloe Friend's , 


I am trying to implement simple BCH or Hamming code using VHDL. Any
help regarding material or code will be appreciated. Any web site link
or VHDL code link etc..........
Cheers

Rgds 

Mac's

Article: 56889
Subject: Xilinx ISE is putting this signal assignment in the wrong timing constraint group...
From: "Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk>
Date: Wed, 18 Jun 2003 13:40:35 +0100
Links: << >>  << T >>  << A >>

Hello folks,

I am having some trouble with multi-cycle constraints and ISE considering
some paths in the wrong timing group - I have quoted the relevant VHDL - it
is short and very simple RTL so shouldn't take much to look at I hope   :-)
.  Thanks very much for your time.

I have a signal H1_V_1_P0 that is assigned like this on each rising edge of
CLK:

_______________________________
DeMux_Proc : process (CLK)

 begin

  if (CLK'event and CLK='1') then

   case InputMUX_Cnt is

    when 0 => H1_V_1_P0 <= signed(X);   -- ***********
    when 1 => H0_V_1_P0_D1 <= signed(X);
    when others => H0_V_1_P0_D1 <= (others => '0');

   end case;

  end if;

 end process;
__________________________

then, H1_V_1_P0 is used in the 2nd addition line below to assign the
H1_V_9_P1 signal - this assignment takes place using a clock enable CLKEN
which is enabled every two rising edges of CLK (CLKEN is derived directly
from CLK via a counter).

AssignProc : process (CLK, CLKEN)

 begin

  if (CLK'event and CLK='1') then

   if (CLKEN = '1') then

    H1_V_1_P1 <= H1_V_1_P0;

    -- ***********
    H1_V_9_P1 <= RESIZE((H1_V_1_P0 & "000") + RESIZE(H1_V_1_P0,16),16);

   end if;

  end if;

 end process;

__________________________

I synthesise my code (there is a lot more than the snippets above) in
Synplify 7.2 targetting a xc2v3000fg676-5 and then place and route in ISE
5.2.03i using the following constraints:

NET "CLK*" TNM_NET = "CLK";
TIMESPEC "TS_CLK" = PERIOD "CLK" 4.1 ns HIGH 50 %;
NET "clken*" TNM_NET = "CLKEN";
TIMESPEC "TS_CLKEN" = FROM "CLKEN" TO "CLKEN" "TS_CLK" * 2;

So, CLK is about 240MHz and CLKEN is about 120MHz.

The TS_CLKEN timing constraint analyses 39487 items with no timing errors at
all.

The TS_CLK constraint analyses 1326 items and finds one failing path (full
report at end of message):

===============================================================
Timing constraint: TS_CLK = PERIOD TIMEGRP "CLK"  4.100 nS   HIGH 50.000000
% ;

 1326 items analyzed, 1 timing error detected. (1 setup error, 0 hold
errors)
 Minimum period is   4.441ns.
----------------------------------------------------------------------------
----
Slack:                  -0.341ns (requirement - (data path - clock skew))
  Source:               h1_v_1_p0[3] (FF)
  Destination:          h1_v_9_p1[12] (FF)
_______________________________________

You've guessed it - h1_v_1_p0 to h1_v_9_p1 is failing...

THE BIG QUESTION

Why is this path being considered under the TS_CLK constraint when the
process in which this path belongs (AssignProc) is enabled using CLKEN and
should hence come under the TS_CLKEN constraint?

There are several other processes in the code enabled using CLKEN in the
same manner as the AssignProc process and they are not complaining (and must
be being considerd as being under TS_CLKEN since these processes form the
majority of the code and 39487  items come under TS_CLKEN.

Can anyone shed any light or point me in the right direction?

Thanks very much again for your time,

Ken






START full post par static timing report:

============================================================================
====
Timing constraint: TS_CLK = PERIOD TIMEGRP "CLK"  4.100 nS   HIGH 50.000000
% ;

 1326 items analyzed, 1 timing error detected. (1 setup error, 0 hold
errors)
 Minimum period is   4.441ns.
----------------------------------------------------------------------------
----
Slack:                  -0.341ns (requirement - (data path - clock skew))
  Source:               h1_v_1_p0[3] (FF)
  Destination:          h1_v_9_p1[12] (FF)
  Requirement:          4.100ns
  Data Path Delay:      4.439ns (Levels of Logic = 5)
  Clock Skew:           -0.002ns
  Source Clock:         CLK_c rising at 0.000ns
  Destination Clock:    CLK_c rising at 4.100ns

  Data Path: h1_v_1_p0[3] to h1_v_9_p1[12]
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y20.XQ      Tcko                  0.493   h1_v_1_p0(3)
                                                       h1_v_1_p0[3]
    SLICE_X14Y16.F4      net (fanout=3)        0.509   h1_v_1_p0(3)
    SLICE_X14Y16.COUT    Topcyf                0.755   h1_v_9_p1(3)
                                                       un7_h1_v_9_p1_axb_0
                                                       un7_h1_v_9_p1_cry_0
                                                       un7_h1_v_9_p1_cry_1
    SLICE_X14Y17.CIN     net (fanout=1)        0.000   un7_h1_v_9_p1_cry_1/O
    SLICE_X14Y17.COUT    Tbyp                  0.092   h1_v_9_p1(5)
                                                       un7_h1_v_9_p1_cry_2
                                                       un7_h1_v_9_p1_cry_3
    SLICE_X14Y18.CIN     net (fanout=1)        0.000   un7_h1_v_9_p1_cry_3/O
    SLICE_X14Y18.COUT    Tbyp                  0.092   h1_v_9_p1(7)
                                                       un7_h1_v_9_p1_cry_4
                                                       un7_h1_v_9_p1_cry_5
    SLICE_X14Y19.CIN     net (fanout=1)        0.000   un7_h1_v_9_p1_cry_5/O
    SLICE_X14Y19.COUT    Tbyp                  0.092   h1_v_9_p1(9)
                                                       un7_h1_v_9_p1_cry_6
                                                       un7_h1_v_9_p1_cry_7
    SLICE_X14Y20.CIN     net (fanout=1)        0.000   un7_h1_v_9_p1_cry_7/O
    SLICE_X14Y20.Y       Tciny                 1.257   h1_v_9_p1(11)
                                                       un7_h1_v_9_p1_cry_8
                                                       un7_h1_v_9_p1_s_9
    SLICE_X15Y23.BY      net (fanout=1)        0.827   un7_h1_v_9_p1_s_9
    SLICE_X15Y23.CLK     Tdick                 0.322   h1_v_9_p1(12)
                                                       h1_v_9_p1[12]
    -------------------------------------------------  ---------------------
------
    Total                                      4.439ns (3.103ns logic,
1.336ns route)
                                                       (69.9% logic, 30.1%
route)

----------------------------------------------------------------------------
----
Slack:                  -0.340ns (requirement - (data path - clock skew))
  Source:               h1_v_1_p0[2] (FF)
  Destination:          h1_v_9_p1[12] (FF)
  Requirement:          4.100ns
  Data Path Delay:      4.438ns (Levels of Logic = 4)
  Clock Skew:           -0.002ns
  Source Clock:         CLK_c rising at 0.000ns
  Destination Clock:    CLK_c rising at 4.100ns

  Data Path: h1_v_1_p0[2] to h1_v_9_p1[12]
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y20.YQ      Tcko                  0.493   h1_v_1_p0(3)
                                                       h1_v_1_p0[2]
    SLICE_X14Y17.F2      net (fanout=2)        0.687   h1_v_1_p0(2)
    SLICE_X14Y17.COUT    Topcyf                0.668   h1_v_9_p1(5)
                                                       un7_h1_v_9_p1_axb_2
                                                       un7_h1_v_9_p1_cry_2
                                                       un7_h1_v_9_p1_cry_3
    SLICE_X14Y18.CIN     net (fanout=1)        0.000   un7_h1_v_9_p1_cry_3/O
    SLICE_X14Y18.COUT    Tbyp                  0.092   h1_v_9_p1(7)
                                                       un7_h1_v_9_p1_cry_4
                                                       un7_h1_v_9_p1_cry_5
    SLICE_X14Y19.CIN     net (fanout=1)        0.000   un7_h1_v_9_p1_cry_5/O
    SLICE_X14Y19.COUT    Tbyp                  0.092   h1_v_9_p1(9)
                                                       un7_h1_v_9_p1_cry_6
                                                       un7_h1_v_9_p1_cry_7
    SLICE_X14Y20.CIN     net (fanout=1)        0.000   un7_h1_v_9_p1_cry_7/O
    SLICE_X14Y20.Y       Tciny                 1.257   h1_v_9_p1(11)
                                                       un7_h1_v_9_p1_cry_8
                                                       un7_h1_v_9_p1_s_9
    SLICE_X15Y23.BY      net (fanout=1)        0.827   un7_h1_v_9_p1_s_9
    SLICE_X15Y23.CLK     Tdick                 0.322   h1_v_9_p1(12)
                                                       h1_v_9_p1[12]
    -------------------------------------------------  ---------------------
------
    Total                                      4.438ns (2.924ns logic,
1.514ns route)
                                                       (65.9% logic, 34.1%
route)

----------------------------------------------------------------------------
----
Slack:                  -0.315ns (requirement - (data path - clock skew))
  Source:               h1_v_1_p0[0] (FF)
  Destination:          h1_v_9_p1[12] (FF)
  Requirement:          4.100ns
  Data Path Delay:      4.412ns (Levels of Logic = 5)
  Clock Skew:           -0.003ns
  Source Clock:         CLK_c rising at 0.000ns
  Destination Clock:    CLK_c rising at 4.100ns

  Data Path: h1_v_1_p0[0] to h1_v_9_p1[12]
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y18.YQ      Tcko                  0.493   h1_v_1_p0(1)
                                                       h1_v_1_p0[0]
    SLICE_X14Y16.F1      net (fanout=2)        0.482   h1_v_1_p0(0)
    SLICE_X14Y16.COUT    Topcyf                0.755   h1_v_9_p1(3)
                                                       un7_h1_v_9_p1_axb_0
                                                       un7_h1_v_9_p1_cry_0
                                                       un7_h1_v_9_p1_cry_1
    SLICE_X14Y17.CIN     net (fanout=1)        0.000   un7_h1_v_9_p1_cry_1/O
    SLICE_X14Y17.COUT    Tbyp                  0.092   h1_v_9_p1(5)
                                                       un7_h1_v_9_p1_cry_2
                                                       un7_h1_v_9_p1_cry_3
    SLICE_X14Y18.CIN     net (fanout=1)        0.000   un7_h1_v_9_p1_cry_3/O
    SLICE_X14Y18.COUT    Tbyp                  0.092   h1_v_9_p1(7)
                                                       un7_h1_v_9_p1_cry_4
                                                       un7_h1_v_9_p1_cry_5
    SLICE_X14Y19.CIN     net (fanout=1)        0.000   un7_h1_v_9_p1_cry_5/O
    SLICE_X14Y19.COUT    Tbyp                  0.092   h1_v_9_p1(9)
                                                       un7_h1_v_9_p1_cry_6
                                                       un7_h1_v_9_p1_cry_7
    SLICE_X14Y20.CIN     net (fanout=1)        0.000   un7_h1_v_9_p1_cry_7/O
    SLICE_X14Y20.Y       Tciny                 1.257   h1_v_9_p1(11)
                                                       un7_h1_v_9_p1_cry_8
                                                       un7_h1_v_9_p1_s_9
    SLICE_X15Y23.BY      net (fanout=1)        0.827   un7_h1_v_9_p1_s_9
    SLICE_X15Y23.CLK     Tdick                 0.322   h1_v_9_p1(12)
                                                       h1_v_9_p1[12]
    -------------------------------------------------  ---------------------
------
    Total                                      4.412ns (3.103ns logic,
1.309ns route)
                                                       (70.3% logic, 29.7%
route)

----------------------------------------------------------------------------
----

============================================================================
====
Timing constraint: TS_CLKEN = MAXDELAY FROM TIMEGRP "CLKEN" TO TIMEGRP
"CLKEN" TS_CLK * 2.000 ;

 39487 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold
errors)
 Maximum delay is   8.142ns.
----------------------------------------------------------------------------
----


--
To reply by email, please remove the _MENOWANTSPAM from my email address.



Article: 56890
Subject: Re: FPGA to Custom ASIC ??
From: amit_ashara@hotmail.com (Amit)
Date: 18 Jun 2003 06:03:49 -0700
Links: << >>  << T >>  << A >>
nagaraj_c_s@yahoo.com (Nagaraj) wrote in message news:<91710219.0306172121.37274fb1@posting.google.com>...
> Hello all,
> I have my prototype design in Spartan IIE 400K -7 device (package
> FT256). As our high volume application is power,size and cost
> oriented, we have to migrate to ASIC.
> Because of time crunch, we are not in a position to follow the entire
> ASIC design flow.
> I want you to suggest some alternatives. One alternative I have in
> mind is this. If Xilinx or 3rd party can take our FPGA design and map
> it to a one-to-one customized ASIC, we can save the time on ASIC flow
> and ASIC verification. What I mean is that start with the FPGA device
> and do these things:
> 1. Remove the unused dedicated resources as well as logic/routing
> resources (for example we are using only 5% of BRAMs. So all other
> BRAMs can be removed)
> 2. Remove IOBs of unused pins and keep only those pins which are in
> use (we are using only 30% of I/O pins.)
> 3. Change the packaging if possible.
> 
> My question is whether this kind of service is available with XILINX
> or any other 3rd parties?
> If not could you suggest some other alternative?
> 
> Regards,
> Nagaraj CS

Well what sort of design is in the FPGA. That will decide who can
perform the
coversion for you. If you can let me know the type, i.e is the design
a DSP design, SONET design, ATM design or some bus protocol, then it
can be useful

~Amit

Article: 56891
Subject: Re: BCH or Hamming Code
From: news@sulimma.de (Kolja Sulimma)
Date: 18 Jun 2003 06:48:09 -0700
Links: << >>  << T >>  << A >>
if "row(i)" is a vector that is one row from the code matrix and
"input" is your input vector than a simple implementation is:

for i in 0 to k loop
  output(i) <= XOR_REDUCE(row(i) and input);
end loop;

Of course there are things that you can do to help the synthesis tools
to optimize this code.

Kolja Sulimma

vhdl_uk@yahoo.co.uk (MACEI'S) wrote in message news:<fdfcada5.0306180228.61059bb4@posting.google.com>...
> Helloe Friend's , 
> 
> 
> I am trying to implement simple BCH or Hamming code using VHDL. Any
> help regarding material or code will be appreciated. Any web site link
> or VHDL code link etc..........
> Cheers
> 
> Rgds 
> 
> Mac's

Article: 56892
Subject: Re: Simple FEC algorithm
From: jakespambox@yahoo.com (Jake Janovetz)
Date: 18 Jun 2003 06:56:59 -0700
Links: << >>  << T >>  << A >>
"Kevin Neilson" <kevin_neilson@removethistextattbi.com> wrote in message news:<5uRHa.707321$Si4.827055@rwcrnsc51.ops.asp.att.net>...
> I think a BCH code is somewhat simpler to implement than an RS code.  You
> wouldn't have the burst protection inherent in RS.  A small Hamming code,

Just a slight correction here.  BCH codes are based on the same
algebraic properties of RS codes (RS codes are a special case of BCH
codes) and so the same burst protection is inherent.  The burst
protection comes about because a single error from the code's point of
view is an error in a field element.  The field element is implemented
as an extension of F_2 (binary) and so contains 'm' bits.  Therefore,
any number of bit errors in the same code symbol is considered a
single error.

   Jake

Article: 56893
Subject: Re: Downloading bit-stream with a microprocessor.
From: Peter Wallace <pcw@karpy.com>
Date: Wed, 18 Jun 2003 07:06:03 -0700
Links: << >>  << T >>  << A >>
On Tue, 17 Jun 2003 10:21:44 -0700, rickman wrote:

> Larry Doolittle wrote:
>> 
>> Mark Sandford wrote:
>> > The app note details all of this on with good file format suggestions
>> > on pages 8-9 (reading the manual ussually helps).
>> > http://www.xilinx.com/xapp/xapp098.pdf
>> 
>> That document says:
>>  Because of the difficulty in identifying and removing the title
>>  declaration, the binary (.bit) file created by BitGen is not
>>  recommended for use. Instead, one should use BitGen to create a hex
>>  file, which, in turn, is converted to binary as described in the
>>  preceding section.
>> 
>> I humbly disagree, and have successfully used bit files for my work,
>> using the documentation posted by Alan Nishioka <alann@accom.com> in
>> this group (comp.arch.fpga) on 29 Aug 2001.  Google for "Larry
>> Doolittle JTAG" and you can find my source code. The bitfile processor
>> is buried in virtex.c.
>> 
>>       - Larry
> 
> I prefer to use the bit file when I am working with an MCU since the MCU
> can read the header data which contains such things as the date and file
> name.  Useful for tracking purposes.
 
Using the bit mode has saved me quite a bit of time by being able to check
the compile date of the config file, so I dont try and debug problems 
I've already solved... 

Our downloader determines file type (BIT or BIN -- thanks Phil!) and prints
out the compile name and date if the config file is a BIT file)

PCW

Article: 56894
Subject: Re: XILINX Error Message
From: "pradeep" <pradeep_32@msn.com>
Date: Thu, 19 Jun 2003 00:08:21 +1000
Links: << >>  << T >>  << A >>
|"Marc Guardiani" <marc@guardiani.com> wrote in message
|
| The easiest solution is to turn off "verify" in Impact. Personally, I've
| never been able to verify a Xilinx FPGA.

Yes, programming the xilinx fpga works fine though the "verify" operation
fails.

pradeep.




Article: 56895
Subject: Re: PC-104 dev Boards
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 18 Jun 2003 10:29:31 -0400
Links: << >>  << T >>  << A >>
"H. Peter Anvin" wrote:
> 
> Followup to:  <pan.2003.06.10.14.57.31.384036.42674@karpy.com>
> By author:    Peter Wallace <pcw@karpy.com>
> In newsgroup: comp.arch.fpga
> >
> > Actually I would like to use the latest chips but since the PC/104 bus
> > is 5V that does limit your choices. Sure you can add resistors, CPLDS or
> > other mickey-mousery but that adds cost and complexity.
> >
> > This 5V trouble is also true of PCI cards. There are still _many_ 5V PCI cards
> > around. All you need is one 5V card in a backplane and your 3.3V limited
> > FPGA card is in trouble...
> >
> 
> Quickswitches is the way to deal with that.  They aren't very
> expensive and they handle 5.0<->3.3 V PCI just fine.

Yes, but that is very expensive in terms of board area.  PC/104 is a
very compact format and level converters take up way too much space to
be practical.  I am facing the same problem.  I am planning to use a 5
volt tolerant CPLD if I can get the right pricing.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 56896
Subject: WR/RD Problem
From: fpga_uk@yahoo.co.uk (Isaac)
Date: 18 Jun 2003 07:57:04 -0700
Links: << >>  << T >>  << A >>
Dear Fellows, 

I need help regarding two way data transfer using pin's as inout port
mode. I am trying to write VHDL code for read and write operation.

1) I want my code to do write operation using data bus into device
when particular address ( say X on the address bus)and signal
indicating to do write operation appears.
2) I want to do read operation using the same data bus from device
when particular address ( say Y on the address bus) and signal
indicating to read appears.
To accomplish this I have defined data bus as inout port. There is a
read and write signal ( active low) along with the clock signal.


WRITE:


To start with I am just taking the signal (say INPUT) from DATA bus 
storing in a internal signal ( say INTERNAL) during write operation.
Note: Both signal's have same width.
                   INTERNAL <= INPUT;


READ :
And during read operation I am raeding the same stored signal ( which
is INTERNAL). For this I have just assigned
                         INPUT <= INTERNAL;

Problem:

The problem is that while writing everthing is fine. I can see in my
simulation INTERNAL signal contains the value on the DATA bus. But If
I change the signal values from write to read along with the read
address ( Y), then the INTERNAL signal is not being assigned to INPUT
( data bus acting as inout port).
You can see my code which is giving below:
here case a when '1' then I am doing read operation:	
----------------------------------------------------------------------------

         if Rising_Edge (Clock) then 
		    case a is 
			when '0' =>          -- Write  Operation
			   if Address = "11" then
				INTERNAL <= INPUT;
			   end if;	
			when '1' =>          -- Read Operation  
			   if Address = "01" then
				INPUT <= INTERNAL ;
	        			
			    end if;	
		        when others =>
				Null;
			end case;
------------------------------------------------------------------------------
Also I tried by assigning a constant value to INTERNAL and try to see
the result at the INPUT. But without any success.

Does any one have any idea how to accomplish this task?

Rgds

Isaac

Article: 56897
Subject: Re: FPGA to Custom ASIC ??
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Wed, 18 Jun 2003 08:20:06 -0700
Links: << >>  << T >>  << A >>
Nagaraj,

Xilinx no longer provides ASIC conversions.  We have the EasyPath(tm)
program now that is far superior (for most customers) and has replaced
the older FPGA to ASIC program.

Since yours is a power issue, the EasyPath(tm) program does not provide
any power savings, as it is identical to the FPGA (only the test flow
differs).  EasyPath (tm) does not require any re-qualification, test
vectors, or any other customer engineering (hence its overwhelming
success).

In fact, there has not been a way to convert since the 4K days.

The conversion business was always fraught with problems, so it was
abandoned when Virtex came along.

You would be better off taking the VHDL/Verilog (less any FPGA specific
features or any Xilinx IP) and targeting a standard cell ASIC.

Note that using any Xilinx IP (soft or hard) in anything except our FPGA
is specifically prohibited by our licensing.

As was mentioned, there are other conversion services offered by
companies (including other FPGA companies).  Remember that you are
responsible for a totally synchronous design, with no timing hazards, and
that you must be able to supply all test vectors, and accept total
liability for the results.

Based on the headaches and misery the conversion process entails, I wish
you success.  Make sure you ask for customers that you can talk to for
each prospective service, and interview them on their experience.

The reason why I know about this, is that before I joined Xilinx, I had
to convert two different designs to ASIC.  One was succesful (but we lost
the contract), and the other one had a design flaw and resulted in a
waste of a lot of money (and no chips).

Austin

Nagaraj wrote:

> Hello all,
> I have my prototype design in Spartan IIE 400K -7 device (package
> FT256). As our high volume application is power,size and cost
> oriented, we have to migrate to ASIC.
> Because of time crunch, we are not in a position to follow the entire
> ASIC design flow.
> I want you to suggest some alternatives. One alternative I have in
> mind is this. If Xilinx or 3rd party can take our FPGA design and map
> it to a one-to-one customized ASIC, we can save the time on ASIC flow
> and ASIC verification. What I mean is that start with the FPGA device
> and do these things:
> 1. Remove the unused dedicated resources as well as logic/routing
> resources (for example we are using only 5% of BRAMs. So all other
> BRAMs can be removed)
> 2. Remove IOBs of unused pins and keep only those pins which are in
> use (we are using only 30% of I/O pins.)
> 3. Change the packaging if possible.
>
> My question is whether this kind of service is available with XILINX
> or any other 3rd parties?
> If not could you suggest some other alternative?
>
> Regards,
> Nagaraj CS


Article: 56898
Subject: Re: Cyclone vs. Acex consumption?
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 18 Jun 2003 11:45:22 -0400
Links: << >>  << T >>  << A >>
Iode wrote:
> 
> Hi to everyone,
> 
> Has anyone had experience porting a design from Acex to Cyclone? What should
> I expect from the point of view of power consumption? Using the calculator
> tools give worrying results: comparing a c30 with a 1k50 I have 33.5mA of
> standby current for Cyclone, 5 mA for Acex; I/Os consumption also seems to
> be higher in Cyclone; core consumption seems to be less but, all in all, am
> I going to need more or less power using Cyclone?
> 
> Perhaps less power while the clock is running but more power when in
> stand-by?

I am very glad you posted this question.  I had been looking at using a
CPLD in this design for the PC/104 bus interface, but all of the parts I
was considering had limitations.  But the ACEX 1K parts seem to meet all
the needs and are still relatively low power.  5 mA standby is better
than some of the CPLDs!  I estimated a max power consumption of 40 mA
running at 50 Mhz so this part hangs in there with the CPLDs in terms of
dynamic power as well.  

If I can get a decent price, this part will solve a lot of my problems.  

BTW, I suggest that you call Altera support at 800-800-3753.  I have
found them to be very helpful and they even answer the phone fairly
quickly.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 56899
Subject: Re: XCV 6000 data sheets
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 18 Jun 2003 08:55:54 -0700
Links: << >>  << T >>  << A >>
It was called XC6200, and is long dead.
Why do you need a data sheet. (I think it can be found, but before I
start a hunt I want to know why)

Peter Alfke
=====================================
Prashant wrote:
> 
> Hi,
> 
> I have been unable to find a data sheet for the XCV6000 device. Have I
> got the number wrong ? Does such a device exist ? If so, where can I
> find a data sheet for this device.
> 
> Thanks,
> Prashant



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