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Philip, reason being that the project I'm undertaking requires me to edit .bit files, and I understand that the way to do that is to use bitgen to produce .rbt version of the .bit files. I have code that takes in .bit files to configure the FPGA, but not .rbt files. Hence, I'm wondering if there is a way to convert rbt to bit through some utility already available or by coding a program to do that. One other alternative I think would be to use iMPACT to configure the FPGA using rbt files? I just came across documentation stating this can be done, although I have not tried it myself. I'm using Virtex XCV1000. Philip Freidin <philip@fliptronics.com> wrote in message news:<u62afv4tgl8f0va5jf5lqs8todblcvcu5m@4ax.com>... > On 21 Jun 2003 16:55:04 -0700, panjuhwa_fpga@yahoo.com (PanJuHwa) wrote: > >Hi, > > > > how do we do that? Is it possible to code using Java? > > > > Thanks > > Why would you want to do this? The same program (bitgen) generates > both files. If you can get one, you can get the other. > > Philip > > Philip Freidin > FliptronicsArticle: 57051
Spelling. "John K." <jonnykwtb@aol.com> wrote in message news:MPG.195faff69124b5e6989b57@News.CIS.DFN.DE... > > Hi, > sorry if this question has already been asked millions times. :P > > What's the difference between ASIC and FPGA? > > Thanks, > JohnArticle: 57052
Naveed wrote: > So I thought, why use TCP/IP? You can talk to just Ethernet to > Ethernet. Has anybody ever implemented "Ethernet only" solution using > Windows? How do sniffer guys do it by talking directly to NIC? They seem to use the NDIS interface via packet32.dll.. See: http://www.cswl.com/whiteppr/white/ethernet.html KarstenArticle: 57053
> "John K." <jonnykwtb@aol.com> wrote in message > news:MPG.195faff69124b5e6989b57@News.CIS.DFN.DE... > > > > Hi, > > sorry if this question has already been asked millions times. :P > > > > What's the difference between ASIC and FPGA? An ASIC is Application Specific IC. Made for a single application. And very expensive to design up front. An FPGA is not application specific, in that the makers don't know what it will be made to do when the customer buys it. Less efficient use of silicon, but cheaper to design up front.Article: 57054
Followup to: <3EF3878C.ED5CA05C@yahoo.com> By author: rickman <spamgoeshere4@yahoo.com> In newsgroup: comp.arch.fpga > > > > Right. I was stating PC-104+ in every single message. > > I see now that you mentioned in the middle of a message that you were > not using the ISA signals. I missed that. > > I can see that it could be a better way to handle the PCI interface. > But it still depends on where the IO count pushes your part selection. > If you can accommodate the extra IOs on the large FPGA then this can be > a better way to do it. If you need to go to a larger chip, it can be > very pricey compared to adding a smaller FPGA. > > I am curious, do the switch parts you chose meet all the PCI bus > requirements when used with a low voltage FPGA? I know the IO specs on > PCI are very particular on rise time and waveform specs. Typically it > requires that the IO on a chip be spec'd for the application. Were you > able to confirm that this combination meets the spec? And what FPGA are > you using? > Let's put it this way... I've seen these chips used on quite a few boards which need 5.0<->3.3V conversion, and I have never had any problems with any cards (either PC-104+ or card edge PCI) because of it. The FPGA is an APEX 20K device... it's a bit of an older board. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 57055
hi, I need to design vga controller on virtex II fpga. I would like to know how to solve problem accessing video ram (SDRAM in this case) by processor(write access) and vga unit (read) at the same time. Processor can only access VRAM during blanking interval, when vga unit does not read pixel information. I designed text mode with no problems using virtex dual port RAM, but what to do with SDRAM? thx mk -- Serwis Usenet w portalu Gazeta.pl -> http://www.gazeta.pl/usenet/Article: 57056
Basuki Endah Priyanto <EBEPriyanto@ntu.edu.sg> wrote: : Hi, : Anybody can give me more detailed explaination on the following message : : : WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net : iuser_ap_my_trans_i3_i6__n0049 is sourced by a combinatorial pin. : This is not : good design practice. Use the CE pin to control the loading of data : into the : flip-flop. : What is the implication if I just ignore the warning message ? The implication: Your design may or may not work.... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 57057
Hi all, I posted a new project, quadrature decoder in an FPGA. http://www.fpga4fun.com/QuadratureDecoder.html Next week will be a pong game using the quadrature decoder. Have fun! JeanArticle: 57058
Thanks Karsten, That is exactly what I was looking for. Excellent article.Article: 57059
You only need tristate, if there are more than one drivers on one pin. If there is only one driver, you can read and write that pin anytime without tristating. If the pin has been written by just one driver, then you will read back the driven value. But why do you want to read back the value that you just wrote yourself? May be you want to turn off your driver, so somebody else can put their data, that you can read?? In that case, you will have to tristate your driver (writer), so you can read without conflict. Does that answer your question? vhdl_uk@yahoo.co.uk (MACEI'S) wrote in message news:<fdfcada5.0306200348.7bb4c499@posting.google.com>... > Hi fellow, > If I have input port which is bidirectional and I have used this bus > to write into device and thi bus still has signal on it's pins. Now at > this moment if I want to read from same bus then it is possible to do > it or not. What would happen to the signal which is already on the bus > as a result of write operation. > DO I need to tristate the bus just after write and then perform read > operation? > > Rgds > Macei'sArticle: 57060
Has anybody ever implemented off the shelf PC2100/3200 DDR module with Cyclone? Can Cyclone support 64-bit interface with standard modules?Article: 57061
You might also want to have a look at ethereal (www.ethereal.com). It's a program that's handy for monitoring (ethernet) traffic. You could also use UDP instead of TCP. Implementing UDP is easy. And then you don't need to use (or write) any special drivers. If you use fixed IP<->MAC addresses, then you don't even need to implement ARP or anything either. Although e.g. IGMP would be handy, then you can just ping to a card to see if you connection is still OK. Regards, Marc "Naveed" <visualfor@yahoo.com> wrote in message news:864a80dc.0306220410.20d48e21@posting.google.com... > Hello guys, > > I have a multiple card system (56 cards), where I download a huge > amount of data (~500MB) to each card from PC. I have been using > parallel NI "DIO" bus to do that, But it's slow and need very careful > termination to work. > > I have been thinking about using cheap gigabit Ethernet solution. I > have Altera's cyclone 1C6 on cards. I can buy gigabit Ethernet > MAC+PHY for less than $15, then I can do rest of the processing inside > the FPGA. The problem is that 1C6 is not big enough to implement the > TCP/IP stack inside (no external memory to store instruction). > > So I thought, why use TCP/IP? You can talk to just Ethernet to > Ethernet. Has anybody ever implemented "Ethernet only" solution using > Windows? How do sniffer guys do it by talking directly to NIC? > > Just looking for big picture here. Any help is appreciated.Article: 57062
I only do FPGA designs and know little about ASIC. >From my point of view: for RTL design FPGA has its own global resources like GCK, so you needn't a clock tree while ASIC does. also in ASIC you should buy or design the DLL or other library available in FPGA. for PAR design you just hit the "implement" button when using FPGA. but you need a foundry to complete your ASIC design. just FYI "John K." <jonnykwtb@aol.com> 写入消息新闻 :MPG.195faff69124b5e6989b57@News.CIS.DFN.DE... > > Hi, > sorry if this question has already been asked millions times. :P > > What's the difference between ASIC and FPGA? > > Thanks, > JohnArticle: 57063
Hi Naveed,
According to the Cyclone Device Handbook
(http://www.altera.com/literature/lit-cyc.html), Section V, Chapter 10,
Cyclone supports DDR signaling at up to 133 Mhz, or DDR266. That
corresponds to "PC2100" signaling.
As for interfacing with SDRAMs, we offer a DDR SDRAM controller MegaCore for
SDRAM interfaces, but I don't know if it supports PC DIMMs out of the box.
On top of this, according to the online documentation, Cyclone supports <=48
bits data width, suggesting you are out of luck for the 64-bit and 72-bit
DIMMs in use in PCs. Note: this document lists the speed of operation as
preliminary and awaiting characterization, but then again, it hasn't been
updated since March. You're best off asking for the latest status by filing
a case with http://mysupport.altera.com. They will be happy to answer all
of your questions.
But from what I can tell (see below) it looks like if you want to use
Cyclone, you won't be able to use PC-style DIMMs.
******* Warning: I knew nothing about DDR before tonight; read at your own
risk ;-) ******
Here's what I found in a quick scan of the JEDEC spec on PC DDR DIMMs: A
64-bit DDR DIMM has the following pins:
18 address/bank select pins
64 data pins
7 various strobe/select/enable
8 byte-masks
8 data strobes
6 clocks? (not so sure about this one -- looks like three differential
clocks, but all three may be the same)
plus some EEPROM control (SPD stuff, I imagine) and a bunch of power pins.
That makes for ~111 "user pins" in FPGA speak out of the 168 pins on the
package. The 1C6 has 185 pins, so from that perspective you look ok.
However, Cyclone has a set special DQS pin that has a delay chain for
producing the shifting version of the DQS signal. You need one DQS signal
per byte of data -- and the number of DQS pins is limited to 3-4 in some
Cyclone devices, and 8 in the rest (see table in I/O Structure section of
Chapter 2 in Cyclone Handbook). So that gives you a theoretical limit of 64
bits (or 72 bits with parity) of DDR data in a Cyclone 1C4, 1C12, or 1C20.
The 1C6 tops out at 32- (or 36-) bits.
I'm not sure what tops us out at 48-bits in the bigger Cyclone members --
I've fired a question of to the relevant design guys.
Regards,
Paul Leventis
Altera Corp.
"Naveed" <visualfor@yahoo.com> wrote in message
news:864a80dc.0306221557.21ad98ba@posting.google.com...
> Has anybody ever implemented off the shelf PC2100/3200 DDR module with
> Cyclone? Can Cyclone support 64-bit interface with standard modules?
Article: 57064In datasheet Vcco ranges from -0.5 to 4.0 V. but in Xilinx Constraints Editor, the option for IOSTANDARD only has several levels: LVCMOS15,18,25,33 So what will happen if I set the IOSTANDARD LVCMOS25 and connect 2.9V to the Vcco?Article: 57065
Paul Leventis wrote: > Hi Naveed, > > According to the Cyclone Device Handbook > (http://www.altera.com/literature/lit-cyc.html), Section V, Chapter 10, > Cyclone supports DDR signaling at up to 133 Mhz, or DDR266. That > corresponds to "PC2100" signaling. > > As for interfacing with SDRAMs, we offer a DDR SDRAM controller MegaCore for > SDRAM interfaces, but I don't know if it supports PC DIMMs out of the box. > On top of this, according to the online documentation, Cyclone supports <=48 > bits data width, suggesting you are out of luck for the 64-bit and 72-bit > DIMMs in use in PCs. Note: this document lists the speed of operation as > preliminary and awaiting characterization, but then again, it hasn't been > updated since March. You're best off asking for the latest status by filing > a case with http://mysupport.altera.com. They will be happy to answer all > of your questions. > > But from what I can tell (see below) it looks like if you want to use > Cyclone, you won't be able to use PC-style DIMMs. > > ******* Warning: I knew nothing about DDR before tonight; read at your own > risk ;-) ****** > > Here's what I found in a quick scan of the JEDEC spec on PC DDR DIMMs: A > 64-bit DDR DIMM has the following pins: > 18 address/bank select pins > 64 data pins > 7 various strobe/select/enable > 8 byte-masks > 8 data strobes > 6 clocks? (not so sure about this one -- looks like three differential > clocks, but all three may be the same) > > plus some EEPROM control (SPD stuff, I imagine) and a bunch of power pins. > That makes for ~111 "user pins" in FPGA speak out of the 168 pins on the > package. The 1C6 has 185 pins, so from that perspective you look ok. > > However, Cyclone has a set special DQS pin that has a delay chain for > producing the shifting version of the DQS signal. You need one DQS signal > per byte of data -- and the number of DQS pins is limited to 3-4 in some > Cyclone devices, and 8 in the rest (see table in I/O Structure section of > Chapter 2 in Cyclone Handbook). So that gives you a theoretical limit of 64 > bits (or 72 bits with parity) of DDR data in a Cyclone 1C4, 1C12, or 1C20. > The 1C6 tops out at 32- (or 36-) bits. > > I'm not sure what tops us out at 48-bits in the bigger Cyclone members -- > I've fired a question of to the relevant design guys. > > Regards, > > Paul Leventis > Altera Corp. > > > "Naveed" <visualfor@yahoo.com> wrote in message > news:864a80dc.0306221557.21ad98ba@posting.google.com... > >>Has anybody ever implemented off the shelf PC2100/3200 DDR module with >>Cyclone? Can Cyclone support 64-bit interface with standard modules? > > > Haven't used the DDR support in Cyclone yet. Am planning on using it in a project later this year. Anyway, the EP1C6 seem to be able to drive everything but the 64bit data bus, so I was planning on burning half the module, ie. only use 32bit data. SO-DIMM DDR modules are so cheap I don't mind paying for a 256MB module to get 128MB (128MB is still more than I need anyway), also, you can give away some addressing (ie. only drive enough address lines to drive 512MB) and with a little buffering on the FPGA you can probably ditch the byte mask lines and make all reads bus width (32 bit). This should get the pin budget under 70 pins, still give you ~1GBps peak theoretical transfer (more like 300-400MBps probably, though I haven't worked the numbers and this could be much worse), and allow you to use cheap commodity memory. As I said, untried, but I haven't read anything so far to discourage me. -CarlArticle: 57066
> hi, > I need to design vga controller on virtex II fpga. I would like to know > how to solve problem accessing video ram (SDRAM in this case) by > processor(write > access) and vga unit (read) at the same time. Processor can only access > VRAM during blanking interval, when vga unit does not read pixel > information. I designed text mode with no problems using virtex dual port > RAM, but what to do with SDRAM? > thx > > mk > I would (and did in an experimental design) use a small cache for the VGA core accessing the RAM. It's read-only, mostly linear access, so even a FIFO should suffice. You stuff the FIFO from the SDRAM as fast as you can and read that with precise timing for display. You need an arbiter between the CPU and the FIFO-stuffing function for RAM accesses but the CPU can access the RAM (almost) whenever it wants. The arbiter should give high-pri access to the CPU when the FIFO is almost full and to the stuffing function when the FIFO is almost empty. You should make your FIFO long enough to store a complete scanline of data so you can even out the blanking intervals and really use up only the average data-rate your VGA core needs. There's another trick you can use for low-res modes: under 400 lines of resolution (320x200, 320x240 etc.) every scan-line is doubled on the screen so the actual resolution is 320x400 or 320x480 respectively. The first and the second scan-line are read from the same memory locations so as the 3rd and 4th and so on. Now, for these modes, you can setup another FIFO, that can store another scan-line worth of data and feed that to the timing part of your core for the second rescan. Since this double-trace mode is used only in low-res, the FIFO you need for this second functionality should fit into one or at most two BRAMs. That would effectively halven your data-rate needs (in low-res) and also make the read from the RAM for the VGA core really sequential. If you employ this functionality, your FIFO-stuffing function is a simple counter generating the addresses, that resets at the end of the active display area. Regards, Andras TantosArticle: 57067
"m." <mikel262@gazeta.pl> wrote: > I need to design vga controller on virtex II fpga. I would like to know how > to solve problem accessing video ram (SDRAM in this case) by processor(write > access) and vga unit (read) at the same time. Processor can only access > VRAM during blanking interval, when vga unit does not read pixel > information. I designed text mode with no problems using virtex dual port > RAM, but what to do with SDRAM? You setup two (or more) logical banks. One bank is being displayed (read) while the other bank/s are available for writing. When ready, you simply flip the banks during vertical. That's the basics. From there on you have architectural choices to make: Do you use a wide and fast bus to a single physical SDRAM buffer (one SDRAM controller) or do you implement two physical SDRAM banks with the requisite controllers (one per physical bank). The first is more complex in that you'll need to service all I/O needs through a single bus interface, so control becomes a bit more involved (not terribly though). Additionally, for better performance you might have to write a much more sophisticated SDRAM controller than the garden variety controllers you'll find out there. The goal is to make use of command pipelining and some predictive control (look ahead) in order to maximize bus utilization. The second approach has simpler control but eats-up more resources as well as I/O pins on the FPGA. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 57068
Hi, I wanna do partial reconfiguration on Virtex II Pro, does anybody know if JBits supports V2P ? Thx in advance. tkArticle: 57069
On Sun, 22 Jun 2003 22:19:00 GMT, "Jean Nicolle" <j.nicolle@sbcglobal.net> wrote: >Hi all, > >I posted a new project, quadrature decoder in an FPGA. >http://www.fpga4fun.com/QuadratureDecoder.html This seems to be a straightforward translation of some VHDL I posted in 1998. Allan.Article: 57070
John K. <jonnykwtb@aol.com> wrote: > sorry if this question has already been asked millions times. :P Google might help for such questions (if teacher can't). > What's the difference between ASIC and FPGA? ASIC (Aplication Specific IC) is a design, made for a specific purpose. FPGA is a programmable device which could be used for an ASIC. Fpga may be one time programmable (e.g. most Actel devices) or many times (eg. most Xilinx and Altera devices) Normaly you say ASIC when you mean Cell Based Design. Under that context it's true to say an ASIC could be more complex as a FPGA and achieve higher performance while an FPGA is much easier and cheaper for small amount of needed IC. In the last two years we saw, that FPGAs come more and more to the edge of technologie, meaning the technological gap between cellbased and FPGA is getting smaller. In some places you could say, that FPGAs are getting technological advanced against cellbased. bye ThomasArticle: 57071
I came across a CPU which uses MIPS instruction set. I know that current trend is towards ARM, may I know, how was the popularity and how is prosperity of MIPS? Who uses MIPS? What are the areas that MIPS processors most likely to use? Thanks. Kelvin.Article: 57072
How do you recompile the libraries for ModelSim 5.7? all the libs I found at for 5.6 I tried to ask modelsim to rebuild them, but there are lots of errors. I tried the tcl script on xilinx's ftp, as a result it goes for a while and then modelsim just crashes and quits...Article: 57073
The newer versions of ISE come with a compile tool named compxlib. You can compile your modelsim libraries e.g. with compxlib -s mti_se -f all -l all -o c:\modeltech_5.7c\xilinx_libs There is somewhere a xilinx answer on this topic. Hope this helps, Best, MatthiasArticle: 57074
Hi, I had a project which is targeted to XCV800. That time the number of equivalent gate count is around 350K. Now, I change the target chip to XC2V6000. After I run map process, I found that the number of equivalent gate becomes 800K. Any comment from those who got the same experience or any xilinx ppl here ? Thanks. Rgds, Basuki
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