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"Jay" <yuhaiwen@hotmail.com> schrieb im Newsbeitrag news:bd5rdl$pa41j$1@ID-195883.news.dfncis.de... > So what will happen if I set the IOSTANDARD LVCMOS25 and connect 2.9V to the > Vcco? The output will swing between 0V and 2.9V. Iam not sure what the input threshold will be, since on some families the input buffers are powered by VCCint??! -- Regards FalkArticle: 57076
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:CowJa.413$BE3.33739899@newssvr15.news.prodigy.com... > "m." <mikel262@gazeta.pl> wrote: > > > I need to design VGA controller on Virtex II FPGA. > > I would like to know how to solve problem > > accessing video ram (SDRAM in this case) by > > processor(write access) and VGA unit (read) > > at the same time. Processor can only access > > VRAM during blanking interval, when VGA unit does not read pixel > > information. > You set-up two (or more) logical banks. One bank is being displayed (read) > while the other bank/s are available for writing. When ready, you simply > flip the banks during vertical. I'm guessing the CPU is restricted to blanking because the VRAM bus is used by the VGA circuit. If so, multiple banks (logical or physical) won't help because they would also need the VRAM bus. It's a well known problem. Some machines just gave the CPU priority and had screen 'snow' if access was not limited to blanking. Others used cunning circuits to avoid CPU access disrupting VDU access. Typically Z80 machines did this, and I think most VGA cards do. Yet others used CPU/VDU interleaved access. The CPU and VDU ran at identical rates but 180 degrees out of phase. The VRAM being accessed twice per cycle: once for the CPU and once for the VDU. Typically 6502 machines did this, as their bus cycles were very regular. The latter technique has pros and cons. The pros being that you can use a single memory instead of separate memories. The cons being that the RAM has to work twice as fast as the CPU, and the CPU/VDU cycle rates are tied together. There's also a lot of bus multiplexing but if this is done inside the FPGA there is no cost in PCB complexity. See an example system at: http://www.howell1964.freeserve.co.uk/logic/acorn_atom_project.htmArticle: 57077
"kryten_droid" <kryten_droid@ntlworld.com> wrote: > > You set-up two (or more) logical banks. One bank is being displayed > (read) > > while the other bank/s are available for writing. When ready, you simply > > flip the banks during vertical. > > I'm guessing the CPU is restricted to blanking because the VRAM bus is used > by the VGA circuit. > > If so, multiple banks (logical or physical) won't help because they would > also need the VRAM bus. > > It's a well known problem. I wasn't thinking VRAM at all. I have a board running right now (at 8x VGA resolution) that uses the same sort of technique. Available memory I/O throughput is substantially greater than the combined input and output data rate requirements (including housekeeping). Therefore, with appropriate FIFO's on the I/O, each side "thinks" it has it's own memory bank. Vertical bank switching is done when both sides agree that it is appropriate. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 57078
Hi Carl, Sounds like that should work. The only limitation in Cyclone appears to be data width, which you are side-stepping by tying off some of the data inputs. Are SO-DIMM or DIMM modules that much cheaper than using DDR SDRAM chips directly on your board? If you take that approach, you can build a x32 memory sub-system without needing to waste any memory, but I guess you loose the advantage of replaceable/expandable memory. - Paul > Haven't used the DDR support in Cyclone yet. Am planning on using it in > a project later this year. > > Anyway, the EP1C6 seem to be able to drive everything but the 64bit data > bus, so I was planning on burning half the module, ie. only use 32bit > data. SO-DIMM DDR modules are so cheap I don't mind paying for a 256MB > module to get 128MB (128MB is still more than I need anyway), also, you > can give away some addressing (ie. only drive enough address lines to > drive 512MB) and with a little buffering on the FPGA you can probably > ditch the byte mask lines and make all reads bus width (32 bit). > > This should get the pin budget under 70 pins, still give you ~1GBps peak > theoretical transfer (more like 300-400MBps probably, though I haven't > worked the numbers and this could be much worse), and allow you to use > cheap commodity memory. > > As I said, untried, but I haven't read anything so far to discourage me. > > -Carl >Article: 57079
but, what if I want to draw for eg. a line, and after that i want to add another line on the screen later? When I switch banks (after first line was drawn) the first line will "dissapear", because memory of bank1 is filled only with data of second line. mike Użytkownik "Martin Euredjian" <0_0_0_0_@pacbell.net> napisał w wiadomości news:SRBJa.429$zL4.37792923@newssvr15.news.prodigy.com... > "kryten_droid" <kryten_droid@ntlworld.com> wrote: > > > > You set-up two (or more) logical banks. One bank is being displayed > > (read) > > > while the other bank/s are available for writing. When ready, you > simply > > > flip the banks during vertical. > > > > I'm guessing the CPU is restricted to blanking because the VRAM bus is > used > > by the VGA circuit. > > > > If so, multiple banks (logical or physical) won't help because they would > > also need the VRAM bus. > > > > It's a well known problem. > > I wasn't thinking VRAM at all. I have a board running right now (at 8x VGA > resolution) that uses the same sort of technique. Available memory I/O > throughput is substantially greater than the combined input and output data > rate requirements (including housekeeping). Therefore, with appropriate > FIFO's on the I/O, each side "thinks" it has it's own memory bank. Vertical > bank switching is done when both sides agree that it is appropriate. > > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > > -- Serwis Usenet w portalu Gazeta.pl -> http://www.gazeta.pl/usenet/Article: 57080
Jay, The IO drive will be slightly weaker than it would be at 3.3V. This can actually be modeled fairly well using the IBIS models, and setting Vcco=2.9V (or whatever). Austin Jay wrote: > In datasheet Vcco ranges from -0.5 to 4.0 V. > but in Xilinx Constraints Editor, the option for IOSTANDARD only has several > levels: LVCMOS15,18,25,33 > > So what will happen if I set the IOSTANDARD LVCMOS25 and connect 2.9V to the > Vcco?Article: 57081
On Mon, 23 Jun 2003 17:39:44 +0800, Basuki Endah Priyanto wrote: > Hi, > > I had a project which is targeted to XCV800. That time the number of > equivalent gate count is around 350K. Now, I change the target chip to > XC2V6000. After I run map process, I found that the number of equivalent > gate becomes 800K. > > Any comment from those who got the same experience or any xilinx ppl > here ? > > > Thanks. > > Rgds, > > Basuki Equivalent gate counts are for amusement only, you shouldn't take them to seriously. If you were designing an ASIC you would have made very different design choices based on the different relative values of components. Also the gate counter is probably assigning treating every component as if it were fully utilized even if it's not. For example does your design use block RAMs?. The block RAMs in the XCV800 were 4K, in the XC2V6000 they are 18K. Assuming that the synthesis tool just substituted 18K RAMs for 4K RAMs, that alone would account for the jump in equivalent gate count.Article: 57082
Hello All: I'm working on an old PCB design from a piece of test equipment and I'm looking to replace a bunch of old logic chips with a single PLD/FPGA. The only chip I'm having trouble reproducing the behavior for is the delay line. It's somewhat of a special part. It's a 10 bit programmable line that steps in 1 ns increments and has an initial prop. delay of 6 ns. Also, like most delay lines, it isn't clock driven. I've read about a fairly straight-foward method of using a counter with an overflow bit to create a delay, but the problem is the step size. Since I need 1 ns steps I'd have to drive the counter with a 1 Ghz clock which seems a little impractical for this circuit. If you guys have any suggestions as to how I might pull this off I'd really appreciate it. Thanks in advance! -Erik BoltonArticle: 57083
Iam using Prallel cable IV to download jedec file to the XC95144 . The cable Cable connection established correctly , and the device is Identified correctly , i can Perform blank check on device, and it's completed successfully. but when i am trying to read back or program i got an error . when i tried to readback i got error : ERROR:Portability:90 - Command line error: Unexpected argument[5] "and" found. and the error : ERROR:iMPACT:514 - One of the options for this operation is invalid,please choose different options.Article: 57084
PanJuHwa wrote: > > Philip, reason being that the project I'm undertaking requires me to > edit .bit files, and I understand that the way to do that is to use > bitgen to produce .rbt version of the .bit files. I have code that > takes in .bit files to configure the FPGA, but not .rbt files. Hence, > I'm wondering if there is a way to convert rbt to bit through some > utility already available or by coding a program to do that. > > One other alternative I think would be to use iMPACT to configure the > FPGA using rbt files? I just came across documentation stating this > can be done, although I have not tried it myself. I'm using Virtex > XCV1000. If you are hand editing .bit files, why not do that directly using a hex editor? If I understand correctly, the .rbt file is just a format where one character in the .rbt is one bit in the .bit file. With a hex editor such as Codewright or similar, you can edit the bit file bytes as hex digits. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57085
Erik Bolton wrote: > > Hello All: > > I'm working on an old PCB design from a piece of test equipment and > I'm looking to replace a bunch of old logic chips with a single > PLD/FPGA. The only chip I'm having trouble reproducing the behavior > for is the delay line. It's somewhat of a special part. It's a 10 > bit programmable line that steps in 1 ns increments and has an initial > prop. delay of 6 ns. Also, like most delay lines, it isn't clock > driven. I've read about a fairly straight-foward method of using a > counter with an overflow bit to create a delay, but the problem is the > step size. Since I need 1 ns steps I'd have to drive the counter with > a 1 Ghz clock which seems a little impractical for this circuit. If > you guys have any suggestions as to how I might pull this off I'd > really appreciate it. Thanks in advance! > > -Erik Bolton I think the easy answer is *don't try*. It is very hard to implement delay lines in generic PLDs. The problem is that max delays are spec'd, but the chip maker can not guarantee that the chip won't be faster... *lots* faster than the spec. So your 1 nS delay could be anywhere between 1 nS and 0.2 nS. Normally delay lines are used to time DRAMs. Since DRAMs are getting harder to find, why not redesign the board for SDRAM which will eliminate the need for the delay line altogether? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57086
"Leon Heller" <leon_heller@hotmail.com> wrote in message news:<bct7s7$plb$1@hercules.btinternet.com>... > "Christopher" <blackpack3000@yahoo.com> wrote in message > news:a993b408.0306181714.75e51d4e@posting.google.com... > > Hi! > > > > Does anyone know or have used the Quartus II? If so, I am looking for > > an inexpensive FPGA such that I can build a cable to communicate with > > the chip directly. I don't want to purchase the programmer. Some of > > these kits are $150. I am on a budget and just want to get my feet > > wet. > > I've got the PCB design files for my version of the ByteBlaster on my web > site. > > Leon Apparentl;y, there is a newer version of the Byteblaster parallel cable, do you have any information or circuits on this?? thanks tedArticle: 57087
On Mon, 23 Jun 2003 11:29:37 +0200, Matthias Dyer <m.dyer@switzerland.org> wrote: > The newer versions of ISE come with a compile tool named compxlib. You > can > compile your modelsim libraries e.g. with > > compxlib -s mti_se -f all -l all -o c:\modeltech_5.7c\xilinx_libs > > There is somewhere a xilinx answer on this topic. > > Hope this helps, > > Best, Matthias > great, thanks! where does it get the source though? I am a bit confused by the library system. I got the ISE update, I also got the IP update from Xilinx; Where are the sources, etc? (I'm confused by what it what, etc)Article: 57088
Hi All, working for the verification team of my company, we are using vertexII fpga's to emulate asic designs. I am currently looking in to simulating the result from synplifier with ncsim to be able to reproduce a suite of simulation done on the asic. we have the following setup: - ncsim on UNIX - synplify pro 7.2 on PC - ISE5.1 xilinx software on PC Looking on application note and forum,I understand I need to compile the xilinx library using the compxlib utility, but when I do that I go the a message telling me that compilation of the library for ncsim cannot be done with windowsNT. The command I execute is: compxlib -s ncsim -f virtex2 -l all -o c:\comp_lib and the message : Release 5.1i - compxlib NOTE:compxlib[cmd]:0 - library compilation for ncsim not supported on windows-NT has anybody encountered such situation/problem ? could it be a problem of environement setup in Windows ? or is it not possible to do this with the setup we have ? Thanks in advance BernardArticle: 57089
Well, I wasn't aware of your posting, but looks like we came to the same conclusions. Do you have a link to your post? Jean "Allan Herriman" <allan_herriman.hates.spam@agilent.com> wrote in message news:7k9dfvcak1nqs07rn6khdqdtjulot80sf8@4ax.com... > On Sun, 22 Jun 2003 22:19:00 GMT, "Jean Nicolle" > <j.nicolle@sbcglobal.net> wrote: > > >Hi all, > > > >I posted a new project, quadrature decoder in an FPGA. > >http://www.fpga4fun.com/QuadratureDecoder.html > > This seems to be a straightforward translation of some VHDL I posted > in 1998. > > Allan.Article: 57090
Is this a schematic design? Check the fitter report to see if sw1_ibuf is the top level port name. I suspect that sw1_ibuf may be the name that you applied to the net driven by the IBUF in the design. Name the net between the pad and the input of the IBUF and use that for your Schmitt trigger constraint.Article: 57091
Make sure that you aren't pointing to a Jedec file (or writing to a location) that is contains a directory with spaces (for example: c:\program files\xilinx).Article: 57092
Hi- I'm currently in the process of creating a synthesizable Verilog F/S I2C slave, but have little experience with I2C in the real world. I'm reading the specs, and I feel I'm getting a pretty good understanding. If I'm getting this right, the SDA line will only change when the SCL line is low - except when the master is indicating a START or STOP command. So the question I have for those who have really done this is - in the real world, could a master (or series of masters) issue a STOP command followed by a START command - all on the same SCL high period. The latest I2C spec doesn't explain whether or not this could happen. This is key to me, since I'm trying to create an I2C slave that runs solely off the SDA and SCL signals. Whether or not I have to deal with START and STOP on the same SCL high period will impact the design choice I make. Thanks in advance.Article: 57093
"y_p_w" <y_p_w@hotmail.com> wrote in message news:591da479.0306230937.42883d68@posting.google.com... > Hi- > > I'm currently in the process of creating a synthesizable Verilog > F/S I2C slave, but have little experience with I2C in the real > world. > > I'm reading the specs, and I feel I'm getting a pretty good > understanding. If I'm getting this right, the SDA line will only > change when the SCL line is low - except when the master is > indicating a START or STOP command. > > So the question I have for those who have really done this is - > in the real world, could a master (or series of masters) issue > a STOP command followed by a START command - all on the same > SCL high period. The latest I2C spec doesn't explain whether > or not this could happen. > > This is key to me, since I'm trying to create an I2C slave that > runs solely off the SDA and SCL signals. Whether or not I have > to deal with START and STOP on the same SCL high period will > impact the design choice I make. > AFAIK, that's normal when the bus is idle in the meantime. The idle bus has all drivers loose and both lines up. When the master ends a transmission, the last thing is the STOP condition: SCL up, then SDA up. When the next transmission starts, the first thing is the START condition: SCL still up, SDA down. HTH Tauno Voipio tauno voipio @ iki fiArticle: 57094
Tauno Voipio wrote: > > "y_p_w" <y_p_w@hotmail.com> wrote in message > news:591da479.0306230937.42883d68@posting.google.com... > > Hi- > > > > I'm currently in the process of creating a synthesizable Verilog > > F/S I2C slave, but have little experience with I2C in the real > > world. > > > > I'm reading the specs, and I feel I'm getting a pretty good > > understanding. If I'm getting this right, the SDA line will only > > change when the SCL line is low - except when the master is > > indicating a START or STOP command. > > > > So the question I have for those who have really done this is - > > in the real world, could a master (or series of masters) issue > > a STOP command followed by a START command - all on the same > > SCL high period. The latest I2C spec doesn't explain whether > > or not this could happen. > > > > This is key to me, since I'm trying to create an I2C slave that > > runs solely off the SDA and SCL signals. Whether or not I have > > to deal with START and STOP on the same SCL high period will > > impact the design choice I make. > > > > AFAIK, that's normal when the bus is idle in the meantime. > > The idle bus has all drivers loose and both lines up. When the master ends a > transmission, the last thing is the STOP condition: SCL up, then SDA up. > When the next transmission starts, the first thing is the START condition: > SCL still up, SDA down. I think he means the other way around, a START followed by a STOP with no clock transitions inbetween. In essence, this would be an "empty" frame. I have not worked with I2C before, so I don't know the answer. But I am interested since I will be making one as well. I have not checked opencores.org, but it seems likely that they would have a core for this. It might be a bit larger than you would want to use however. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57095
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3EF744FB.AF2FB36E@yahoo.com... > Tauno Voipio wrote: > > > > "y_p_w" <y_p_w@hotmail.com> wrote in message > > news:591da479.0306230937.42883d68@posting.google.com... > > > Hi- > > > > > > I'm currently in the process of creating a synthesizable Verilog > > > F/S I2C slave, but have little experience with I2C in the real > > > world. > > > > > > I'm reading the specs, and I feel I'm getting a pretty good > > > understanding. If I'm getting this right, the SDA line will only > > > change when the SCL line is low - except when the master is > > > indicating a START or STOP command. > > > > > > So the question I have for those who have really done this is - > > > in the real world, could a master (or series of masters) issue > > > a STOP command followed by a START command - all on the same > > > SCL high period. The latest I2C spec doesn't explain whether > > > or not this could happen. > > > > > > This is key to me, since I'm trying to create an I2C slave that > > > runs solely off the SDA and SCL signals. Whether or not I have > > > to deal with START and STOP on the same SCL high period will > > > impact the design choice I make. > > > > > > > AFAIK, that's normal when the bus is idle in the meantime. > > > > The idle bus has all drivers loose and both lines up. When the master ends a > > transmission, the last thing is the STOP condition: SCL up, then SDA up. > > When the next transmission starts, the first thing is the START condition: > > SCL still up, SDA down. > > I think he means the other way around, a START followed by a STOP with > no clock transitions inbetween. In essence, this would be an "empty" > frame. > > I have not worked with I2C before, so I don't know the answer. But I am > interested since I will be making one as well. > > I have not checked opencores.org, but it seems likely that they would > have a core for this. It might be a bit larger than you would want to > use however. > An empty frame is expressely forbidden in the specs. However, the logic must still not hang up if such a condition should happen. Tauno Voipio tauno voipio @ iki fiArticle: 57096
Erik Bolton wrote: > Hello All: > > I'm working on an old PCB design from a piece of test equipment and > I'm looking to replace a bunch of old logic chips with a single > PLD/FPGA. The only chip I'm having trouble reproducing the behavior > for is the delay line. It's somewhat of a special part. It's a 10 > bit programmable line that steps in 1 ns increments and has an initial > prop. delay of 6 ns. Also, like most delay lines, it isn't clock > driven. I've read about a fairly straight-foward method of using a > counter with an overflow bit to create a delay, but the problem is the > step size. Since I need 1 ns steps I'd have to drive the counter with > a 1 Ghz clock which seems a little impractical for this circuit. If > you guys have any suggestions as to how I might pull this off I'd > really appreciate it. Thanks in advance! There are plenty of programmable delays, try analog devices, micrel, plus a few others. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 57097
rickman wrote: > > Normally delay lines are used to time DRAMs. Since DRAMs are getting > harder to find, why not redesign the board for SDRAM which will > eliminate the need for the delay line altogether? > There are plenty of other uses for delay lines. There are even products consisting almost entirely of delaylines, the DG535 or similar comes to my mind. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 57098
Rene Tschaggelar <tschaggelar@dplanet.ch> wrote: : Erik Bolton wrote: :> Hello All: :> :> I'm working on an old PCB design from a piece of test equipment and :> I'm looking to replace a bunch of old logic chips with a single :> PLD/FPGA. The only chip I'm having trouble reproducing the behavior :> for is the delay line. It's somewhat of a special part. It's a 10 :> bit programmable line that steps in 1 ns increments and has an initial :> prop. delay of 6 ns. Also, like most delay lines, it isn't clock :> driven. I've read about a fairly straight-foward method of using a :> counter with an overflow bit to create a delay, but the problem is the :> step size. Since I need 1 ns steps I'd have to drive the counter with :> a 1 Ghz clock which seems a little impractical for this circuit. If :> you guys have any suggestions as to how I might pull this off I'd :> really appreciate it. Thanks in advance! : There are plenty of programmable delays, try analog devices, micrel, : plus a few others. For the Analog Devices AD9500|1 hurry up. End-of-life is announces, with last time buy somtimes in July 2003, if I remember right... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 57099
"mike" <mikel262@gazeta.pl> wrote in message news:bd70pi$lhe$1@inews.gazeta.pl... > but, what if I want to draw for eg. a line, and after that i want to add > another line on the screen later? When I switch banks (after first line was > drawn) the first line will "dissapear", because memory of bank1 is filled > only with data of second line. I didn't say it was a perfect solution ... or the only one. :-) You'd normally paint in system memory and DMA the rendered frame to the graphics controller. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"
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