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Messages from 57575

Article: 57575
Subject: Re: why so many problems Xilinx ?
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Wed, 02 Jul 2003 11:41:01 -0700
Links: << >>  << T >>  << A >>
Peter Sommerfeld wrote:
> I too have been contacted thru email everytime that my Altera ng
> questions were not replied to in the group. Altera seemed to put alot
> of thought into the answers. It would be nice if they replied to the
> group to share the knowledge, except that maybe my questions were too
> specific to be helpful to others.


Consider posting any solution that is useful to you.
I may be googling for it next week.

  -- Mike Treseler


Article: 57576
Subject: USB flash disk drive -> "Unknown Device". MultiLINX to blame.
From: symon_brewer@hotmail.com (Symon)
Date: 2 Jul 2003 11:52:29 -0700
Links: << >>  << T >>  << A >>
Dear All,
      I wasted several hours of drinking time the other day trying to
fix my removable drive USB mass storage device Thumbdrive flash disk.
Wouldn't work on a Windows XP PC, where it'd once been happy. Reported
Unknown Device. I eventually found the posting below. MultiLINX is
pants, once again! Thought I'd post this with as many searchable
keywords as I can think of, so people with the same problem can get to
the pub quicker than I did!

      BTW, why is the MultiLINX cable / iMPACT so rubbish? It should
:-
1) be 'plug and play'. Really!
2) be powered from the USB port, not the target. I often need to cycle
the target power. This means closing iMPACT, stopping the cable, then
starting it all up again.
3) be much faster at downloading devices/driving Chipscope. There's no
way it gets anywhere near the bandwidth of the USB port.
4) not stop the date appearing when I position the mouse cursor over
the little clock in the bottom right hand corner of my screen!! What
is going on there?
5) be open source so I can drive it from my own software.
6) not team up with FPGA editor to give my PC narcolepsy. What is that
software doing during those 30ish second pauses? Probably laughing in
my face, that's what!
      Anyway, rant over, HTH, Symsx.


From: Berni Joss (berni_13@yahoo.com)
Subject: USB Device not recognized 
View: Complete Thread (4 articles)  
Original Format 
Newsgroups: microsoft.public.windowsxp.general
Date: 2002-10-29 13:57:02 PST 
 

FYI

After using a flash card reader successfully for many months, I
suddenly get:
"USB Device Not Recognized" after plugging the TravelFlash 5in1 reader
into any usb port.
Some other usb peripherals work fine, only the PQI TravelFlash is not
recognized.
The system is a Dell Dimension 4400 running XP home.

Luckily I seem to have found the problem.
It appears that the MultiLINX driver installed by the Xilinx Free ISE
WebPACK 5.1i is not innocent.

After removing:
1. mlnxfltr.sys & mltlnx.sys from c:\windows\system32\drivers
2. rebooting
3. uninstalling the USB root hubs (there are two in a Dell Dimension
4400)
4. rebooting

I can again read my flash cards :-)

Have a good day,
Berni.

Article: 57577
Subject: Process variable setup times and propogations
From: Matt <newsgroups@raven-systems.net>
Date: Wed, 02 Jul 2003 14:52:46 -0400
Links: << >>  << T >>  << A >>

	Reposting: Sorry for the earlier mess. The Xilinx newsgroup portal 
apparently chewed my origional posting!

Greetings folks,

	I am having a strange time with some code I recently wrote to implement 
a UART - the code seems to be working fine now, but a problem cropped up 
that is baffling me. This design is being synthesized in Xilinx ISE 5.1 
and implemented into a Spartan-II XD2S50 device. I'm on something of a 
learning curve with things right now so please go easy on me! :D

............
	when 10 => -- Stop Bit
	BitPos := 11; -- next is holding pattern for breaks
	if(FIFOhead = 3) then
		FIFOhead := 0; -- wrap around
	else
		FIFOhead := FIFOhead + 1;
	end if;

	FIFO(FIFOhead)(8) <= RxD; -- stash the break bit
	FIFO(FIFOhead)(7 downto 0) <= RReg; -- stash the received data
............

	The two FIFO array assignment statements at the bottom are the 
predominant problem.... The object is to assign the break bit to the 9th 
bit of the array of 9-bit words (indexed by the process variable 
'FIFOhead'), and then assign the databyte to the lower part. As written 
and synthesized, the above writes ONLY the received byte and NOT the 
break bit. If the statements are exchanged, the opposite happens. In 
short, only the SECOND assignment appears to be executing properly. If a 
'dummy' statement is inserted, so the code looks like:

............
	end if;
	FIFO(FIFOhead)(7 downto 0) <= RReg; -- DUMMY
	FIFO(FIFOhead)(8) <= RxD; -- stash the break bit
	FIFO(FIFOhead)(7 downto 0) <= RReg; -- stash the received data
............

	then both assignments work properly. There appears to be some amount of 
latency inherent in updating the variable before it can be used as an 
index, but why? And what is the proper way to detect or circumvent this 
problem? This fix seems to work just fine, but I fear this problem may 
explain similarly strange behavior in other sections of code.

	If this IS a latency problem, how should I go about detecting these 
sort of things in my design to ensure all code is relatively 
bulletproof? All of the VHDL texts I have here really only cover 
language theory and simulation synthesis, not things like proper timing 
and floorplanning of the design into a physical device. What's the best 
way to work on filling in my learning gaps in this area? Thanks in 
advance for any insight!

-- Matt


Article: 57578
Subject: Re: Combining Distributed RAM and Block RAM
From: gilad_coh@walla.co.il (Gilad Cohen)
Date: 2 Jul 2003 12:00:17 -0700
Links: << >>  << T >>  << A >>
muthu_nano@yahoo.co.in (Muthu) wrote in message news:<28c66cd3.0307020649.356989c9@posting.google.com>...

Hello Muthu,
You should use the distributed RAM for the extra bit.
There are macros for 16x1, 32x1, 64x1, and 128x1. If you need dual
port RAM, it will cost you twice as many LUTs.
If the depth is not enough, you can easily cascade the macros.

As for the timing, the reading from the distributed RAM is
asynchronous, so you should register it's output to make it's delay
like the BRAM's (That's before the sampling of the entire RAM you said
you are doing before the use of the data).

Gilad.

Article: 57579
Subject: Virtex 2Pro, ML300, VP2PDK, EDK, etc..
From: antti@case2000.com (Antti Lukats)
Date: 2 Jul 2003 12:03:21 -0700
Links: << >>  << T >>  << A >>
Hi

just a few comments, hope the may save some time for someone

ML300 is shipped with V2PDK
most V2Pro 'reference designs' are only for V2PDK
V2PDK is no longer supported by xilinx
the V2PDK examples only compile with synplicity, 
not with XST, well XST compiles the verilog versions
and one simple VHDL example also compiles.
when using XST synthesis (with the verilog example) with almost
all options turned off the VP7 device on ML300 is 89% percent full?

with EDK 3.2 there are no similar examples (for the V2Pro) as in
the V2PDK, as example the TFT LCD (available and working in V2PDK)
is 'obsoleted' and not replaced in EDK 3.2 so if you want to build
a standalone system with EDK 3.2 (and TFT) then you have no support -
the obsoleted core can be 'forced' to be visible in EDK/XPS but
no idea if it would function or not.

ml300 does boot linux, ok, but all you can do is starting a calculator
- there is no docu about the linux implementation at all, yes there
is linux but how to write simplest application for it, no idea, from
montavista there is link back to xilinx. a round-trip. well at least
ml300 is now listed by montavista as supported platform (few months
ago still wasnt even listed).

the VxWorks 'demo' with ml300 simply loads 5 bitmaps in delayed sequence.

maybe I am missing some information, but that are my first feelings with
V2Pro/ml300

antti

Article: 57580
Subject: Re: VirtexII bitstream relocation
From: gilad_coh@walla.co.il (Gilad Cohen)
Date: 2 Jul 2003 12:09:59 -0700
Links: << >>  << T >>  << A >>
ecarvalho@inf.pucrs.br (Ewerson Carvalho) wrote in message news:<1d281733.0307011401.2740faa4@posting.google.com>...

Hi,
Take a look at: http://www.xilinx.com/xapp/xapp290.pdf
The flow described there recommends no more than one reconfigurable
module, but allows more than one.
They also have a flow for minor changes - such as RAM contents and
things like that.
Gilad.

Article: 57581
Subject: Re: Fixed point signed multiplication algorithm
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 02 Jul 2003 12:14:01 -0700
Links: << >>  << T >>  << A >>
The Xilinx (Virtex) multiplier does 18 x 18 bit two's complement
combinatorial multiplication, using the (modified, I think) Booth's
algorithm, just like most combinatorial multipliers have done for the
past 20 years. Virtex includes an optional pipeline stage that increases
speed, but adds latency. The data sheet gives you the through-delay for
all different widths.
Peter Alfke, Xilinx Applications.
=================================
praveen wrote:
> 
> How does the signed multipliers in xilinx
> that fast. what algorithm do they use. I need to first implement in on
> MATLAB and see the result.
> 
> waiting for reply
> praveen

Article: 57582
Subject: Re: Xlilin xc9572XL Default register values
From: "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com>
Date: Thu, 3 Jul 2003 07:39:10 +1200
Links: << >>  << T >>  << A >>

"Steven Elzinga" <steven.elzinga@xilinx.com> wrote in message
news:3F02FD70.1090202@xilinx.com...
> reposting in plain text
>
> Ralph,
>
> Sorry for the delay in my response.  I tried the code below with ISE
> 5.2i sp3 targeting a 9572:
>
>     library IEEE;
>     use IEEE.STD_LOGIC_1164.ALL;
>
>     entity inits is
>         Port ( d : in std_logic;
>                c : in std_logic;
>                q : out std_logic);
>     end inits;
>
>     architecture inits_arch of inits is
>
>     signal q_temp : std_logic := '1';
>
>     begin
>
>     process (c) is begin
>     if c'event and c = '1' then
>
>     q_temp <= d;
>
>     end if;
>     end process;
>
>     q <= q_temp;
>
>     end inits_arch;
>
> The register had the INIT value of '1' attached to it.  I then tried the
> below code with record types:
>
>     library IEEE;
>     use IEEE.STD_LOGIC_1164.ALL;
>
>     entity inits is
>         Port ( d1 : in std_logic_vector (4 downto 0);
>                d2 : in std_logic_vector (4 downto 0);
>                c : in std_logic;
>                q1 : out std_logic_vector (4 downto 0);
>                q2 : out std_logic_vector (4 downto 0));
>     end inits;
>
>     architecture inits_arch of inits is
>
>     type v_reg_type is record
>             -- registers
>             IOLatch     :   std_logic_vector(4 downto 0);
>             IOLatch2     :   std_logic_vector(4 downto 0);
>         end record;
>
>     signal d_temp : v_reg_type;
>     signal q_temp : v_reg_type := (IOLatch => "11111", IOLatch2 =>
"11111");
>
>     begin
>
>     process (c) is begin
>     if c'event and c = '1' then
>
>     q_temp <= d_temp;
>
>     end if;
>     end process;
>
>     d_temp.IOLatch <= d1;
>     d_temp.IOLatch2 <= d2;
>
>     q1 <= q_temp.IOLatch;
>     q2 <= q_temp.IOLatch2;
>
>     end inits_arch;
>
> The registers did not get initialized in 5.2i sp3 or in our next version
> of the software.  I will file a bug report on this.
>
> As for your version of webpack not working please try the latest
> version.  If the register is still not initializing as suspected (not
> using record types that is) please contact the hotline.
>

I don't really have allot of time to spend with this now (it's working fine
with the constraints file).

I will say however, that when the record initisation didn't work I tried
initializing another 16 bit register in the design using the same method:

 signal latchedAddress : std_logic_vector(15 downto 0)  :=
"1010101010101010";

This didn't work either. Perhaps 5.1 is to old

Thanks for the help.

Regards
Ralph



Article: 57583
Subject: Re: Xilinx ISE drops support for more parts
From: Steve Lass <lass@xilinx.com>
Date: Wed, 02 Jul 2003 13:48:55 -0600
Links: << >>  << T >>  << A >>
lecroy wrote:

>JoeG <no@where.net> wrote in message news:<3F0219B6.8F56CB33@where.net>...
>  
>
>>I've ask Xilinx the ? about legacy support for years -- I have the same
>>problem with XC4005 series -- we have hundreds fielded on MILITARY
>>applications. However Xilinx newer tool suites Foundation/Alliance DO NOT
>>support these legacy devices. So we are STUCK with maintaining an OLD
>>machine with OLD Xilinx XACT software.
>>    
>>
>
>I feel for you, and every other company who is now in this trap thank
>to Xilinx.  I think with Xilinx dropping Spartan, you really have to
>wonder what their long term plans are.  Will we have one "stable"
>version of software for each series?  Each version with it's own
>interface, bugs and PC requirements?  Is this really what we expect
>from a company who claims to be the best?
>
>I had called Xilinx marketing to ask some of these questions, and like
>the person I spoke to on the Hotline, they just don't have a clue what
>the long term plans are.  Who is driving the ship?
>
I'm driving the ship and like I said, we have no plans to drop any other 
architectures from our
software.  All the FPGAs we have in the software now are derivatives of 
the Virtex arcitecture
so keeping them in the release is not difficult.

Steve Lass
Director, Software Product Marketing
Xilinx, Inc.


Article: 57584
Subject: Re: Programmable Delay (not clock driven)
From: erik.bolton@gdds.com (Erik Bolton)
Date: 2 Jul 2003 12:49:30 -0700
Links: << >>  << T >>  << A >>
Thanks for all the insight guys, its been a big help.

I think I have a possible solution.  Maxim-IC (Dallas Semi.) makes the
DS1020 series, which is a fairly inexpensive ($10) 8-bit delay line
with a step zero delay of 10 ns.  I'm thinking about daisy-chaining
four of them together in order to obtain the total delay range I need
(10 - ~1000ns).  The current delay line is programmed in parallel, but
the data is initially received via a serial data bus into a shift
register which is latched with an external clock signal.  The shift
register output is then used to actually program the delay line.  I've
got VHDL code written for the shift register.  I'm planning on writing
code that breaks down the single 10 bit number into four 8 bit numbers
that will be used to program all four delay lines in parallel
simultanouesly.  I'll also be running each delay lines output pin back
into the Virtex so I can make use of all four chips together or each
one individually.  If I want a delay of 265 ns for example, I can
simply program the first chip with all 1's and use its output.  If I
need 266 ns, I can program the first chip to delay 256 ns, and then
program the second chip with zeros so that the second ouput is delayed
approx. 266ns.  The step zero delay can vary in this chip (+/- 2ns),
and I'm not sure how well the daisy-chaining will work, so this idea
might completely suck :).  Let me know what you guys think.

-Erik

Erik Bolton <erik.bolton@gdds.com> wrote in message news:<vp4efv8hnd592mjtkimsr13gevd1jsjij7@4ax.com>...
> Hello All:
> 
> I'm working on an old PCB design from a piece of test equipment and
> I'm looking to replace a bunch of old logic chips with a single
> PLD/FPGA.  The only chip I'm having trouble reproducing the behavior
> for is the delay line.  It's somewhat of a special part.  It's a 10
> bit programmable line that steps in 1 ns increments and has an initial
> prop. delay of 6 ns.  Also, like most delay lines, it isn't clock
> driven.  I've read about a fairly straight-foward method of using a
> counter with an overflow bit to create a delay, but the problem is the
> step size.  Since I need 1 ns steps I'd have to drive the counter with
> a 1 Ghz clock which seems a little impractical for this circuit.  If
> you guys have any suggestions as to how I might pull this off I'd
> really appreciate it.  Thanks in advance!
> 
> -Erik Bolton

Article: 57585
Subject: Re: Cyclone vs Spartan-3
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 02 Jul 2003 15:55:07 -0400
Links: << >>  << T >>  << A >>
"Nicholas C. Weaver" wrote:
> 
> In article <omuMa.1725$zn2.469105682@twister1.starband.net>,
> Steven K. Knapp <steve.knappNO#SPAM@xilinx.com> wrote:
> 
> >Personally, I agree with your statement and have been trying to convince the
> >powers that be to add additional Spartan-3 devices to WebPack.  The folks
> >responsible for WebPack are concerned about the total download size.  The
> >larger devices have multi-MB support files.
> 
> Split the download, or switch the devcie files to be
> download-on-demand or download-via-miniapp.

Actually the device files should be separate anyway since they change
frequently.  There are often reasons for not wanting to change the
version of the tools you are using, but there is never a reason to keep
an out of date speed file.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 57586
Subject: VHDL & OV6620 CMOS camera
From: "PC" <philippe.chagny**@NOSPAM@**@free.fr>
Date: Wed, 2 Jul 2003 22:28:10 +0200
Links: << >>  << T >>  << A >>
Hello

please, if anyone can help me to find some information to interface the
OV6620 to my FPGA ( VHDL ),
don"t hesitate !

ov6620 : www.ovt.com
ther is no application note .. no support.. :-(

thank's to contact me ( remove the antispam on my email ..)

thank's
Philippe



Article: 57587
Subject: NIOS tutorial for the Stratix1S10
From: Rene Tschaggelar <tschaggelar@dplanet.ch>
Date: Wed, 02 Jul 2003 20:31:41 GMT
Links: << >>  << T >>  << A >>
I'm trying to follow the NIOS tutorial for the Stratix1S10.
At one point, page 16 of the 'tt_nios_hw_stratix_1s10.pdf'
I should start the SOPC builder. A quick console window opens,
to fast to recognize anything, and vanishes.
There is no error message, nowhere.
There is no SOPCBuilder as it should be according to the pdf.
I browswed the SOPC Builder solutions in the knowledge base.

 From this FAQ I could gleam that the SOPC builder has to
be installed. How can I check whether it was installed, and if
not, where is this SOPC Builder to be found ?

I'm using Quartus2 Build 176 02/04/2003 SJ Full Version
plus the SP1


Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net


Article: 57588
Subject: Re: Process variable setup times and propogations
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Wed, 02 Jul 2003 13:38:32 -0700
Links: << >>  << T >>  << A >>


Matt wrote:

>     The two FIFO array assignment statements at the bottom are the 
> predominant problem.... The object is to assign the break bit to the 9th 
> bit of the array of 9-bit words (indexed by the process variable 
> 'FIFOhead'), and then assign the databyte to the lower part. As written 
> and synthesized, the above writes ONLY the received byte and NOT the 
> break bit. If the statements are exchanged, the opposite happens. In 
> short, only the SECOND assignment appears to be executing properly. If a 
> 'dummy' statement is inserted, so the code looks like:
> 
> ............
>     end if;
>     FIFO(FIFOhead)(7 downto 0) <= RReg; -- DUMMY
>     FIFO(FIFOhead)(8) <= RxD; -- stash the break bit
>     FIFO(FIFOhead)(7 downto 0) <= RReg; -- stash the received data
> ............
> 
>     then both assignments work properly. There appears to be some amount 
> of latency inherent in updating the variable before it can be used as an 
> index, but why? 


The change you show should not have made any difference.
Post the  complete process. Something else is going on.

Try changing  if(FIFOhead  = 3) to
               if(FIFOhead >= 3)


  -- Mike Treseler


Article: 57589
Subject: Re: why so many problems Xilinx ?
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 02 Jul 2003 16:39:45 -0400
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> rickman wrote:
> > Often vendors don't want to seem like they are hawking their wares
> > here.
> 
> I can guarantee you that neither Xilinx nor Altera harbors this kind of
> girlish modesty.
> But we must consider the audience, and avoid the BS.
> 
> I definitely will hawk the capabilities of the Virtex-II DCM and MGTs if
> anybody ever asks for a related functionality. That's my job, and that's
> what this ng is for, isn't it?
> Peter Alfke

I don't really care how I get help.  When I have a question, I just want
an answer.  If they are more comfortable with email than the newsgroup,
I don't care.  Anything is better than the hotline or god forbid.. the
web site!  

But I guess I should say that an open discussion here was what alerted
me to the modular configuration capability of ISE.  I have checked this
out on the web site several times and pretty much found nothing.  But
now I have at least one app note about how to use it and this will make
a very big difference in my device selection.  However I expect this
will require a lot of support since it seems a bit more complex than the
app note covers.  Can you recommend a point of contact for modular
configuration?  This is exactly the sort of thing I expect will be like
pulling teeth to get any real info on from the hotline.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 57590
Subject: New FPGA RISC C-NIT
From: do_not_post_to_thisaddress@yahoo.com (Sumit)
Date: 2 Jul 2003 13:46:49 -0700
Links: << >>  << T >>  << A >>
Visit the website for C-NIT at

http://www.c-nit.net

Sumit

Article: 57591
Subject: Re: How to get 27MHz from 10 MHz in FPGA???
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 02 Jul 2003 13:53:19 -0700
Links: << >>  << T >>  << A >>


Glen Herrmannsfeldt wrote:
> If you needed a lower frequency couldn't you always generate a power of two
> multiple of it, and then divide that down?
> 
Of course, that's the way. 
I had misunderstood the problem as violating the min INPUT frequency...
Sorry for the confusion.
Peter Alfke

Article: 57592
Subject: Re: Looking for DIMM format FPGA board
From: bconnersprint03@earthlink.net (Bill)
Date: 2 Jul 2003 13:55:12 -0700
Links: << >>  << T >>  << A >>
"Leon Heller" <leon_heller@hotmail.com> wrote in message news:<bdv712$oki$1@hercules.btinternet.com>...
> <eholbrook@austin.rr.com> wrote in message
> news:874r24dalp.fsf@vole.holby-net...
> > I'm looking for a DIMM format FPGA board like Pilchard or the AcB from
> > (now defunct?) Nuron. I've done several web searches, but found
> > nothing that both fits the bill, and is from a company that is
> > apparently alive. I've found a couple of things that are close to what
> > i want (from mite.cz, and sunrise-systems.de), but they don't return
> > emails, so i figure they're dead, too.
> >
> > Has anyone heard of something like this, or do i need to design/build
> > it myself?
> 
> I was thinking of developing one. How about us collaborating?
> 
> Leon


From what I hear, SRC Computers holds patents in this area and is not
licensing to anyone right now.

www.srccomp.com

Article: 57593
Subject: Re: why so many problems Xilinx ?
From: Steve Lass <lass@xilinx.com>
Date: Wed, 02 Jul 2003 15:10:40 -0600
Links: << >>  << T >>  << A >>
rickman wrote:

>Peter Alfke wrote:
>  
>
>>rickman wrote:
>>    
>>
>>>Often vendors don't want to seem like they are hawking their wares
>>>here.
>>>      
>>>
>>I can guarantee you that neither Xilinx nor Altera harbors this kind of
>>girlish modesty.
>>But we must consider the audience, and avoid the BS.
>>
>>I definitely will hawk the capabilities of the Virtex-II DCM and MGTs if
>>anybody ever asks for a related functionality. That's my job, and that's
>>what this ng is for, isn't it?
>>Peter Alfke
>>    
>>
>
>I don't really care how I get help.  When I have a question, I just want
>an answer.  If they are more comfortable with email than the newsgroup,
>I don't care.  Anything is better than the hotline or god forbid.. the
>web site!  
>
>But I guess I should say that an open discussion here was what alerted
>me to the modular configuration capability of ISE.  I have checked this
>out on the web site several times and pretty much found nothing.  But
>now I have at least one app note about how to use it and this will make
>a very big difference in my device selection.  However I expect this
>will require a lot of support since it seems a bit more complex than the
>app note covers.
>
It depends on how well your design fits into physical modules.  Some 
designs are certainly more
complicated than what's described in the App Note.

>  Can you recommend a point of contact for modular
>configuration?
>
Yes, I will check with a couple of our modular design experts and get 
you a name.

Steve

>  This is exactly the sort of thing I expect will be like
>pulling teeth to get any real info on from the hotline.  
>
>  
>


Article: 57594
Subject: Re: NIOS tutorial for the Stratix1S10
From: Petter Gustad <newsmailcomp5@gustad.com>
Date: 02 Jul 2003 23:50:34 +0200
Links: << >>  << T >>  << A >>
Rene Tschaggelar <tschaggelar@dplanet.ch> writes:

> I'm trying to follow the NIOS tutorial for the Stratix1S10.
> At one point, page 16 of the 'tt_nios_hw_stratix_1s10.pdf'
> I should start the SOPC builder. A quick console window opens,
> to fast to recognize anything, and vanishes.

It appears that you have a problem with your installation. 

> There is no error message, nowhere.

Not even in the message window? View->Utility Windows->Messages if you
don't have it visible.

>  From this FAQ I could gleam that the SOPC builder has to
> be installed. How can I check whether it was installed, and if
> not, where is this SOPC Builder to be found ?

There should be a directory containing a bin directory which contains
a file called sopc_builder (which is a perl script). I don't know how
Quartus will search for sopc_builder because both under Windows and
Solaris I have multiple revisions of sopc builder and Quartus is using
the most recent one.

You should have received a CD containing the NIOS 3.0 release with
SOPC Builder (version 2.8) and Quartus II.

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 57595
Subject: Re: Regarding NRZ
From: H. Peter Anvin <hpa@zytor.com>
Date: 2 Jul 2003 14:52:31 -0700
Links: << >>  << T >>  << A >>
Followup to:  <bducne$10r362$1@ID-84877.news.dfncis.de>
By author:    "Falk Brunner" <Falk.Brunner@gmx.de>
In newsgroup: comp.arch.fpga
> 
> <guest> schrieb im Newsbeitrag news:ee7e625.-1@WebX.sUN8CHnE...
> > Hi everyone,
> > Iam basic to the communication design,
> > I have a query regarding NRZ interface with FPGA,
> > Can we provide NRZ interface to FPGA,
> > how does the voltage level will be at the interface ?
> > Is it like 1 --> + V
> > 0 --> -V ?
> > Is it possible to interface it with FPGA?
> > Thanks in Advance.
> 
> This is not a question of NRZ, ist a quaestion of signaling voltage level.
> 
> TTL 0-5V
> LVTTL 0-3.3V
> RS232  +/-12V
> etc.
> 
> So the FPGA can only output/input voltage levels stated in the datasheet.
> 

Well, it sort of is.  NRZ is a trivoltage code (which, I have to
admit, I have never seen the point of... it seems that MFM or
Manchester code is better in every aspect including being
self-synchronizing regardless of the bit sequence.  Yet NRZ got used
in USB.  Sigh.)

So the question really is:

"Are there any FPGAs with NRZ-capable I/O buffers?"

The answer to the best of my knowledge is "no", but as you said, look
a the data sheets to find what kind of signalling standards your
particular FPGA supports.

Obviously, one can always use an external I/O buffer.

	-hpa
-- 
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64

Article: 57596
Subject: Re: Xilinx ISE drops support for more parts
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Thu, 03 Jul 2003 09:56:47 +1200
Links: << >>  << T >>  << A >>
Steve Lass wrote:
> 
> lecroy wrote:
> <snip>
> >I had called Xilinx marketing to ask some of these questions, and like
> >the person I spoke to on the Hotline, they just don't have a clue what
> >the long term plans are.  Who is driving the ship?
> >
> I'm driving the ship and like I said, we have no plans to drop any other
> architectures from our
> software.  All the FPGAs we have in the software now are derivatives of
> the Virtex arcitecture
> so keeping them in the release is not difficult.
> 
> Steve Lass
> Director, Software Product Marketing
> Xilinx, Inc.

 Can we get a quick summary of what's removed, and what 
legacy versions of SW are needed to support which family ?

 Peter A mentioned SpartanXL as being still active, 
(and lowest power?) but not supported in the latest SW ?

 I also noted in another thread that Altera ADDED support for
an older 10Kxx family to Quartus 3.0.

 -jg

Article: 57597
Subject: Re: VHDL & OV6620 CMOS camera
From: "Jonathan Bromley" <jonathan@oxfordbromley.u-net.com>
Date: Wed, 2 Jul 2003 23:00:31 +0100
Links: << >>  << T >>  << A >>
"PC" <philippe.chagny**@NOSPAM@**@free.fr> wrote
in message news:3f033fb1$0$4611$626a54ce@news.free.fr...

> please, if anyone can help me to find some information to interface the
> OV6620 to my FPGA ( VHDL ), don"t hesitate !
> ov6620 : www.ovt.com
> ther is no application note .. no support.. :-(

ahem, no, it's just that (I quote the website)

>>> The DATASHEET for the OV6620 requires an NDA.

(NDA = Non Disclosure Agreement, a confidentiality
contract agreeing that you won't give away any technical
information without the vendor's permission).

On the other hand, there is a full data sheet for the
OV6630 part on the web site.

If you got the sample device legitimately, how about
contacting them, signing the NDA and getting the data
that way?

Hint:  If anyone else HAS the data, they've signed the
NDA already and therefore they would be breaking their
contract with Omnivision by telling you about it.

Cheers
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
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Article: 57598
Subject: Re: Cyclone vs Spartan-3
From: "Paul Leventis" <paul.leventis@utoronto.ca>
Date: Wed, 02 Jul 2003 22:36:28 GMT
Links: << >>  << T >>  << A >>
Hi Dennis,

> for the new multichannel filter design I have a choice -
> Altera Cyclone EP1C12 ($60) or Xilinx Spartan-3 XC3S1000(???)

Here are a few key advantages for Cyclone that I can think of off the top of
my head:

- Availability.  The 1C12 is in full production on a 130 um process that
we've used to manufacture 10+ different devices (including 7 Stratix
members, 4 Cyclone members, and some Apex II members)

- Performance.  The _slowest_ Cyclone speed grade is 20% faster (geometric
average of fmax over many real user designs) than Spartan-3, which is
currently offered in only one speed-grade.  If you need greater performance,
there are two more Cyclone speed grades available, giving you an additional
30% performance advantage.

- 3.3V Tolerance.  Cyclone is 3.3V tolerant, in today's silicon.  PCI?  No
problem.

- Bitstream Compression.  Regardless of your data source, you can compress
your bitstream (~2:1 ratio) to reduce the cost of your non-volatile storage
device, whether that is our low-cost, low-footprint serial configuration
devices or something else.

Regards,

Paul Leventis
Altera Corp.



Article: 57599
Subject: Re: UART -- Process variable setup times and propogations
From: Matt <newsgroups@raven-systems.net>
Date: Wed, 02 Jul 2003 18:53:30 -0400
Links: << >>  << T >>  << A >>
Mike Treseler wrote:

> The change you show should not have made any difference. Post the  complete process. Something else is going on.

	Thanks for the reply, Mike - here's the whole reciever UART process I'm 
currently synth'ing... I started with a basic UART design from freecores.org and 
wound up rewriting a bunch of it in order to process things like break 
conditions and the like, as well as adding in the small FIFO to help with 
handling data flow. As written below, the UART seems to function pretty much 
normally when synthesized into the chip. However, beyond the problem I 
origionally mentioned (the FIFOhead not seeming to update right away) this UART 
also seems to have the quirk of occasionally letting two of the same received 
byte slip thru when data is constantly streaming in.

	Unfortunatly this system contains two seperate clocks - one which is devided 
down to run the UART at standard baud rates, and another which drives the main 
chunk of the system which reads the recived bytes from the UART. It seems that 
on occasion (and this is verifiable on a logic analyzer) the clocks seem to line 
up such that status data is not read correctly, and the UART is somehow being 
read twice in quick succession.

	Do I need to include a higher-level syncronization method to ensure the two 
clocks don't cause issues when inevitably lining up such that one is reading 
data controlled by the other, whilst the data is in the middle of a transition?

	I've played with a couple possible solutions, but nothing seems to work with 
the double-reads. This seems like a nice simple recieving UART, but I'm stumped. 
Any ideas?

Regards,
-- Matt

................
entity RxUnit is
   port (
      Clk    : in  Std_Logic;  -- system clock signal
      Reset  : in  Std_Logic;  -- Reset input
      Enable : in  Std_Logic;  -- Enable input
      ReadA  : in  Std_logic;  -- Async Read Received Byte
      RxD    : in  Std_Logic;  -- RS-232 data input
      RxAv   : out Std_Logic;  -- Byte available
      DataO  : out Std_Logic_Vector(7 downto 0); -- Byte received
	Break  : out Std_Logic;  -- Break Detected
	Debug  : out Std_Logic); -- debug
end entity;

architecture Behaviour of RxUnit is
   signal RReg    : Std_Logic_Vector(7 downto 0); -- receive register
   signal ReadS    : Std_Logic;	-- Synchronised load signal

   component synchroniser is
   port (
      C1 : in Std_Logic;	 -- Asynchronous signal
      C :  in Std_Logic;	 -- Clock
      O :  out Std_logic);-- Synchronised signal
   end component;

   -- the FIFO
   type FIFOarraytype is array (integer range 0 to 4) of std_logic_vector(8 
downto 0);
   signal FIFO:FIFOarraytype;

begin

   -- Synchronise Read on Clk
   SyncLoad : Synchroniser port map (ReadA, Clk, ReadS);
   --Busy <= LoadS or TBufL;

   -- Rx Process
   RxProc : process(Clk,Reset,Enable,RxD,ReadS)
   variable BitPos : INTEGER range 0 to 11;   -- Position of the bit in the frame
   variable SampleCnt : INTEGER range 0 to 3; -- Count from 0 to 3 in each bit
   variable FIFOhead, FIFOtail : INTEGER range 0 to 4; -- FIFO head and tail

   begin
      if Reset = '0' then -- Reset
         --RRegL <= '0';
	   --RRegLcache <= '0';
         BitPos := 0;
	   FIFOhead := 0;
	   FIFOtail := 0;
      elsif Rising_Edge(Clk) then
	
		DataO <= FIFO(FIFOtail)(7 downto 0); -- always output whatever is on the FIFO tail
		Debug <= FIFO(FIFOtail)(0); -- a signal to the outside world for debugging on 
logic analyzer
		Break <= FIFO(FIFOtail)(8);

		if (ReadS = '1' and FIFOhead /= FIFOtail) then -- advance FIFO on read edge
	     	if(FIFOtail = 3) then
				FIFOtail := 0;
			else
				FIFOtail := FIFOtail + 1;
			end if;
		else	
				Debug <= '0';
		end if;
	
	if(FIFOhead /= FIFOtail) then -- there is stuff in the FIFO
	     	RxAv <= '1';  -- Indicate there is data avaliable to be read
	else
			RxAv <= '0';
	end if;

         if Enable = '1' then
            case BitPos is
               when 0 => -- idle
                  if RxD = '0' then -- Start Bit
                     SampleCnt := 0;
                     BitPos := 1;
                  end if;
               when 10 => -- Stop Bit
                  BitPos := 11;    -- next is holding pattern for breaks
			  if(FIFOhead = 3) then
		 		FIFOhead := 0; -- wrap around
		 	  else
		 		FIFOhead := FIFOhead + 1;
			  end if;
			  FIFO(FIFOhead)(7 downto 0) <= RReg; -- DUMMY 'WAIT'
			  FIFO(FIFOhead)(8) <= RxD; -- stash the break bit
			  FIFO(FIFOhead)(7 downto 0) <= RReg; -- stash the recieved data

		    when 11 => -- Holding pattern for break release (so only one break is 
recieved)
		    	  if(RxD = '1') then
			  	BitPos := 0;
			  end if;
               when others =>
                  if SampleCnt = 1 then -- Sample RxD on 1
                     RReg(BitPos-2) <= RxD; -- Deserialisation
                  end if;
                  if SampleCnt = 3 then -- Increment BitPos on 3
                     BitPos := BitPos + 1;
                  end if;
            end case;
            if SampleCnt = 3 then
               SampleCnt := 0;
            else
               sampleCnt := SampleCnt + 1;
            end if;

         end if;
      end if;
   end process;
end Behaviour;
.............





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