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"Muthu" <muthu_nano@yahoo.co.in> wrote in message
news:28c66cd3.0306300523.7bc9f636@posting.google.com...
Hi Muthu,
> I have read some where
Probably here :-) It's been discussed several times.
> that " RESET " signal has to be released with respect
> the the clock edge, though it is asynchronous RESET?
> Why is this required? Will the SET and RESET signals of the FFs will
> Fall under the signals list as D-in for clock timings (Setup / HOLD).
There is some agreement that the "right" way to do reset is to
assert reset asynchronously, but deassert it synchronously. That
way, reset takes effect immediately regardless of the clock; but
if you remove reset very close to the time of a clock edge,
you have no risk of race conditions between the release of reset
and the next clock. This is quite important because static
timing analysis tools are not generally capable of analysing
the timing of reset paths. In some FPGA architectures, the
reset signal may have a very large skew (greater than 1 clock
period) across the device, so it is difficult to ensure that
your design will start correctly after reset has been removed.
Unfortunately it's easy to give the advice (assert reset
asynchronously, remove it synchronously) but it is quite
tricky to implement it! The obvious approach is to code
all your synchronous logic like this:
always @(posedge clock or posedge async_reset)
if (async_reset) begin
// reset actions
end else begin
if (sync_reset) begin
// reset actions, repeated here
end else begin
// usual synchronous actions
end
end
And then you need to create the sync_reset signal. Of
course it should be asserted as soon as async_reset
comes along, but it should be held for one or two clocks
after the release of async_reset:
reg sync_reset, sync_1;
always @(posedge clock or posedge async_reset)
if (async_reset) begin
sync_1 <= 1;
sync_reset <= 1;
end else begin
sync_1 <= 0;
sync_reset <= sync_1;
end
This approach is very bullet-proof, but it gives you another
global net (sync_reset) to distribute.
HTH
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 57426On 30 Jun 2003 06:23:08 -0700, muthu_nano@yahoo.co.in (Muthu) wrote: >Hi, > >I have read some where, saying that " RESET " signal has to be >released with respect the the clock edge, though it is asynchronous >RESET? > Yes, this is true. >Why is this required? Will the SET and RESET signals of the FFs will >Fall under the signals list as D-in for clock timings (Setup / HOLD). An FF is essentially a controlled asynchronous sampler and if it has a (re)set input it has to resolve (re)set changing in addition to data changing. For (re)set there is a different timing check called "recovery" which is measured against active edge of (re)set clearing vs. active edge of the clock. There is also a minimum pulse width of the (re)set for it to take effect correctly. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 57427
Hi Seth, Have you looked at www.avvida.com? We make and sell a 64-bit 66-MHz board with 1 to 5 Stratix FPGAs and a lot of I/O and external memory. One of our customers is developing Linux drivers, which we can bundle with the board. Peter Sommerfeld petersommerfeld@hotmail.comArticle: 57428
Here is a tutorial explanation of potential problems: Asynchronous Reset overrides any synchronous activity. Therefore there is no problem with the leading edge of Reset. But the trailing edge of Reset needs to be timed such that it does not coincide with a clock edge that might try to set the flip-flop ( High on D ). That's where you have a set-up-time requirement: You must end asynchronous Reset a certain time before that clock edge, or you must extend it beyond that clock edge. Otherwise you cannot guarantee the behavior of the flip-flop. This gets especially tricky when the Reset drives many flip-flops. The clocks will have very little skew, but the Reset line has longer skew, and some flip-flops might operate synchronously while others are still being held reset. Solution: Create a local synchronized or synchronous Reset signal that lasts longer ( ends later ) than the common asynchronous Reset. Peter Alfke, Xilinx =============== Muthu wrote: > > Hi, > > I have read some where, saying that " RESET " signal has to be > released with respect the the clock edge, though it is asynchronous > RESET? > > Why is this required? Will the SET and RESET signals of the FFs will > Fall under the signals list as D-in for clock timings (Setup / HOLD). > > Regards, > MuthuSArticle: 57429
enliteneer@mindless.com (eric) wrote in message news:<2b8a3423.0306281351.2ff6e311@posting.google.com>... > Antti, > > I think downloading the sample files require being an EDK registered user. > Im registered with Xilinx but only for the ISE 2.1 Student Edition software, > so nothing happens when I click the examples and enter my account info. > > Im not familiar with the memec support pages, is this from Xilinx? The > EDK costs about $500, so if they have a low priced kit that includes > such examples, Im interested! > > Eric uups - I am registered for foundation and EDK, and its seemed 'remember password' so I didnt notice that the actual files are not public. as of memec - all memec designs (inclusice EDK examples) are downloadable from one page, all are downloadable not only those that work with the kit I did register with. so I guess buying the cheapest kit provides the access to 'full lounge' but as said those designs dont 'do anything' if you dont have EDK/XPS :( anttiArticle: 57430
Hi, All for the new multichannel filter design I have a choice - Altera Cyclone EP1C12 ($60) or Xilinx Spartan-3 XC3S1000(???) Xilinx part has a embedded MAC units. I've used in a past Altera chips and they have a good tech support and free tools. Does any one has experience with Xilinx support? And is it possible to obtain a free tools from Xilinx or they charge for the software? Any other hidden issues? Thanks, Dennis dknews@ueidaq.comArticle: 57431
I forgot to mention a method that sometimes is easier: Simply make sure that the D input ( or the CE input ) of the flip-flops is and stays Low during and a little beyond the time that Reset ends. That guarantees that the flip-flops stay in their Reset state and later come out of it in a synchronous way. Peter Alfke Peter Alfke wrote: > > Here is a tutorial explanation of potential problems: > Asynchronous Reset overrides any synchronous activity. Therefore there > is no problem with the leading edge of Reset. > But the trailing edge of Reset needs to be timed such that it does not > coincide with a clock edge that might try to set the flip-flop ( High on > D ). > That's where you have a set-up-time requirement: You must end > asynchronous Reset a certain time before that clock edge, or you must > extend it beyond that clock edge. Otherwise you cannot guarantee the > behavior of the flip-flop. > This gets especially tricky when the Reset drives many flip-flops. The > clocks will have very little skew, but the Reset line has longer skew, > and some flip-flops might operate synchronously while others are still > being held reset. > Solution: Create a local synchronized or synchronous Reset signal that > lasts longer ( ends later ) than the common asynchronous Reset. > > Peter Alfke, Xilinx > =============== > Muthu wrote: > > > > Hi, > > > > I have read some where, saying that " RESET " signal has to be > > released with respect the the clock edge, though it is asynchronous > > RESET? > > > > Why is this required? Will the SET and RESET signals of the FFs will > > Fall under the signals list as D-in for clock timings (Setup / HOLD). > > > > Regards, > > MuthuSArticle: 57432
Make sure that you either: 1) add the correct .elf file to your ISE project and associate it with the top level HDL (also make sure that your .bmm file is associated with top level HDL file) or 2) after creating a bit file in ISE, import back into XPS and run "Update bitfile" from there. Assuming that you're using Block RAM for any instruction storage, you absolutely need to have the .elf file data initialized in the BRAM. From what you described, it's possible that your hardware (processor, bus, etc.) is all configured just fine, save the BRAM Init values. In other words, if you don't have any instructions in the Block RAM, then MicroBlaze doesn't have any instructions to run. Check out the EST Guide (specifically page 42) for more info on this and what Antti said. If you're still having troubles, please open a case with our support hotline or at support.xilinx.com. You may also be interested in checking out our Embedded Processor Forum here: http://toolbox.xilinx.com/cgi-bin/forum?14@241.TGAYa5F8e8l.0@.ee7236a Best regards, Ryan Laity Xilinx Applications GpsBob wrote: > Anyone familiar with generating Microblaze uP as a component of a larger > design? > > I have no trouble with the example Microblaze projects (EDK 3.2) when > using the XPS environment only. But, if I try to generate the uP as a > component an integrate using Xilinx's ISE 5.1i, when I download to the > eval board nothing works (although the build appears to complete with no > errors).Article: 57433
Hi all,
I need to use a LVDS signal as a clock (in PLL) in a Stratix.
Is someone could explain me how to implement this clk (in a csf file or
in Quartus II with "assign pin") ?.
Can you tell me if I need :
to indicate 2 signals in my VHDL file :
CLK_INn : in std_logic;
CLK_INp: in std_logic;
=> how to simulate this clk_in with ModelSim (VHDL Script file)
or only :
CLK_IN : in std_logic;
=> how to indicate the two pin external number ?.
Thanks lot for your answer.
Benoit.
Article: 57434In article <3eff173f$1_3@newsfeed>, DK <dknews@ueidaq.com> wrote: >Hi, All > >for the new multichannel filter design I have a choice - >Altera Cyclone EP1C12 ($60) or Xilinx Spartan-3 XC3S1000(???) > >Xilinx part has a embedded MAC units. Spartan 3 does not have embedded Serdeses, IIRC. Only the V2Pro/V2Pro-X have the serdeses. >Does any one has experience with Xilinx support? And is it possible to >obtain a free tools from Xilinx or they charge for the software? Xilinx Webpack currently doesn't support the big Spartan-3 chips, so you would have to pay for Foundation. Spartan 3 is very low voltage, which may be a problem for some designs but not for others. It may add an additional voltage you would not otherwise have, but the Cyclones already pretty low. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 57435
What you should really do is count the number of times someone from Xilinx has answered questions on the NG and the number of times you see someone from Altera (or other vendors) answer any questions. I think you will see it is about 100 to 1. A question about Xilinx will almost always be answered where as a question about Altera will only be answered by some other user. So basically you see more Xilinx questions because users know they will get an answer by someone who knows what they are talking about. You can't say that about Altera. Steve "qlyus" <qlyus@yahoo.com> wrote in message news:da71446f.0306260952.676b93d8@posting.google.com... > Just took a look of a few pages of comp.arch.fpga Thread Subject:Article: 57436
> > You forgot that RAM16X8S, RAM32X1D, RAM32X4S, RAM32X8S, RAM64X1D, > > RAM64X2S and RAM128X1S are absent in Spartan3. This is the "problem", > > not half of the ditributed memory! > > Unless I am missing something, I still don't see the issue. My point is > that it is a rare design indeed that needs even close to half the LUTs > used as distributed RAM or SRs. Most designs use a small number of SRs > and RAMs and the rest of the chip is used as logic. Rick, I donīt know about other applications, but this kind of dual ported memory helps me a lot. I use it primary as memory for filters, and the fact that I can have a write and a read separate ports, save me a lot of logic and let me run the filters at double speed (or half clock rate). The block RAM is not usable because the throughput: I have a lot of filters running in parallel. So these wider memories let me implement bigger filters at high speed without to much complication. Of course I can, and have to live without them in Spartan3, but if Iīm not alone, maybe in Spartan4... Peter and Austin, I know there are Virtex2 and Virtex2Pro! Luiz Carlos Oenning Martins KHOMP SolutionsArticle: 57437
"William LenihanIii" <lenihan3we@earthlink.net> wrote in message news:<MXKLa.18348$C83.1734029@newsread1.prod.itd.earthlink.net>... > ---------------------------------------------------------------------------- > ------ > HOW DOES SPARTAN-3 DIFFER FROM VIRTEX-II? > > Spartan-3 is supposed to be = Virtex-II minus "some features". > Unfortunately, > Xilinx does not appear to provide a comprehensive list of those differences. > The following is my attempt at making such a list based on a first-cut > review > of each families' literature. > > Anyone have any comments, corrections, additions, or questions about this > list? > Then post them here and please 'cc' me via email. > > Thank you. > > Bill Lenihan lenihan3we@earthlink.net The key factor is that the Spartan 3 will be 1/2 the cost of the Virtex II. This is a major selling point for large designs. I have a design that uses the XC2V6000-4 at a cost of $4,000 per chip. The design requires 23,000 slices. The Spartan 3 XC3S4000 (27,648 slices) costs $1,531 (1-24). The XC3$5000 (33,280 slices) costs $1,933 (1-24). The costs are $200 lower for the lower pin count BGA packages (900). The lower clock speed is not a problem, limited I/O pads are not a problem and the lower VCC supply voltage is not a problem (1.2 VDC). The parts are not available until 2004. Bill Hanna > ---------------------------------------------------------------------------- > ------ > > Vccint = 1.2v ..... instead of V-II's 1.5v > Are there any off-the-shelf, 1-chip linear regulators (not switching > regulators) that can supply 1.2v? > > Vccaux = 2.5v ..... instead of V-II's 3.3v > > half the slices are NOT full-featured: missing RAM & shift-register > capability > > up to 4 DCMs ..... instead of V-II's 12 > > DCM works on input clocks up to 325 Mhz ..... V-II up to 450 Mhz > > 8 global clocks ..... instead of V-II's 16 > > data sheet mentions BUFGMUX global clock buffer, but not BUFGCE ..... V-II > has both > > greater # of I/O, due to staggered pad scheme at chip periphery > > LVPECL I/O not available > > LVDS only w/ Vcco = 2.5v ..... V-II can run LVDS from Vcco = 2.5v or 3.3v > > Is there any capability for Spartan-3's +3.3v LVTTL inputs & outputs to > interact with other devices that use +5v TTL? ..... V-II (and Virtex-E) > +3.3v LVTTL inputs could be driven by +5v TTL outputs if an appropriately > sized current-limiting resistor were in series, while V-II (and Virtex-E) > +3.3v LVTTL outputs could safely connect directly to +5v TTL input devices > with no intervening resistor networks. > > configuration pins are LVCMOS25 @ 12mA ..... V-II's are LVTTL @ 12mA > > data sheet mentions a Master/Slave "Parallel" configuration mode that LOOKS > the same as V-II's "SelectMap" mode. Are they completely identical? If so, > then why do they have different names? (I know, marketing droids -- who > specialize in renaming that which already has a name -- rule the universe.) > > Flip-Chip packages not available > > 90 nm process ..... V-II uses 120/150 nm [not that the OEM designing with > FPGAs really cares]Article: 57438
"Peter Alfke" wrote: > > Solution: Create a local synchronized or synchronous Reset signal that > > lasts longer ( ends later ) than the common asynchronous Reset. Would you venture a guess at a guideline of what "local" means? Is this a matter of how far within the chip the reset signal must travel or how many FF's it hits? The easiest would be to create a little two or three FF reclocker per HDL module ... but an HDL module could create a huge amount of logic across a relatively large area of the chip (without manual floorplanning). -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 57439
Ralph Mason wrote:
> > It's just a signal assignment, but
> > the right hand side value must match the type, for example:
> >
> > constant v_reg_init : v_reg_type :=
> >
> > (IOLatch => ( others => '0'),
> > IOLatch2 => ( others => '0')
> > );
> >
> Thanks Mike, that compiles nicely (although doesn't appear to have the
> desired effect! )
Maybe you forgot the signal assignment.
Should be something like:
process(clk,rst) is
begin
if (rst = '1') then
r <= v_reg_int; -- init
elsif rising_edge(clk);
-- do other stuff;
end if;
end process;
-- Mike Treseler
Article: 57440The Stratix Fast PLL can go up to 1GHz for certain speedgrades, which is why the Megawizard allows this (only the Enhanced PLL is limited to 800Mhz). A design that needs a VCO at 1GHz will work in Stratix. The PLL will then be placed on the Fast PLL and be used as a general purpose PLL. However a Fast PLL cannot be used for dynamic reconfiguration, and this should have been reported during fitting. For Quartus II version 3.0, the Megawizard has been enhanced to recognize that only an Enhanced PLL can be used when dynamic reconfiguration is selected, and as a result it will ensure that the VCO is valid for an Enhanced PLL in the Megawizard itself. The Megawizard will become speedgrade aware in a future release of Quartus. In the meantime all calculations are based on the fastest speedgrade. - Subroto Datta Altera Corp. already5chosen@yahoo.com (Michael S) wrote in message news:<f881b862.0306300619.58b3f8a5@posting.google.com>... > Following PLL was generated with MegaWizard Plug In Manager and > compiled (for Stratix) under Quartus 2.2: > Input Frequency: 36MHz > Dynamic reconfiguration is in use. > c0 Clock Multiplication Factor = 158 > c0 Clock Division Factor = 36 > Other counters are not in use. > The compilation report shows: > M value = 79 > N value = 3 > VCO frequency = 948MHz !!!! > It looks like Quartus design team is not aware of limitations of the > Stratix PLL as listed in the respective datasheet (300 to 800MHz for > -5 and -6 grades, 300 to 600MHz for -7 grade). They live under > impression that everything up to 1000MHz is o.k. :(Article: 57441
"Mike Treseler" <tres@peoplepc.com> wrote in message news:3F009696.9050203@peoplepc.com... > Ralph Mason wrote: > > > > > It's just a signal assignment, but > > > the right hand side value must match the type, for example: > > > > > > constant v_reg_init : v_reg_type := > > > > > > (IOLatch => ( others => '0'), > > > IOLatch2 => ( others => '0') > > > ); > > > > > > > Thanks Mike, that compiles nicely (although doesn't appear to have the > > desired effect! ) > > > Maybe you forgot the signal assignment. > Should be something like: > > process(clk,rst) is > begin > if (rst = '1') then > r <= v_reg_int; -- init > elsif rising_edge(clk); > -- do other stuff; > end if; > end process; it's just to set the default state of the Macrocell latches on startup. There is no reset signal. RalphArticle: 57442
My approach would be to generate a synchronous CE (clock disable) signal and distribute it. Now I have a synchronous signal distribution problem that I can analyze the conventional way. If the prop delay is less than a clock period, there is no problem. Otherwise I can resort to pipelining... That means, you are in charge and not at the mercy of some loosely specified asynchronous delay. Peter Alfke ========================= Martin Euredjian wrote: > > "Peter Alfke" wrote: > > > > Solution: Create a local synchronized or synchronous Reset signal that > > > lasts longer ( ends later ) than the common asynchronous Reset. > > Would you venture a guess at a guideline of what "local" means? Is this a > matter of how far within the chip the reset signal must travel or how many > FF's it hits? The easiest would be to create a little two or three FF > reclocker per HDL module ... but an HDL module could create a huge amount of > logic across a relatively large area of the chip (without manual > floorplanning). > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu"Article: 57443
Hi all, It won't fit in xcv100e, the adder has 48 and 16 bit inputs. Maping gives error and suggest bigger device,.... Is there anyway to get around this? of course I like to stick with the 100 Many thanksArticle: 57444
The chip is not "high" enough to accomodate the 48-bit adder in one column of CLBs (the carry chain uses only 2 LUTs per CLB vertically) The solution is to break the adder (I think it really is an incrementer?) chain, I would suggest 32 bits plus another one with 16 bits. You lose some speed speed, since you have to route the carry back to the "bottom". There are sneaky ways of pipelining and speeding this up, but at moderate speed you should have no problem. Peter Alfke =============== Marlboro wrote: > > Hi all, > > It won't fit in xcv100e, the adder has 48 and 16 bit inputs. Maping > gives error and suggest bigger device,.... > > Is there anyway to get around this? > of course I like to stick with the 100 > > Many thanksArticle: 57446
Hi Petter, The speed is very slow, data is updated every 33 ms or so but the clock is 50 mhz, I think there would be no problem... Thanks,Article: 57447
FPGAs can become video generators easily. http://www.fpga4fun.com/PongGame.html Next week, I'll try to build something using RC servos. Any other nice idea of something fun and easy to build for FPGA beginners is welcome. JeanArticle: 57448
> > I am trying to find tools for benchmarking a processor written > completely in Verilog as part of my research Projects at the > University of Wisconsin- Madison. The way the processor is designed should not effect the programs it can run. The two major CPU benchmark suites are: http://www.spec.org http://www.eembc.org Although the best benchmark is the application you intend to run. Cheers, JonBArticle: 57449
Luiz Carlos <oen_br@yahoo.com.br> wrote: > Playstation2 also use a MIPs microprocessor. This one with 128 bit registers! but these are SIMD, not-GP, registers. > > Luiz Carlos -- Sander +++ Out of cheese error +++
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