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Nicholas C. Weaver wrote: > In article <c148d133f3627dcc857a52d54fcea3fc@news.teranews.com>, > Rene Tschaggelar <tschaggelar@dplanet.ch> wrote: > >>As immediate question : What is the timeframe you're thinking of ? > > Probably 9 month out, or a year. So there is the time to get up to > speed on the tools involved, probably by doing a much simpler, slow > speed demoboard first. > > And the other tradeoff is that I don't know yet, but I may need to do > 2-3 separate designs over a 3 year period, which lends itself to > in-house design. > >>A few points : >>You cannot decide to do an inhouse board design without previous >>knowledge. Whatever tool you choose, it takes some time to figure >>out and become comfortable with. It takes at least 6 month to become >>productive and another for the bells and whistles. And as I see it, >>you'll be using 2 tools, one the the pcb and another one for the FPGA. >>And each tool is the mentioned complexity. >>A design working with subnanoseconds is far from trivial, without >>some knowledge hardly doable. There is more to it than 'just do a >>multilayer'. > > > Thats the concern: between the high speed differential pairs (you have > to get the V2Pro/Stratix GX transceivers interfaced with the optical > components, giving 1.25 GHz board traces) and a DDR-DRAM bus, its > non-trivial even when the "It's a prototype, throw more layers at the > problem" response is invoked. It doesn't look too bad then, at least you're expecting the problems. The resources may be a problem. Meaning, this is senior engineer's stuff. Some experience in doing boards is an advantage. You appear not to have one with that experience. It may be an advantage to hire a specialist to pop in sometimes for some hints while you're getting familiar. Ahem : Doing boards is a commitment for a lifetime ... Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 53026
You can attach an attribute (pullup) to the input pin. But you mentioned 2.4 V. What's the Vcco? And what is the drive impedance when it is at 2.4 V? Try pulling it Low with a resistor to find out. Use 1 kilohm and 100 kilohm, and observe the difference. Peter Alfke =================== S Embree wrote: > > It's a Spartan II, and I'm using Xilinx ISE 5.1. > > I tried to configure the pin as an output, but ISE refuses to connect > the pullup node to the rest of the circuit (because it thinks that I > am want to drive an output, when what I really want to do is drive an > input). How could I use a tristate buffer to pull-up the resistor?Article: 53027
Hello everyone.
I have no experience on FPGA programming, thus many questions. I am
developing hardware for modular math operations that have big area
requirements. Given that, only high density FPGAs, which are volatile,
appear to meet these requirements. So, I have some questions:
* Are there high density non-volatile FPGAs?
* What are the ways to program a FPGA like APEX as my hardware is
powered up?
* How long does it take typically?
* How big are the typical memory requirements to hold a FPGA
configuration data?
* What is the protocol for this programming?
Thank you in advance,
Roberto Gallo
Article: 53028Do you absolutely need the 50% duty cycle on your derived 10 MHz clock? If so, do you need sub-nanosecond skew beteween the various signals? "Dirk Dörr" <dirk.doerr@delsy.de> wrote in message news:b3nadl$1o3nf1$1@ID-175447.news.dfncis.de... > Hello! > > Does anyone know how to generate a 10 MHz Clock (and 2 other signals) > derived from 30 MHz? > > What I need would look like: > > 30 MHz: _-_-_- > 10 MHz: ___--- > > SigA: --_--- > SigB: -----_ > > (Best viewed using Courier font) > > It is for a design that consists of a Xilinx XC5204 using VHDL with > Foundation 3.1 FPGA Express. > > Thanks in advance > > Dirk Dörr > > >Article: 53029
Hi group, I wonder if someone has designed an ultra320 SCSI (SPI-4) interface in FPGA, please direct me a start point, reference sites, or any thing related, Thanks alot.Article: 53030
"Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote > I'm in the very VERY preliminary planning stages, and looking to do > one or more FPGA board designs with multiple Gb (1000-baseSX) ports & > tranceivers. Thus there will be multiple 1.25 gigabaud differential > pair traces running around, between the FPGA and the transcievers. > > Whats the general (rough order ballpark) figure for an ousourced > design consisting of an FPGA, 8 transceivers, a DDR SO-DIMM slot, and > a compact flash/bootup? > > Similarly, if doing it in-house, what are the prefered tool-suites? > Is it the cadence branded tools? The cadence buyout ORCAD flow? > Mentor Graphics flow? I use the Mentor Expedition PCB tools and I find them great. Of course like every complex software it's far from perfect but it is really powerful and can route differential pairs. If you want to do really fast design you should look at the signal integrity modules. Also be prepared to spend some time to master it. The biggest problem is the price :( Doing the PCB is kind of fun and I do like to completely design a board, from the PCB to the software... By doing the PCB yourself, I'm sure you will get a better result. If you spend enough time to master the tools... Marc Battyani (who is working on a 10 layer VirtexII FG676 board)Article: 53031
Roberto Gallo wrote: > > * Are there high density non-volatile FPGAs? Apparently not yet. I wondered myself why there is no flash included. > > * What are the ways to program a FPGA like APEX as my hardware is > powered up? Have a look at the application note AN-116 from Altera. -You can use a configuration chip, they have a flash plus some loader. -You can have your own flash plus some support logic. > > * How long does it take typically? Programming time is in the order of a few 100ms depending on the size. > > * How big are the typical memory requirements to hold a FPGA > configuration data? I guess 1Mbit up. > > * What is the protocol for this programming? There is JTAG doing the FPGA and the configuration chip under Quartus. Plus some more. Though there are application notes about that subject, the process it not standardized. I got stuck rather soon and settled for JTAG. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 53032
I apologize for having misread the original question. This makes it a bit more complicated, since the outputs need to change on either edge of the incoming clock. It can still be done fairly simply assuming the incoming 30 MHz has a reasonable duty cycle. Otherwise you need a PLL or DLL Here is my old article that talks about the subject. http://www.xilinx.com/xcell/xl33/xl33_30.pdf Peter Alfke ============ John_H wrote: > > Do you absolutely need the 50% duty cycle on your derived 10 MHz clock? > > If so, do you need sub-nanosecond skew beteween the various signals? > > "Dirk Dörr" <dirk.doerr@delsy.de> wrote in message > news:b3nadl$1o3nf1$1@ID-175447.news.dfncis.de... > > Hello! > > > > Does anyone know how to generate a 10 MHz Clock (and 2 other signals) > > derived from 30 MHz? > > > > What I need would look like: > > > > 30 MHz: _-_-_- > > 10 MHz: ___--- > > > > SigA: --_--- > > SigB: -----_ > > > > (Best viewed using Courier font) > > > > It is for a design that consists of a Xilinx XC5204 using VHDL with > > Foundation 3.1 FPGA Express. > > > > Thanks in advance > > > > Dirk Dörr > > > > > >Article: 53033
nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) wrote in message news:<b3ocqh$i5e$1@agate.berkeley.edu>... > In article <c148d133f3627dcc857a52d54fcea3fc@news.teranews.com>, > Rene Tschaggelar <tschaggelar@dplanet.ch> wrote: > >As immediate question : What is the timeframe you're thinking of ? > > Probably 9 month out, or a year. So there is the time to get up to > speed on the tools involved, probably by doing a much simpler, slow > speed demoboard first. > > And the other tradeoff is that I don't know yet, but I may need to do > 2-3 separate designs over a 3 year period, which lends itself to > in-house design. Sounds like an interesting project and with the number nets likely involved it is good you are thinking of multiple spins. One thing about the slow speed demo option is that your transceivers may not scale. I was working with a 2.5GHz SERDES and the base 125MHz (from spec) could not deviate. Other issues forced use to use a 90MHz base in the lab until we got things figured out. I could probably do a bare board for you around $300/per assuming about a 8"x8" four layer board. (see http://www.tech-forge.com ) And before I get flamed on the unfeasibility of these dimensions, I would like to defend that this would be for a lab environment to get things going, not suitable for temp/volt/freq sweeps. Assembly costs may be high if there are BGAs on board since the shop I have used charges $100 for a single BGA attach. -SteenArticle: 53034
Roberto Gallo wrote: > > So, I have some questions: > > * Are there high density non-volatile FPGAs? Not really, since the capacity of antifuse-based FPGAs is lower, and CPLDs are much lower. > > * What are the ways to program a FPGA like APEX as my hardware is > powered up? Bit-serial or byte-serial data streams, clocked either from the outside (slave mode) or from the FPGA (master mode) > > * How long does it take typically? Clock speeds vary between 8 MHz max to 50 MHz max. That means from 8 Mbits/sec to 400 Mbits/sec at the highest clock rate, clocking in Bytes. > * How big are the typical memory requirements to hold a FPGA > configuration data? 1 to 25 Mbits, i.e. 100kBytes to t 3 MBytes. I suppose you are interested in the high end. > > * What is the protocol for this programming? Check with the manufacturer. It is quite straightforward. Some devices can be programmed via JTAG. I have tried to be resonably generic. Of course I prefer Xilinx :-) Peter Alfke, Xilinx ApplicationsArticle: 53035
In article <3E5DF0D4.D60FFDA8@gmx.net>, thomas_rudloff@gmx.net says... > > > > what is single and multiple function PCI? please give me example? > > > > You might have an IO section and a memory section. > Graphic cards often use this. Such a card has multiple memory windows/spaces as defined by the BARs, but that is not what is meant by "multiple function". A PCI device with more than one function has more than one config space. It pretty much allows you to put two or more distict devices (functions) in a single chip (that uses one IDSEL). Config transactions that target the other functions have the FUNCTION_NUMBER field equal to 1, 2, etc. > > > > How can you find if the burst transfer has crossed cacheline > > boundaries > > > > You need to have an address counter. You need this anyway cause > the target can stop the burst at any time. > If your address counter wraps at the appropiate bit position you are > in the next line. And in case its not obvious, your comparison needs to be based on the value programmed into the Cache Line Size register in config space. -- Rich Iachetta iachetta@us.ibm.com I do not speak for IBM.Article: 53036
Thank you.
By the way, I heard that Xilinx have some FPGAs whose memory elements
have multiple (two?) address and data ports so that one can access more than
one memory position at the same time. Am I correct?
Roberto Gallo
"Peter Alfke" <peter@xilinx.com> wrote in message
news:3E5FE9BF.3C93124C@xilinx.com...
>
>
> Roberto Gallo wrote:
> >
> > So, I have some questions:
> >
> > * Are there high density non-volatile FPGAs?
> Not really, since the capacity of antifuse-based FPGAs is lower, and
> CPLDs are much lower.
> >
> > * What are the ways to program a FPGA like APEX as my hardware is
> > powered up?
> Bit-serial or byte-serial data streams, clocked either from the outside
> (slave mode) or from the FPGA (master mode)
> >
> > * How long does it take typically?
> Clock speeds vary between 8 MHz max to 50 MHz max. That means from 8
> Mbits/sec to 400 Mbits/sec at the highest clock rate, clocking in Bytes.
> > * How big are the typical memory requirements to hold a FPGA
> > configuration data?
> 1 to 25 Mbits, i.e. 100kBytes to t 3 MBytes. I suppose you are
> interested in the high end.
> >
> > * What is the protocol for this programming?
> Check with the manufacturer. It is quite straightforward. Some devices
> can be programmed via JTAG.
> I have tried to be resonably generic. Of course I prefer Xilinx :-)
>
> Peter Alfke, Xilinx Applications
Article: 53037Rene Tschaggelar wrote: > > Roberto Gallo wrote: > > > > * Are there high density non-volatile FPGAs? > > Apparently not yet. I wondered myself why there is no flash included. > Simple reason: The IC process has to be optimized for highest density, highest performance, and lowest price, Including Flash would make the FPGA larger in area per function, slower, and more expensive. The majority of users would consider this a bad trade-off. ( 12 years ago we offered the XC3720 Flash-based derivative of the XC3020. We found almost no customers willing to pay "twice the price for half the speed".) Volatility was originally considered a drawback. Now more and more applications take advantage of reprogrammability, even dynamic reprogrammability. What used to be an embarrassment has become a major selling feature. :-) Peter Alfke, Xilinx ApplicationsArticle: 53038
Nicolas,
As you have an edu address I assume that you have access to the tools at
your university. That may make quite a difference in what you do. Because
the PCB layout is a new process to you, the access to knowledgable people may
be very important. I am doing fairly high speed design (200MHz plus, with
some as high as 800MHz) with something as simple as PADS powerPCB and power
logic. These are now owned by Mentor Graphics. If you are willing to watch
exactly what you are doing in every area and follow every rule for the logic
family (trace impedance, maximum stub length, termination voltages, etc.) you
can do the design with something as simple as this. On the other hand, if you
are willing to take the time to learn all the signal integrity tools, you can
do as well with the expensive tools with a better promise of signal
integrity. In my case, I started doing PCB layout back when the tools were
stickers and you put them down on a pice of clear mylar by hand at 2:1 size
layout. Some thoughts...
What is the cost of the tool suite?
What is the cost of your time to learn them?
How long will it take to learn them?
What is the cost of a respin of the board?
What is the probability of a respin?
On the other hand, the selection of a board designer at that kind of speed is
_not_ a trivial task. There is a substantial risk of getting someone who says
they can do it, but really can't. Also, it is very tempting to hire the
cheapest house. DON"T!!! Sorry for the shout, but it cannot be overstated.
We hired an individual to do some fairly high speed design for us. He came in
very late, and it _still_ did not work right.
My recomendation...
If you are planning on doing a fair bit of layout, don't hire someone
outside, learn to do it yourself or get someone in the department trained (not
a student, especially not an undergrad. They have too little experience and
too little time to learn the techniques and then they graduate.) If you have
access to someone from the EE dept there at Berkley see what they have to
say. If you have access to someone in industry doing similar stuff, see what
they say. The problem is that this is a multidisciplinary design endevour.
There are manufacturing issues if you intend to build more than one or two
pieces. It is an electromagnetics problem, an analog circuit problem, and a
digital problem. The schematic is perhaps 25% of the design problem. The
remainder is the circuit board. The FPGA will greatly simplify things _IF_ it
is not a BGA part. The layout and routing of BGA parts looks like it could be
a little tricky.
As I said, I am using the PowerPCB product and the only thing I really
would like to see is an easy way to integrate the design so that the FPGA UCF
file and the schematic would track. Simulation would be nice, but quite
frankly, I prefer to just follow the rules. To get good precise simulation
models for all the parts I use would be impossible and more costly and time
consuming than a couple of re-spins. As I think things over, given the number
of potential designs you are looking at I would bite the bullet, learn the
software, and do it myself. Then I would hire a good consultant to go over
the layout with me. I just don't like the consultant idea.
Good Luck,
Theron Hicks
"Nicholas C. Weaver" wrote:
> I'm in the very VERY preliminary planning stages, and looking to do
> one or more FPGA board designs with multiple Gb (1000-baseSX) ports &
> tranceivers. Thus there will be multiple 1.25 gigabaud differential
> pair traces running around, between the FPGA and the transcievers.
>
> Whats the general (rough order ballpark) figure for an ousourced
> design consisting of an FPGA, 8 transceivers, a DDR SO-DIMM slot, and
> a compact flash/bootup?
>
> Similarly, if doing it in-house, what are the prefered tool-suites?
> Is it the cadence branded tools? The cadence buyout ORCAD flow?
> Mentor Graphics flow?
>
> Thanks.
> --
> Nicholas C. Weaver nweaver@cs.berkeley.edu
Article: 53039Yes, each of the Virtex and Spartan-II BlockRAMs ( 4K bits of 18Kbits) is dual-ported. There is a common storage array with two completely independent access mechanisms, separate clocks, write enables, and even separate definitions of the aspect ratio = depth vs width. So you can use one port narrow and deep, the other wide and shallow. Dual-ported RAMs are ideal for FIFOs, even asynchronous ones ( independent write and read clocks). Look up the Virtex-II and Virtex-IIE families on the web. Virtex-IIPro adds on-chip microprocessors and 3-gigabit/sec transceivers. Good stuff! Peter Alfke, Xilinx Applications =============== Roberto Gallo wrote: > > Thank you. > > By the way, I heard that Xilinx have some FPGAs whose memory elements > have multiple (two?) address and data ports so that one can access more than > one memory position at the same time. Am I correct? > > Roberto Gallo > > "Peter Alfke" <peter@xilinx.com> wrote in message > news:3E5FE9BF.3C93124C@xilinx.com... > > > > > > Roberto Gallo wrote: > > > > > > So, I have some questions: > > > > > > * Are there high density non-volatile FPGAs? > > Not really, since the capacity of antifuse-based FPGAs is lower, and > > CPLDs are much lower. > > > > > > * What are the ways to program a FPGA like APEX as my hardware is > > > powered up? > > Bit-serial or byte-serial data streams, clocked either from the outside > > (slave mode) or from the FPGA (master mode) > > > > > > * How long does it take typically? > > Clock speeds vary between 8 MHz max to 50 MHz max. That means from 8 > > Mbits/sec to 400 Mbits/sec at the highest clock rate, clocking in Bytes. > > > * How big are the typical memory requirements to hold a FPGA > > > configuration data? > > 1 to 25 Mbits, i.e. 100kBytes to t 3 MBytes. I suppose you are > > interested in the high end. > > > > > > * What is the protocol for this programming? > > Check with the manufacturer. It is quite straightforward. Some devices > > can be programmed via JTAG. > > I have tried to be resonably generic. Of course I prefer Xilinx :-) > > > > Peter Alfke, Xilinx ApplicationsArticle: 53040
On Fri, 28 Feb 2003 15:42:21 +0200, "Noddy" <g9731642@campus.ru.ac.za> wrote: >I have implemented a polyphase serial DA fir filter. A new sample is given >as input every 8 clock cycles, while the filter takes 5 clock cycles to >generate an output. Everything works perfectly in simulation, however I only >obtain a constant output when I program the FPGA (Spartan 2e) and test with >logic analyser. I have tested the output interface, aswell as checked the >inputs to the filter, and all are fine. Can anyone possibly offer an idea as >to why this is happening? > >Thanks > >Adrian > You should run delay back-annotated simulations after P&R to see if this is a timing problem. You might be having really bad setup problems to see constant output. Also how are you resetting the design? Do you expect any internal state to be at a certain value during your RTL simulations ? If you have external reset, are you taking your chip off reset ? HTH, Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 53042
Peter Alfke wrote: > Rene Tschaggelar wrote: > >>Roberto Gallo wrote: >> >>> * Are there high density non-volatile FPGAs? >> >>Apparently not yet. I wondered myself why there is no flash included. >> > Simple reason: > The IC process has to be optimized for highest density, highest > performance, and lowest price, > Including Flash would make the FPGA larger in area per function, > slower, and more expensive. > The majority of users would consider this a bad trade-off. > ( 12 years ago we offered the XC3720 Flash-based derivative of the > XC3020. We found almost no customers willing to pay "twice the price for > half the speed".) > > Volatility was originally considered a drawback. Now more and more > applications take advantage of reprogrammability, even dynamic > reprogrammability. What used to be an embarrassment has become a major > selling feature. :-) Interesting. It might depend on the application then. All modern microcontrollers now have the code in flash. I consider the pricing of the Altera configuration flash chips extremely steep. It can be 150% of the FPGA it loads, so just being charged double for both would be quite acceptable. If I remember correctly, 27Fr for the ACEX1k30 and 45Fr for the EPC2, or so. I recently had a look on how I'd load an FPGA from a USB controller. It wasn't that simple either. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 53043
"Jim" <jim@nospam.com> wrote in message news:b3l3ug$fej$1@news8.svr.pol.co.uk... > "Alex Gibson" <alxx@ihug.com.au> wrote in message > news:b3l2f6$3os$1@lust.ihug.co.nz... > > > > "Jim" <jim@nospam.com> wrote in message > > news:b3iqbn$49m$1@newsg1.svr.pol.co.uk... > > > Anyone know how/where to get hold of a Xilinx Coolrunner-II dev kit > ($49) > > in > > > the UK please? The Xilinx web store is out of stock. The offical > > > distrbitutor for the UK (Insight Memec) only seems to sell it in the > U.S. > > > > > > Many thanks. > > > > Its made by digilent www.digilentinc.com > > They sell the board but not the design kit. > > > > http://www.digilentinc.com/XC2/index.html > > Also have a nice spartan2e board > > > > Insight memec has worldwide offices. > > They are one of the local distributors here in Australia. > > > > Tried emailing xilinx sales ? > > > > Alex > > > > Many thanks for the info Alex - Digilent have some nice boards and good > prices. > > Jim Sure have. I've got a coolrunner2 board and spartan2e board. Give good support as well and are very quick to respond to emails. Alex GibsonArticle: 53044
Hi all, in any design of a wireless digital communication system, what are the bottlenecks that has been hindering the progress to have very high data-rate, supposely > 100Mbps ? looking at this flow:: info src-->(source encoding + compaction + compression) ---> channel encoder-->modulator---->CHANNEL + NOISE(AWGN)--->Demodulator---->(re-inserting redundant info)--->estimated information channel encoding has proven to be able to operate > 100Mbps using Turbo Codec in parallel. Where are the bottlenecks from here ? Does the RF transmitter & reciever also plays a part?Article: 53045
John Tan wrote: > Hi all, > > in any design of a wireless digital communication system, what are the > bottlenecks that has been hindering the progress to have very high > data-rate, supposely > 100Mbps ? > > looking at this flow:: > > info src-->(source encoding + compaction + compression) ---> channel > encoder-->modulator---->CHANNEL + > NOISE(AWGN)--->Demodulator---->(re-inserting redundant > info)--->estimated information > > channel encoding has proven to be able to operate > 100Mbps using > Turbo Codec in parallel. Where are the bottlenecks from here ? Does > the RF transmitter & reciever also plays a part? Well, you cannot just blast some data into the air. You need a useable and affordable frequency band. Many frequency bands are reserved for a tiny group of people. Eg Military, Flight control, Satellite control, Science, to name a few. Then there are commercial bands where you have to pay for the frequencies. And then there are the free bands. The free bands are actually the expensive ones because they are overcrowded and the gear to use them is that sophisticated. Whereas in the military bands the gear is much simpler. Well now you wish to transmit 100MBit, making 100MHz bandwidth with a trivial modulation. With better modulation you can perhaps squeeze it down to 25MHz, at the expense of signal to noise. Meaning the transmission conditions have to be better, the more you want to transmit over a fixed frequency range. Such a lot of bandwidth is only available in the microwave bands above a few GHz. There you need line of sight to transmit too. And further, the power required is proportional to the bandwidth. So there probably is no handheld battery operation any more. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 53046
Is there a special free job posting board and / or forum I can post a position for a Verilog/FPGA Manufacturing Test Engineer? I have an alliance partner needing one for a client in Northern California. Your help will be greatly appreciated. Sincerely, Steve Michaels 281-6651-9184 832-563-9349 MobileArticle: 53047
> > * Are there high density non-volatile FPGAs? The Lattice ispXPGA family may meet your requirements. The first device to be released - and available now - is the ispXPGA1200 - see at the link below - http://www.latticesemi.com/lit/docs/prodbull/pb1166.pdf > > * What are the ways to program a FPGA like APEX as my hardware is >powered up? This device family uses embedded EECMOS memory elements, and programs via JTAG as would a CPLD > > * How long does it take typically? > The initial JTAG programming time is ~13 seconds, after that, on each power up cycle, the EECMOS autoloads the SRAM operating array in under 200uS. > * How big are the typical memory requirements to hold a FPGA >configuration data? > NONE, it is embedded in the device > * What is the protocol for this programming? > Again, for initial programming of EECMOS, use JTAG, after that, the SRAM array can be reconfigured via a parallel sysconfig port, so you can A - have a nonvolatile, 'instant on' FPGA B- have an embedded interface to do on the fly - or in the field - reprogramming of the device. > Please take a look at the technology that Lattice is now shipping. Michael Thomas Lattice FAE NY/NJ - USA > > Thank you in advance, > > Roberto Gallo > > > > > > > > >Article: 53048
Hi, =20 I am quite surprise coz i can not find Xilinx Design Manager in ISE 5.1i =20 Previously, I am using ISE 4.2i and Design Manager was still there for = my FPGA implementation. =20 Any advice ? =20 =20 Thanks. =20 Cheers, =20 BasukiArticle: 53049
I'm cleaning out my office, and came across two boards I
wish to get rid of. I've posted both on ebay:
An Atmel AT6005 prototyping board
http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=3404172147
and a VCC XC6216DS Hotworks board:
http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=3404173840
I'm posting here since you all would be the most likely to
be interested in such boards.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
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