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XST does a fine job, much better than foundation did. You will be happy with it. You can use your Aldec for both
pre-PAR and post route simulations. Aldec 3.2 is getting a bit long in the tooth now, the current version is 5.2. Just
make sure your unisim and simprim libraries have been updated and you should be fine though. For what it is worth, the
later editions of Aldec fixed a few annoying bugs in 3.2, increased the simulation speed considerably, and added
features. You'd probably find the update to be well worth the money when you can afford it.
Goran wrote:
> kevinbraceusenet@hotmail.com (Kevin Brace) wrote in message news:<cc7b0b5f.0302231456.ce5e3f9@posting.google.com>...
>
> Kevin,
> Thanks for answer.
>
> > Goran,
> >
> > Which Xilinx part are you planning to target?
>
> Spartan IIe, smaler Virtex (mainly because multipliers).Below 300K
> gates.
>
> > As long as you are targeting Xilinx devices below 300K system gates or
> > you don't have to target a 2.5V Virtex device, you may want to try the
> > free ISE WebPACK first before paying for ISE BASE-X.
> > Unlike ISE BASE-X users, ISE WebPACK users won't have access to FPGA
> > Editor or CORE Generator, but if those tools aren't important to you,
> > you should be fine with ISE WebPACK.
>
> I would like to use CORE Generator. I think it's a nice thing and ISE
> baseX doesn't seem to expencive. I don't like paying every year,
> but...
>
> > Regarding ModelSim XE, you may want to try ModelSim XE-Starter
> > first before paying for ModelSim XE.
> > Yes, ModelSim XE-Starter has a 500 statements limit, but what that
> > really means is that the simulation speed will drop after that limit,
> > and the simulator will still continue to run past that limit.
> > In the past, I have simulated a design that exceeded the 500
> > statements limitation by 40,000 lines, but ModelSim XE-Starter
> > completed the simulation fine.
> > However, it took quite a time to complete because I was doing a Post
> > P&R simulation of a design, and a Post P&R simulation is inherently
> > very slow compared to an RTL simulation.
>
> The problem is we have some older version of Aldecs ActiveVHDL, I
> think 3.2. I did lot of behavioral simulations on this one, and I like
> it. My question is can I import post place & route design from ISE and
> perform simulation in ActiveVHDL 3.2? I'm beginer in this, so really
> need help!
>
> > I also agree with Spam Hater that XST's synthesis quality is
> > good, so unless you don't mind paying $8,000 for a third party
> > synthesis tool, I will just use XST.
>
> Lot of people are saying XST is OK. Since I mind paying that much I'll
> go with XST.
>
> Regards,
> Goran
>
> >
> >
> > Kevin Brace (If someone wants to respond to what I wrote, I prefer if
> > you will do so within the newsgroup.)
> >
> >
> >
> > goran@net.yu (Goran) wrote in message news:<3c0f6336.0302221215.1ab0ed0d@posting.google.com>...
> > > Hi all,
> > > I work in small, development company, and we would like to start some
> > > more advanced FPGA designs (we are now using Xilinx FPGAs for simple
> > > glue logic only). My question is what tools we need to complete medium
> > > sized projects on Spartan IIe & smaller Virtex members.
> > > I learned (on Xilinx web site) that ISEbaseX would be OK?
> > > Does "one year license" that you buy from Xilinx mean your software
> > > stops working after one year, or you just don't have access to
> > > updates?
> > > If we purchase ModelSim XE does the same license apply?
> > > Can we use another VHDL simulator for post place & route simulation?
> > > We have, for example, Active VHDL, can we use it?
> > > How does XST behave, do we have to buy other synthezis tool to compile
> > > anything more advanced?
> > > Thanks in advance,
> > > Goran.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 53101praveenkumar1979@rediffmail.com (praveen) writes: > 1. I didnot understand why cacheline register required. I have read > that its length is same as processor cacheline length. what is the > exact function of this cacheline register. If you can give me an > example it will be wonderful. Look at the sections of the PCI spec concerning the "Memory Read Line", "Memory Read Multiple", and "Memory Write and Invalidate" commands. Also the stuff on the bahavior of bridges. > 5. In PCI cache support protocol how is the next address information > given to cache controller because cache latches only the starting > address and snoops it. Thereafter its the function of target PCI to > give the next address addressed (in burst mode as target PCI latches > the starting address and thenafter it increments it withinself). How > this incremented address given to cachecontroller? By a counter. Note that the burst address order specified by AD1 and AD0 of the address may cause it to be not strictly sequential. A target that doesn't support a particular burst address order must signal a target disconnect to prevent the master from bursting.Article: 53102
Getting a USB port in the FPGA working is not a trivial project by itself. As a
school project, you'd be better off using a dedicated USB chip and concentrating
on the interesting video stuff. That said, the application you describe would
be a good candidate for reconfiguration. For download from the camera, you'd
load the FPGA with the USB interface and memory management, and perhaps a first
pass your processing/decompression. Then after the image is loaded and perhaps
preprocessed, reconfigure the FPGA with the next step in the processing. The
compression could even be done as a series of FPGA images, depending on how much
you want to reduce the device size.
Theron Hicks wrote:
> Scott,
> I am looking at a USB application myself and the nicest option I found
> is the quickUSB option from QuickUSB. They have a daughter card with a
> built-in USB 2.0 connection. The card can either go to an altera FPGA or to
> a break-out board. We are also using the spartan2e. They use a cypress
> chip (EZ-USB). There also a couple of USB source codes in opencores
> http://www.opencores.org . If I recall correctly, the full USB core takes a
> fairly big FPGA. It sounds like the real object of the project is
> compression not USB. Could you live with a standard com port to do the
> up-load and down load? I know the time to do the upload/download is
> horrible but would that do what you want for the project? If so, there are
> several good UARTs out there. (look at Xilinx for a free reliable UART.
> XAPP223)
>
> Theron Hicks
>
> "Scott" <scottiecs@yahoo.com> wrote in message
> news:ad642abe.0302241334.393e834a@posting.google.com...
> > I am new to FPGA's and its programming language VHDL. I am working on
> > an electrical engineering senior project and have a few questions.
> > 1.) is it possible to connect a USB device (ie a digital camera) to
> > the Spartan 2e FPGA? 2.) If it is possible, could someone give a
> > quick overview or a good resource for me to research. 3.) If not, any
> > good suggestions on how i would go about accomplishing my
> > objective(see below)
> >
> > My main goal is to connect a Digital camera directly to the FPGA board
> > to get a picture from the camera. Once the picture is loaded into the
> > FPGA memory i am going to compress that image and then send it to a
> > computer.
> >
> > Thanks in advance!!
> > Scott
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 53103Hi Tom, I believe slaves narrower than the CPU are fully supported via dynamic bus sizing. See pg. 69 of http://www.altera.com/literature/manual/mnl_avalon_bus.pdf. I think in SOPC Builder you only need to select "This is a memory device" - that turns on dynamic bus sizing. FYI, I haven't personally accessed code from anything other than 32-bit slaves, so if I'm wrong about this, someone please point it out. Hope that helps, Peter > Hello everybody, > > We want our 16 bit Nios to execute code from a 8 bit wide external > SRAM. The high speed parts should run from internal memory. > > Ist that possible ? I think it *must* be possible when we connect the > SRAM with our own VHLD code to the Avalon Bus. But is it also possible > without writing own logic ? > > Thanks to everybody reading this :) > > By > > TomArticle: 53104
Hi: I have a question about how to realise RS232 srial coomunication between PC an Altera APEX20KE. I have less experience . Do I need to inplement UART in APEX20KE or just implemet RS232 logic control part? Anyone can give some suggestions ? Thank you very much. Sarah(sarahshenca@yahoo.ca)Article: 53105
Here's a question I was asked by a friend and realized I have no answer for. He wants to use `include, to include a text file of comments that initializes a blockRAM, but he wants to do it conditionally based on the hierarchy of the module. That is, he wants to reuse the same module in many places, but wants to `include a different text file in each one. Here's an example of what he would like to do (although this isn't possible): // Instantiate RAM 0 defparam ram0.TEXT_FILE = "file0"; ram_module ram0 (..); // Instantiate RAM 1 defparam ram1.TEXT_FILE = "file1"; ram_module ram1 (..); //This is the code for the RAM module module ram_module (..); parameter TEXT_FILE = "something_that_will_be_passed_from_above"; `include "TEXT_FILE" endmodule Is there a way to do something like this? -KevinArticle: 53106
The actual hardware receives white noise samples...in simulation I try to use a random sequence of input samples. The input frequency is a white noise source, filtered through an analogue LP filter with cutoff 32 MHz, whilte the cutoff of the LPF is 2MHz... this problem has nothing to do with signal attenuation! adrian > Are the samples the filter receives in the actual hardware the same as the > samples you used for the simulation? What is the frequency of your input? > What kind of FIR filter (LPF, BPF, HPF) are you designing and what is the > cutoff frequency? > > Jim > > I posted a question (Ref: SDA FIR Filter) regarding the refusal of my SDA > > FIR filter to work in hardware, although it works perfectly in simulation. > I > > noticed that in the CORE generator GUI, the latency (startup latency I > > presume) was 9 clock cycles. I am feeding the filter 4 bit input samples > > every 8 clock cycles, so should get an output every 4 clock cycles. > However, > > my complaint was that I am only getting a DC output in hardware, and am > now > > wondering whether the fact that I am giving samples every 8 clock cycles > > from startup might have an effect on the filter, since the latency is 9 > > clock cycles... to me this is not possible, but I am getting desperate!!! > > > > adrian > > > > > >Article: 53107
"Stamatis Sotiropoulos" <ssothro@hotmail.com> wrote in message news:b3v7cu$21ja$1@ulysses.noc.ntua.gr... Regarding bypass Capacitors, is it important to use SMD Capacitors (like Y5V)? I intended to use classic MKT-370 capacitors... AFAIR, MKT is a foil capacitor. Therefore it is absolutely unsuitable for supply bypassing. Use ceramic types: Y5V or X7R. DziadekArticle: 53108
Hi Panzo,
Although I have little experience with Genetic FPGA for JBits, I believe
that the following two pieces of information from
...\JBits2.8\doc\GeneticFPGA\GeneticFPGA.html will be of interest to you:
"The Virtex Device Simulator does not support the Global Set Reset
functionality nor provide support for the SRAMs. It is suggested that
GeneticFPGA be used with the Celoxica RC1000pp board."
"The API to the user code has changed. User code generated for previous
versions will not work with this version. The user code should be either
updated or previous versions should be maintained."
After reading the GeneticFPGA.html file, it would seem that it is not
possible to run GeneticFPGA without a Celoxica board (see the requirements
section) in JBits 2.8. Perhaps it is possible with the VirtexDS in earlier
versions of the tool, as the section "Changes to Version 2.8" might suggest.
Also, you might try posting this message on the JBits newsgroup at yahoo
groups and reviewing the messages there as I recall some discussion about
this subject a few months ago. (You might also wish to subscribe to
jbits@yahoogroups.com from www.yahoo.com)
Hope this helps,
Alex Carreira
> "panzo" <panzo@wanadoo.fr> wrote in message
news:b3i2nh$3dr$1@news.cict.fr...
> Hi,
>
> I'm lookin for someone who has some experience with Jbits tool ,
especially
> the genetic hardware part. I need help with some examples provided with
the
> Genetic FPGA classes from the Jbits library.
> I can't get work the examples named Prec1x1, 2x2 ... and following
> I work with the virtex simulator VirtexDS configured as the XCV100 board.
> The compiler says that the CoreTemplate class throws the exception :
"Device
> XCV50 was specified, but Device XCV1000was targetted". I wonder if the
> genetic FPGA is able to work with another board than the Rc1000pp board
> (XCV1000).
> If i configure my virtexDS as XCV1000 then the compiler says a little
> farther that it could not load the SRAM onto the device.
>
> If you have succeeded to make it work yourself, please help me !!!
>
> A+.Panzo
>
>
Article: 53109Hello!! I am a beginner in FPGA/CPLD world but I am a pretty experienced ASIC designer. I am wondering if there is any simple but maybe not so efficient way to program CPLD. What I mean is, I know it is EEPROM inside CPLD that provides programmability, and the CPLD programming is merely writing to these EEPROM cells. My question is, is there any simple way (just using a few wirings without the programmer) to program CPLD? I just want to verify programmability as learning process. The CPLD I have is Atmel ATV2500BQL. It is wierd that Atmel doesn't put the programming to the datasheet (or I didn't find it?). thanks, CraigArticle: 53110
u can get some useful thing at www.t10.org "Marlboro" <ccon67@netscape.net> wrote in message news:ee7c1c3.-1@WebX.sUN8CHnE... Hi group, I wonder if someone has designed an ultra320 SCSI (SPI-4) interface in FPGA, please direct me a start point, reference sites, or any thing related, Thanks alot.Article: 53111
Hi guys, I'm trying to configure 2 cpu Nios processor using the SoPC Builder. Firstly I tried creating 2 independent system modules but the Quartus Leonardo level1 synthetizer caused an error argueing that there were some "vhd" files that didn't cohere with one of the system modules that I've created. So I tried creating an unique Nios system module which have had incorporated the both CPUs. But when I try to synthesize with Leonardo Spectrum level 1 it causes a Quartus internal error that impedes me doing anything. I use a dual port ram to enable the comunication between both CPUs, but as you'll image I haven't proved it yet. I would be very grateful if someone could help me. Arkaitz. Note: I've tried with Quartus v1.1 and Quartus v2.1. Both of them are Limited Edition.Article: 53112
Hi all, I am trying to implement a design in virtex device. My design contains quite a few latches (intended). When I implement the design and open the design in the FPGA editor, I see that the latches are implemented using LUTs and not using the registers in the slice. The device contains free resources of registers. Is there a way, I can force the latches to be implemented in registers (other than using primitives)? I would prefer the code to be portable. My code (VHDL) for latch looks something like this: process (enable, din) begin if (enable = 0) then dout <= din; else dout <= dout; end if; end process; Thankyou for your time, JenifferArticle: 53113
I am trying to make a design which uses an Asynchronous Fifo created using Xilinx Coregen programme. I synthesise the project using Synopsys' Fpga-Compiler II. It synthesises ok. When I view the schematic there is just a FIFO box created (you cannot look inside it). Anyway, when I create the project using Dsgnmgr the translation fails (I create new project using the .edf file as the source). The following error is reported: ERROR:NgdBuild:604 - logical block 'design/FIFO' with type 'fifo127deep_18wide' is unexpanded. Symbol 'fifo127deep_18wide' is not supported in target 'spartan2'. however, looking at the xilinx website, the fifo is supported for Spartan II. Anyone know if I'm doing something obvious wrong? Any help would be much appreciated. Regards, PatrickArticle: 53114
Craig Tsui <shaqt@yahoo.com> wrote: : Hello!! : I am a beginner in FPGA/CPLD world but I am a pretty experienced ASIC : designer. I am wondering if there is any simple but maybe not so : efficient way to program CPLD. What I mean is, I know it is EEPROM : inside CPLD that provides programmability, and the CPLD programming is : merely writing to these EEPROM cells. My question is, is there any : simple way (just using a few wirings without the programmer) to : program CPLD? I just want to verify programmability as learning : process. Most CPLD have a JTAG interface. Most vendors have a simple Parallelport Jtag programer published. : The CPLD I have is Atmel ATV2500BQL. It is wierd that Atmel doesn't : put the programming to the datasheet (or I didn't find it?). I don't know about Atmel. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 53115
Uwe Bonnes wrote: > Craig Tsui <shaqt@yahoo.com> wrote: > : Hello!! > > : I am a beginner in FPGA/CPLD world but I am a pretty experienced ASIC > : designer. I am wondering if there is any simple but maybe not so > : efficient way to program CPLD. What I mean is, I know it is EEPROM > : inside CPLD that provides programmability, and the CPLD programming is > : merely writing to these EEPROM cells. My question is, is there any > : simple way (just using a few wirings without the programmer) to > : program CPLD? I just want to verify programmability as learning > : process. > > Most CPLD have a JTAG interface. Most vendors have a simple Parallelport > Jtag programer published. > I once tried exactly that. Operating that JTAG from another software than it was intended is not that trivial. AFAIR, that JTAG interface is not published. Instead I was told to use some other interface which should have required 15k of code, about the size of the controller it was connected. I spared about 1k or two for the interface. Lucky me that I didn't sell the programmability before I had it. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 53116
Hi all, I am considering the future hardware platforms for our designs. As our groups have a wide experience with unix environments (we have been using Solaris for a while, now), we would like to continue in this world. Basically all the EDA tools we need run for either Solaris, HP and some of them now, Linux. I am not going to list all the pro's and con's of these platforms, we have already heard enough about it. What I am mostly curious about is the feasibility of Mac based FPGA design. Mac Os X is a nice and SUPPORTED Unix OS, and the Xservers from Apple are not too expensive compared to equivalent Intel boxes... And with the rumored advent of the 970 chips from IBM they might become even more interesting. Of course none of EDA tools we use (Modelsim, Leonardo, Synplify, Xilinx Alliance...) have native versions for Mac OS X. What do you all think about this? Should we press the EDA vendors to come up with yet-another-supported-platform? Regards, TomasArticle: 53117
12.what is the difference between HIT and D_done in PCI target state machine? waiting for Your reply thank in advance praveenArticle: 53118
Thank you . I prefer the chip APEX20K , but it is FPGA or CPLD, How to differentiate FPGA from CPLD? and are there mang differences of the programming between FPGA and CPLD ? :) brad@tinyboot.com (Brad Eckert) wrote in message > > Both companies claim to have the lowest cost FPGAs. 8-) > > I haven't used Altera, so I can't make a good comparison. But, > installing ISE Webpack was very easy. I got the CD and a product key > from Xilinx for free, and it will run forever. The next thing I knew I > was pushing buttons and synthesizing and fitting VHDL. Too cool. > > Altera uses a third party synthesis tool with Quartus, so licensing > isn't so simple. AKAIK the Mentor evaluation license lasts for 30 > days.Article: 53119
Hi, everyone, I finished the verilog code. I simulated it by Modelsim. Now I want to run it on ISE 5.0 ISE complains that my test bench module has no port list. What shall I do now? Shall I prepare my test bench driver in another way? THANKS BuctherArticle: 53120
Thanks, Ray. But how can I update libraries? I contacted people in Aldec support, and they didn't give me any clear answer. They just told me it would be if I buy new edition ( $4K for Xilinx edition). My idea is to start developing some serious stuff in FPGAs for company I work in, but I first have to show "some" results with what we already got, before I start pursuading my chief to buy some real stuff. Thanks, Goran Ray Andraka <ray@andraka.com> wrote in message news:<3E640E13.EB3569B6@andraka.com>... > XST does a fine job, much better than foundation did. You will be happy with it. You can use your Aldec for both > pre-PAR and post route simulations. Aldec 3.2 is getting a bit long in the tooth now, the current version is 5.2. Just > make sure your unisim and simprim libraries have been updated and you should be fine though. For what it is worth, the > later editions of Aldec fixed a few annoying bugs in 3.2, increased the simulation speed considerably, and added > features. You'd probably find the update to be well worth the money when you can afford it. > > Goran wrote: > > > kevinbraceusenet@hotmail.com (Kevin Brace) wrote in message news:<cc7b0b5f.0302231456.ce5e3f9@posting.google.com>... > > > > Kevin, > > Thanks for answer. > > > > > Goran, > > > > > > Which Xilinx part are you planning to target? > > > > Spartan IIe, smaler Virtex (mainly because multipliers).Below 300K > > gates. > > > > > As long as you are targeting Xilinx devices below 300K system gates or > > > you don't have to target a 2.5V Virtex device, you may want to try the > > > free ISE WebPACK first before paying for ISE BASE-X. > > > Unlike ISE BASE-X users, ISE WebPACK users won't have access to FPGA > > > Editor or CORE Generator, but if those tools aren't important to you, > > > you should be fine with ISE WebPACK. > > > > I would like to use CORE Generator. I think it's a nice thing and ISE > > baseX doesn't seem to expencive. I don't like paying every year, > > but... > > > > > Regarding ModelSim XE, you may want to try ModelSim XE-Starter > > > first before paying for ModelSim XE. > > > Yes, ModelSim XE-Starter has a 500 statements limit, but what that > > > really means is that the simulation speed will drop after that limit, > > > and the simulator will still continue to run past that limit. > > > In the past, I have simulated a design that exceeded the 500 > > > statements limitation by 40,000 lines, but ModelSim XE-Starter > > > completed the simulation fine. > > > However, it took quite a time to complete because I was doing a Post > > > P&R simulation of a design, and a Post P&R simulation is inherently > > > very slow compared to an RTL simulation. > > > > The problem is we have some older version of Aldecs ActiveVHDL, I > > think 3.2. I did lot of behavioral simulations on this one, and I like > > it. My question is can I import post place & route design from ISE and > > perform simulation in ActiveVHDL 3.2? I'm beginer in this, so really > > need help! > > > > > I also agree with Spam Hater that XST's synthesis quality is > > > good, so unless you don't mind paying $8,000 for a third party > > > synthesis tool, I will just use XST. > > > > Lot of people are saying XST is OK. Since I mind paying that much I'll > > go with XST. > > > > Regards, > > Goran > > > > > > > > > > > Kevin Brace (If someone wants to respond to what I wrote, I prefer if > > > you will do so within the newsgroup.) > > > > > > > > > > > > goran@net.yu (Goran) wrote in message news:<3c0f6336.0302221215.1ab0ed0d@posting.google.com>... > > > > Hi all, > > > > I work in small, development company, and we would like to start some > > > > more advanced FPGA designs (we are now using Xilinx FPGAs for simple > > > > glue logic only). My question is what tools we need to complete medium > > > > sized projects on Spartan IIe & smaller Virtex members. > > > > I learned (on Xilinx web site) that ISEbaseX would be OK? > > > > Does "one year license" that you buy from Xilinx mean your software > > > > stops working after one year, or you just don't have access to > > > > updates? > > > > If we purchase ModelSim XE does the same license apply? > > > > Can we use another VHDL simulator for post place & route simulation? > > > > We have, for example, Active VHDL, can we use it? > > > > How does XST behave, do we have to buy other synthezis tool to compile > > > > anything more advanced? > > > > Thanks in advance, > > > > Goran. > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 53121
Jeniffer wrote:
> Hi all,
> I am trying to implement a design in virtex device. My design contains
> quite a few latches (intended). When I implement the design and open
> the design in the FPGA editor, I see that the latches are implemented
> using LUTs and not using the registers in the slice. The device contains
> free resources of registers. Is there a way, I can force the latches to
> be implemented in registers (other than using primitives)? I would
> prefer the code to be portable.
>
> My code (VHDL) for latch looks something like this:
>
> process (enable, din)
> begin
> if (enable = 0) then
> dout <= din;
> else
> dout <= dout;
> end if;
> end process;
>
> Thankyou for your time,
> Jeniffer
The way you describe your latch forces the synthesis tool to build an
multiplexer ("output is either this or that..."), hence the LUT usage. Simply
omitting the else-branch of your if-statement ("output is this only
if...")should do it.
HTH
Jens
Article: 53122Patrick Twomey wrote: > > The following error is reported: > ERROR:NgdBuild:604 - logical block 'design/FIFO' with type 'fifo127deep_18wide' > is unexpanded. Symbol 'fifo127deep_18wide' is not supported in target 'spartan2'. > > however, looking at the xilinx website, the fifo is supported for > Spartan II. > Anyone know if I'm doing something obvious wrong? Any help would be > much appreciated. Hi Make sure the file "fifo127deep_18wide.edn" is present in your synthesis directory. NicolasArticle: 53123
[This followup was posted to comp.arch.fpga and a copy was sent to the cited author.] > Hi, > > I need to be able to programme the following parts on a board :- > > Altera EP2LC20 (I think that's the configuration device) > Altera EP20K100E (FPGA) > > I have the .pof file from the guy who did the design and I'm looking > for the simplest way of programming these parts through the ISP > connector (I don't really want to get into the design software). I > have built a ByteBlasterMV cable using the design on the Altera site. > Could someone advise as to which software to download and what the > settings should be? > > Many thanks > Simon Fisher > Swansea UK > Goto: https://www.altera.com/support/software/download/sof- download_center.html Click on the "ASAP2 (AlteraŽ Stand-Alone Programmer) " link. Install !!! -- Greg Deuerling Fermi National Accelerator Laboratory P.O.Box 500 MS368 Batavia, IL 60510 (630)840-4629 FAX (630)840-5406 Electronic Systems Engineering Group Work: egads@fnal.govArticle: 53124
Thanks Chris and Marc
I've tried both of your suggestions (Setup 1 corresponds to Chris's
suggestion, Setup 2 to Marc's), as yet with no success. Below are the
configurations I've tried and the post place and route results produced by
them. All setups produce the same simulation results (using Active HDL
5.2XE). As explained in my first post, I wish to have two clock domains
(called CLK1 and CLK2 below) running at different frequencies. CLK1 = M/D *
CLK2 where M and D are integers used to set up the DCMs as described in the
Xilinx data sheets. I'm aiming at 80 MHz for CLK1 and 120MHz for CLK2. I'm
using Xilinx ISE 4.2i (SP3) with XST.
Setup 1
Please view in a fixed-width font such as Courier.
+-------------------------------------+
| |
| |
| DCM1 |
| +-----------+ |
| | | |BUFG1 |
+---+clkfb | |\ |
|IBUFG | | | \ | CLK1
|\ | clk0+------------+ /-----+--------
| \ | | | /
--+ /--------+clkin | |/
| / | |
|/ | | +--------------------+
| | | | |
| clkfx+---+ | DCM2 |
| | | | +-----------+ |
| M=1 | | | | | |
| D=1 | | +-+clkfb | |
| | | | | |
+-----------+ | | clk0+------+
| | |
+------+clkin |
| | |BUFG2
| | |\
| | | \ CLK2
| clkfx+------+ /------
| | | /
| M=3 | |/
| D=2 |
| |
+-----------+
With this setup I get the following results from the post place and route
report:
levels of logic for CLK1: 5
delay: 59075 ns
levels of logic for CLK2: 4
delay: 19138ns
It seems to me that something has gone seriously wrong here. The delays are
too big to make any sense of.
Setup 2
Please view in a fixed-width font such as Courier.
+-------------------------------------+
| |
| |
| DCM1 |
| +-----------+ |
| | | |BUFG1 |
+---+clkfb | |\ |
|IBUFG | | | \ | CLK1
|\ | clk0+------------+ /-----+--------
| \ | | | /
--+ /--+-----+clkin | |/
| / | | |
|/ | | |
| | | |
| | clkfx+---+
| | |
| | M=1 |
| | D=1 |
| | |
| +-----------+
|
| +--------------------+
| | |
| | DCM2 |
| | +-----------+ |
| | | | |
| +-+clkfb | |
| | | |
| | clk0+------+
| | |
+-----+clkin |
| | |BUFG2
| | |\
| | | \ CLK2
| clkfx+------+ /------
| | | /
| M=3 | |/
| D=2 |
| |
+-----------+
With this setup I get the following results from the post place and route
report:
levels of logic for CLK1: 4
delay: 9.670 ns
levels of logic for CLK2: 19
delay: 8.399 ns
This time it seems as though CLK2 has not been recognised as a clock net
(despite a BUFG being explicitly instantiated), and it has been buffered a
number of times in order to handle the high fanout. This explains the high
levels of logic.
Setup 3
Please view in a fixed-width font such as Courier.
+-------------------------------------+
| |
| |
| DCM1 |
| +-----------+ |
| | | |BUFG1 |
+---+clkfb | |\ |
|IBUFG | | | \ | CLK1
|\ | clk0+------------+ /-----+--------
| \ | | | /
--+ /--------+clkin | |/
| / | | |BUFG2
|/ | | |\
| | | | \ CLK2
| clkfx+-----+ /------
| | | /
| M=3 | |/
| D=2 |
| |
+-----------+
With this setup I get the following results from the post place and route
report:
levels of logic for CLK1: 4
delay: 11.507 ns
levels of logic for CLK2: 19
delay: 8.997 ns
In this setup, the name "CLK2" is not recognised. Instead all timing
reports refer to a net name like TS_N1064. Again it would seem that CLK2
(TS_N1064) has not been recognised as a clock net.
If I change my design to have two input clock pins as shown below, then I
have none of these problems.
Please view in a fixed-width font such as Courier.
+-------------------------------------+
| |
| |
| DCM1 |
| +-----------+ |
| | | |BUFG1 |
+---+clkfb | |\ |
|IBUFG | | | \ | CLK1
|\ | clk0+------------+ /-----+--------
| \ | | | /
--+ /--+-----+clkin | |/
| / | | |
|/ | | |
| | | |
| | clkfx+---+
| | |
| | M=1 |
| | D=1 |
| | |
| +-----------+
|
| +--------------------+
| | |
| | DCM2 |
| | +-----------+ |
| | | | |
| +-+clkfb | |
|IBUFG| | | |
|\ | | clk0+------+
| \ | | |
--+ /--+-----+clkin |
| / | | |BUFG2
|/ | | |\
| | | | \ CLK2
| clkfx+------+ /------
| | | /
| M=3 | |/
| D=2 |
| |
+-----------+
Post place and route results for the above setup are as follows:
levels of logic for CLK1: 2
delay: 9.789 ns
levels of logic for CLK2: 2
delay: 7.899 ns
If needs be I will modify the hardware to allow for two incoming clock pins.
However, if possible I would like to find out if it's possible to achieve
what I want without any hardware changes. Am I doing something wrong??
Many thanks
Sam
"Marc Randolph" <mrand@my-deja.com> wrote in message
news:15881dde.0303030436.1ddddb75@posting.google.com...
> chris.rosewarne@calyptech.com (Chris Rosewarne) wrote in message
news:<ef33e8a7.0303021535.2765a886@posting.google.com>...
>
> > "Sam Duncan" <damn_spam2001@yahoo.co.uk> wrote in message
news:<b3nmd8$1osp5j$1@ID-167554.news.dfncis.de>...
> > > Hi
> > >
> > > I'm using an XC2V1000 and trying to drive two global clock nets at
different
> > > speeds (using DCMs), using only one clock input pin. I get errors
from
> > > ngdbuild if I try to drive two IBUFG's from the same pad. If I drive
one
> > > IBUFG and split the output to two DCM's, the levels of logic reported
on my
> > > clock net (post place and route) increase from 2 to 19. Is it
possible to
> > > drive two DCM's and two clock nets from one input pin, or should there
be a
> > > separate input for every DCM/clock net?
> > >
> > > Many thanks
> > >
> > > Sam
> > Sam,
> >
> > The way to do it is to drive the DCM #2 with the output from DCM #1.
> > DCM #1 is driven by the IBUFG in this case.
> >
> > regards,
> > Chris
> >
>
> Howdy,
>
> I have found that cascading DCMs is typically only necessary if you
> have either exceeded the divide/multiply abilities of the DCM, or if
> you require a derived clock to be locked to a divided clock (because
> there is no phase guarantee when using two DCM's in parallel to do
> dividing).
>
> To answer the original posters question, I have run 3 DCM's off a
> single global input. I didn't even have to call out an IBUFG as I
> recall (Synplify did it, I assume).
>
> Be aware that engineering sample Virtex-II's had restrictions on which
> GBUF's could drive which DCM's - since I assume you are using
> production parts, it seem unlikely that could be what you are up
> against. But perhaps you still have the _ES environment variable set?
>
> Marc
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