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Talk to Annapolis, I'm sure they'd be happy to get you the latest drivers
(assuming you are a paying customer, of course!). It is in their best
interest for you to have a positive experience. None of the people I
know there bite either.
ABloke wrote:
> Does anyone out there have the latest drivers for their Wildcard (The
> CardBus one with a V300)? I can't seem to find them on their website
> or anywhere else on the web.
>
> Thanks
>
> A
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52401Theron Hicks (Terry) <hicksthe@egr.msu.edu> wrote in message news:3E431E87.905ECF6F@egr.msu.edu... > 2. Has anyone had any experience with either USB2 or 100mB or > firewire as an interconnect to an FPGA based design? I have used the Philips PDI1394L40 link chip and their P23 phy to stream firewire isochronous data in and out of FPGAs. Philips has some eval kits that have a microcontroller with software for implementing the firewire node. You just hook the FPGA to the L40's buffered DMA ports and stream the data. Writing the PC driver can be an ordeal, at least it was for us. Firewire cable max length is 4.5 meters. In practice I hear you can go much longer. Also, a repeater is inexpensive to build, it is just a cable powered phy chip. -JeffArticle: 52402
This is a loaded question. If you have 20 years of design experience and I have 2 years, are we both worth $100/hour. I am sure you understand that we are not. But, it dosen't hurt me to ask for $100/hour. I just may not get much work. If you are going thru a head shop, these prices will vary greatly. Austin Franklin wrote: > "Gregory C. Read" <readgc.invalid@hotmail.com.invalid> wrote in message > news:9iD0a.5636$5g7.336@nwrddc02.gnilink.net... > >>What is the current range of salaries for short term contract work for > > FPGA > >>designers? > > > Er, well, that all depends on the level of experience, what the job entails, > skill of the individual, and what the terms of the contract are...as in do > you supply equipment, or does the client? > > Anywhere from $25/hour to $250/hour. Give me more info, and I'll give you a > better answer ;-) > > Austin > >Article: 52403
I am thinking of using a XC9536XL in a new design, I want the processor to be able to reprogram the CPLD. Is this possible with this part - if so is there any information about the programming algorithm? How big is the bitstream for one of these? Thanks for your help RalphArticle: 52404
I don't have my main computer available right now, so I cannot show you exactly how to do it, but try adding "keep" attribute to a wire if you are using Verilog. That prevents XST from optimizing the logic away. You can add "keep" attribute to your RTL code or through a synthesis constraint file. I personally recommend the synthesis constraint file approach because it will keep the RTL code synthesis tool vendor independent. Kevin Brace (If someone wants to respond to what I wrote, I prefer if you will do so within the newsgroup.) Jim Raynor wrote: > > hi, > > does anyone know how to tell the synthesis tool not to remove the > duplicate logic? I am using Xilinx Foundation and synthesis tool is > XST....the target device is Virtex-E.. >Article: 52405
"Theron Hicks" <hicksthe@egr.msu.edu> wrote in message news:b20hb8$130l$1@msunews.cl.msu.edu... > Aurash, > Good idea but 2 problems. > > 1. The cost for the chip is about $110 compared to about $15 for the > xc2s50e that I am using. This may be a minor cost differential when I add > the cost of a fully integrated ethernet solution. However, I suspect that > an integrated solution can be had for substantially less than $95 US. > > 2. The real show stopper for me is the package for this part. It is a > BGA package. I know that you folks say that the BGA is no big deal but for > me it is. I am just now getting used to fine pitch leaded packages. > > However, thanks for the response. I will keep it in mind if the rest of the > responses are less ideal. > > Thanks, > Theron Hicks > > could always use a seperate ethernet chip something like a lan91c111 chip or other 100Mbs chip has drivers for linux,vxworks, wince and windows http://www.smsc.com/main/catalog/lan91c111.html lot of info comes up with a google search. http://www.uclinux.org/pub/uClinux/archive/9160.html http://www.8052.com/users/sknapp/web_ethernet.phtml http://www.egnite.de/pipermail/en-nut-discussion/2002-October/000133.html "We decided to use the LAN91C111 because of the possibility to design boards for industrial temperature ranges. I've just received a prototype from another company with this chip and started to write the device driver for Nut/OS. However, the LAN91C111 has its drawbacks. It consumes a lot power and its expensive. On the other hand the Asix chip is NE2000 compatible and should make it easy to create a Nut device driver."Article: 52406
Jussi Lähteenmäki <jusa@students.cc.tut.fi> wrote in message news:<b1qegk$l3j$1@news.cc.tut.fi>... > I've always wondered why they call it CE (clock enable) when in fact its > DE (data enable). In the wonderful world of ASICs gated clocks are > often preferred, when power consumption is of concern. In these flip-flops > clock signals are anded with CE. The hard task is controlling the CE > signals... > > regards, > juza Didn't "Clock Enable" originate from motion that data is "Clocked In" ? I agree that it is somewhat misleading if we think about to much, but than, as it has been pointed out, many other things are as well ! Cheers, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV -----Article: 52407
Hello , i designed a VHDL program with XC2C256 coolrunner 2 and the timing analysis of Xilinx ISE5 says eg. Max internal clock frequency 44Mhz ,min period 22ns . Therefore does this imply that i can use a oscillator as a clock input for a max of 44Mhz , anything exceeding that would cause the design to be unstable ? BTW: any advice on double -edge clocking? Thanks in advanceArticle: 52408
On Fri, 7 Feb 2003, Ray Andraka wrote: > Not without using or blocking the second half of the slice. What is the > motivation for doing a carry save adder here? The ripple carry arithmetic uses > half the area (because of the carry chain logic) and a tree made of FPGA ripple > carry adds is faster than one made of carry save adds because of the hit you take > on the routing. See my multipliers page on my website for a bit more detail (under > wallace tree multipliers). I implement an algorithm for a modular multiplication. Unfortunately this algorithm depends highly on the use of a Carry-Save-Adder. As I have to prove the case for the algorithm, there is no way out :) Best wishes, Lars. -- GnuPG public key: http://www.ida.ing.tu-bs.de/~larsu/larsu_ida_ing_tu-bs_de.keyArticle: 52409
Tan Peng Khiang <tpkcbq@singnet.com.sg> wrote: : Hello , i designed a VHDL program with XC2C256 coolrunner 2 and the : timing analysis of Xilinx ISE5 says eg. Max internal clock frequency : 44Mhz ,min period 22ns . : Therefore does this imply that i can use a oscillator as a clock input : for a max of 44Mhz , anything exceeding that would cause the design to : be unstable ? Yes. Look at the timing report and rethink the logic with the longest pathes. : BTW: any advice on double -edge clocking? Whats your question? Double -edge clocking with XC2C works as expected... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 52410
"Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> schrieb im Newsbeitrag news:fR%0a.75730$F63.1556956@news.xtra.co.nz... > I am thinking of using a XC9536XL in a new design, I want the processor to > be able to reprogram the CPLD. > > Is this possible with this part - if so is there any information about the > programming algorithm? It is, have a look at xapp58. > How big is the bitstream for one of these? Have a look in the datasheet, ort simply create a dummy MCS file. -- MfG FalkArticle: 52411
"RC" <rado3@poczta.onet.pl> wrote in message news:<b1vrfn$52o$1@atlantis.news.tpi.pl>... > Hello, > > Can someone tell me which company sells reconfigurable multicontext FPGA > devices? > > Thanks in advance, > Regards, > Rado No one AFAIK. I do remember seeing academic papers on it from Stanford U & others IIRC! The process of reconfiguring is still slow, ie maually time shared. If you need instant HW swap, the only available solution would be N up FPGA size and put in N cases, not quite the same thing and obviously N*$. Really bad if you have N>2.Article: 52412
Hello,
johnjakson@yahoo.com (john jakson) writes:
>> Can someone tell me which company sells reconfigurable multicontext FPGA
>> devices?
>> Thanks in advance,
>> Regards,
>> Rado
>
> No one AFAIK.
You are right. In recent time I looked through some papers, and there
are no commercial multicontext FPGAs available.
I do remember seeing academic papers on it from Stanford
> U & others IIRC!
Here are some references:
M. Motomura, Y. Aimoto, A. Shibayama, Y. Yabe, M. Yamashina: An
embededded DRAM-FPGA with instantaneaous logic reconfiguration. In
1997 "Sysmposium on VLSI Circuits Digest of Technical Papers" (June
1997), pp. 55-56
S.M. Scalera, J.R. Vazquez: The Design and implementation of a context
switching FPGA "IEEE Symposium on Field-Programmable Custom Computing
Machines" (April 1998), pp. 495-498
S. Trimberger, D. Carberry, A. Johnson, J. Wong: A time-multiplexed
FPGA. In "Proceedings of IEEE Workshop on FPGAs for Custom Computing
Machines" (April 1997), pp. 22-28
I hoped it helped you
Florian
--
int m,u,e=0;float l,_,I;main(){for(;1840-e;putchar((++e>907&&942>e?61-m:u)
["\t#*fg-pa.vwCh`lwp-e+#h`lwP##mbjqloE"]^3))for(u=_=l=0;79-(m=e%80)&&
I*l+_*_<6&&26-++u;_=2*l*_+e/80*.09-1,l=I)I=l*l-_*_-2+m/27.;}
Article: 52413On Thu, 06 Feb 2003 18:48:40 -0800, Theron Hicks (Terry) wrote: > Hi, > I am looking at design upgrade of an existing instrumentation > project. Currently the design talks over a high speed bus to a rather > expensive (~$1600 US) parrallel digital input board. The data rate > would be on the order of 50M bits per second not including any overhead. > I do not think I want to go to an all FPGA based solution. Currently > the FPGA in the system is the smallest Spartan2e series device. By the > way, quantities are very small, on the order of less than 50 pieces per > year. > > So here are my questions... > > 1. Does anyone happen to know what the USB2 or firewire is rated for > in terms of the longest cable length? I had thought USB2 was limited to > about 2 meters but I have seen USB cables about 5 meters long recently. > A longer length interconnect would appear to be desireable. I know that > ethernet is good for several hundred meters. That would be far beyond > my needs. > > 2. Has anyone had any experience with either USB2 or 100mB or > firewire as an interconnect to an FPGA based design? > > 3. Do you happen to have any recommendations as to a possible > off-the-shelf solution (either a small board or a 1 or two chip > solution, ideally something with a demo board available)? > > Thanks, > Theron Hicks Since it looks like you just need a point to point (full duplex?) link, why not just use a 100BT Ethernet PHY. You do not need an Ethernet MAC in your FPGA at all since you are only doing a simple point-point link, just the simple machinery to send and recieve nibbles from the PHY... Using 100BT Ethernet physical layer has the advantage of long inexpensive cables (50 meters?) and electrical isolation Not sure what the PLL sync delay in the PHY is so you probably want to be sending fairly large packets to reduce the % of overhead... Peter WallaceArticle: 52414
In article <b235lh$n01$03$1@news.t-online.com>, Florian-Wolfgang Stock <f.stock@tu-bs.de> wrote: >S. Trimberger, D. Carberry, A. Johnson, J. Wong: A time-multiplexed >FPGA. In "Proceedings of IEEE Workshop on FPGAs for Custom Computing >Machines" (April 1997), pp. 22-28 This one, a Xilinx design for a multicontext XC4000, was basically killed as a potential product because context switching draws a LOT of power, especially in all the interconnect bits, and they envisionsed multicontext being used to virtualize larger circuits. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 52415
Hello, can we estimate the area/speed effect on an FIR implementation when the input wordlength is increased say by one bit either for parallel or serial arithmetic for a multiplier, we can assume that if a coefficient wordlength is N, when increasing the multiplicand wordlength by 1, we need to allocate roughly one LUT for each partial product. therefore we can deduce that the area increase in the multiplier implementation is is N+log2(N).... is that true Regards -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 52416
Hello, can we estimate the area/speed effect on an FIR implementation when the input wordlength is increased say by one bit either for parallel or serial arithmetic for a multiplier, we can assume that if a coefficient wordlength is N, when increasing the multiplicand wordlength by 1, we need to allocate roughly one LUT for each partial product. therefore we can deduce that the area increase in the multiplier implementation is is N+log2(N).... is that true Regards -- Ce message a ete poste via la plateforme Web club-Internet.fr This message has been posted by the Web platform club-Internet.fr http://forums.club-internet.fr/Article: 52417
Is there anything equivalent to JBits for Altera devices? I'm dearly hoping so ...Article: 52418
Haven't used the simulator much, but my Quartus II 2.2 locks up probably once a day during compiling just as it finishes the initialization stage. Peter > I've been having some problems with Quartus II 2.2 and I'd be interested to > hear if anyone else has had similar experiences: > > 1) For a while I have been successfully using the Quartus II simulator but > recently a strange phenomenon has stopped me. I define the input waveforms > in the .vwf file and run the simulator. All appears to run OK but the output > waveforms in the Simulator messages window do not appear correctly. For > example, the input clock signal just appears to be low all the time. > Scrolling in time is only possible by dragging the marker along - using the > left or right arrows doesn't work. Changes in the input waveforms do occur > when these random positions are visited. It's as if I'm zoomed in to a tiny > resolution and can only see a small area of the waveforms. Trying to zoom > out has no effect. > > 2) Quartus II hangs up now and again (Win XP professional, P4 1.8GHz, 384MB) > sometimes when the compiler is running, sometimes during simulation. > Re-installing from the CD as changed nothing. It would be neat to blame all > this on file corruption but I don't believe it is. > > Any suggestions anyone? > > Thanks. > > Rog.Article: 52419
Hi, 1394a FireWire is officially rated for 400MBit/sec communications across cable lengths up to 4.5m. Longer cable lengths are not recommended, but possible. We have a couple of products that integrate FPGA and DSP technology with ready to use FireWire interfaces. The FPGA implements the software stack and all asynchronous communications. Isochronous communications is streamed through the FPGA. The ultra-compact UC1394a might be of interest. It is really small (30mm x 36mm in a 116pin PLCC form factor), and combines a 50kGate Spartan-II FPGA, TMS320C5509 DSP (up to 400MIPS) and an on-board FireWire interface. http://www.traquair.com/products/ultracompact/uc1394a.html For more computationally intensive applications, the C6713Compact combines a 1MGate Virtex-II FPGA, TMS320C6713 DSP (up to 1800 MIPS or 1350MFLOPS), and on-board FireWire. http://www.traquair.com/catalog/microline.products.html Hope this helps. Regards, Steve Bradshaw Traquair Data Systems, Inc. http://www.traquair.com "Theron Hicks (Terry)" <hicksthe@egr.msu.edu> wrote in message news:3E431E87.905ECF6F@egr.msu.edu... > Hi, > I am looking at design upgrade of an existing instrumentation > project. Currently the design talks over a high speed bus to a rather > expensive (~$1600 US) parrallel digital input board. The data rate > would be on the order of 50M bits per second not including any > overhead. I do not think I want to go to an all FPGA based solution. > Currently the FPGA in the system is the smallest Spartan2e series > device. By the way, quantities are very small, on the order of less > than 50 pieces per year. > > So here are my questions... > > 1. Does anyone happen to know what the USB2 or firewire is rated for > in terms of the longest cable length? I had thought USB2 was limited to > about 2 meters but I have seen USB cables about 5 meters long recently. > A longer length interconnect would appear to be desireable. I know that > ethernet is good for several hundred meters. That would be far beyond > my needs. > > 2. Has anyone had any experience with either USB2 or 100mB or > firewire as an interconnect to an FPGA based design? > > 3. Do you happen to have any recommendations as to a possible > off-the-shelf solution (either a small board or a 1 or two chip > solution, ideally something with a demo board available)? > > Thanks, > Theron Hicks >Article: 52420
Rather than trying to overclock your design, if you need the speed look at the "critical paths" in your design that limit the timing to 44MHz. The timing analyzer that's part of the Xilinx imlpementation tools will let you see what your worst-case paths are. Often, it's straightforward to implement a piece of "slow" logic that has to go through several levels of logic into fewer logic levels. If you find that you've got too much logic to go from register to register without all the delay you're seeing, you can consider pipelining. If you can wait en extra clock cycle for your result, you can do half of the logic on the first clock cycle and half the logic on the next clock cycle. You get your results out a cycle later but if you pipeline correctly, you get a proper answer every clock period. As an example, if you have an adder that's a+b+c (each of these three values are registers a few bits wide) you can register the result of a+b and register the c value so on the next cycle you can get your final result. The intermediates aplusb = a+b and r_c = c can give you sum = aplusb + r_c. Pipelineing. If you try doubling the clock using the special feature in the Coolrunner-II devices, you won't improve your timing overall. Since it takes 22 ns to get from one register to another, if you split half the logic into the first 11 ns and the other half into the next, you add another setup time and clock-to-out for the intermediate register making the overall timing worse. Have fun with the design! "Tan Peng Khiang" <tpkcbq@singnet.com.sg> wrote in message news:3E44D5FD.3730@singnet.com.sg... > Hello , i designed a VHDL program with XC2C256 coolrunner 2 and the > timing analysis of Xilinx ISE5 says eg. Max internal clock frequency > 44Mhz ,min period 22ns . > > Therefore does this imply that i can use a oscillator as a clock input > for a max of 44Mhz , anything exceeding that would cause the design to > be unstable ? > > BTW: any advice on double -edge clocking? > > Thanks in advanceArticle: 52421
Just curious if anyone has booted WIN CE or CE.NET on any of the available embedded processors available from Xilinx or Altera: MicroBlaze, PowerPC VIIPro, Excalibur ARM, or NIOS? If so, what was your experience? -Guy g.schlact@attbi.remove2mail.comArticle: 52422
On Sat, 08 Feb 2003 08:50:09 -0800, Peter Wallace <pcw@karpy.com> wrote: >On Thu, 06 Feb 2003 18:48:40 -0800, Theron Hicks (Terry) wrote: > >> Hi, >> I am looking at design upgrade of an existing instrumentation >> project. Currently the design talks over a high speed bus to a rather >> expensive (~$1600 US) parrallel digital input board. The data rate >> would be on the order of 50M bits per second not including any overhead. >> I do not think I want to go to an all FPGA based solution. Currently >> the FPGA in the system is the smallest Spartan2e series device. By the >> way, quantities are very small, on the order of less than 50 pieces per >> year. >> >> So here are my questions... >> >> 1. Does anyone happen to know what the USB2 or firewire is rated for >> in terms of the longest cable length? I had thought USB2 was limited to >> about 2 meters but I have seen USB cables about 5 meters long recently. >> A longer length interconnect would appear to be desireable. I know that >> ethernet is good for several hundred meters. That would be far beyond >> my needs. >> >> 2. Has anyone had any experience with either USB2 or 100mB or >> firewire as an interconnect to an FPGA based design? >> >> 3. Do you happen to have any recommendations as to a possible >> off-the-shelf solution (either a small board or a 1 or two chip >> solution, ideally something with a demo board available)? >> >> Thanks, >> Theron Hicks > > > Since it looks like you just need a point to point (full duplex?) link, >why not just use a 100BT Ethernet PHY. You do not need an Ethernet MAC in >your FPGA at all since you are only doing a simple point-point link, >just the simple machinery to send and recieve nibbles from the PHY... > > Using 100BT Ethernet physical layer has the advantage of long >inexpensive cables (50 meters?) and electrical isolation > > Not sure what the PLL sync delay in the PHY is so you probably >want to be sending fairly large packets to reduce the % of overhead... They don't resync every packet if used in full duplex mode. The interface looks just like a pipe once the initial sync-up has taken place.. Regards, Allan.Article: 52423
On 7 Feb 2003 03:42:28 -0800, serebr@mailandnews.com (Valeri Serebrianski) wrote: >In Virtex-II Pro datasheet stated that PowerPC processor has 16 KByte >of instruction and 16 KByte of data cache onboard. For my application >that amount of memory is more than enough (processor speed is far more >valuable). >Is this possible to store both the program and data tables solely in >those caches without any use of Virtex-II Pro SelectRAM or external >RAM? It assumes that initial content for both caches will be stored in >main Virtex-II Pro configuration RAM and will be loaded at startup. No. You cannot initialise the caches from the bitstream used to download the FPGA; they must be read from a memory outside the PPC core :( Regards, Allan.Article: 52424
On Fri, 07 Feb 2003 18:37:00 GMT, Bob Perlman <bobsrefusebin@hotmail.com> wrote: >Hi - > >On 7 Feb 2003 08:46:28 -0800, chris.p.ward@ntlworld.com (Chris Ward) >wrote: > >>I am correct in thinking Galois and Fibonacci LFSRs are mathematically >>equivalent? >> >>If I have a generator polynomial and I implement the two architectures >>do I need to do anything different to obtain the same sequences from >>the two? >> >>Thanks >>Chris > >A Google search for "Fibonacci LFSR" returns the following link: > >http://www.newwaveinstruments.com/resources/articles/m_sequence_linear_feedback_shift_register_lfsr.htm > >There's a very nice explanation of Fibonacci and Galois LFSRs that >seems to answer your question. The program that you can download from this page: http://www.logiccell.com/~jean/LFSR/ also shows the equivalence between the two forms of LFSR. Regards, Allan.
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