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Messages from 52175

Article: 52175
Subject: Re: Group Multiple tables
From: Tullio Grassi <tullio@umd.edu>
Date: Mon, 03 Feb 2003 16:47:52 -0500
Links: << >>  << T >>  << A >>
Roberto Gallo wrote:
>     Hello there,
> 
>     I am desiging a device that uses table lookups on processing of
> information (Writing an AES core). However  as many as sixteen 256x8 bits
> tables should be used. These tables are equal in content, however they have
> independent indexing.
>     I was wondering about how to group them, so that I could use FPGAs
> memory intead of registers. Is it possible to use a multi-output memory? How
> to?
>     I am using a APEX20K200 with Quartus II 2.0 and Leonardo and writing in
> VHDL.
> 
>     Thank you,
>         Roberto Gallo.
> 
> 

I think that LUTs fit particularly well the xilinx
distributed RAM. This feature is not available
on Altera devices (I've heard xiinx has a patent on it).

-- 

Tullio Grassi

======================================
Univ. of Maryland - Dept. of Physics
College Park, MD 20742 - US
Tel +1 301 405 5970
Fax +1 301 699 9195
======================================


Article: 52176
Subject: Re: xilinx tools: How to convert Schematic design to VHDL code
From: Chen Wei Tseng <chenwei.tseng@xilinx.com>
Date: Mon, 03 Feb 2003 15:08:22 -0700
Links: << >>  << T >>  << A >>
Bams,

With ISE, it always generate VHDL or Verilog file depending on which flow you
use. XST VHDL generate .VHF(equivalent of .vhd) while XST VERILOG generates .VF
file(equivalent of .v).

Regards, Wei

bams wrote:

> I want to know if we can convert a schematic design to a VHDL file inside a
> xilinx project.Do I need any external software to do that?
>
> --bams


Article: 52177
Subject: Targeting the VirtexII version of Picoblaze at a SpartanII....
From: "Nial Stewart" <nial@spamno.nialstewart.co.uk>
Date: Mon, 3 Feb 2003 22:09:05 -0000
Links: << >>  << T >>  << A >>
Most of you probably know that the Picoblaze is a free minimal
processor core that Xilinx provide, see....

http://www.xilinx.com/ipcenter/processor_central/picoblaze/index.htm

There are three different versions targeting the VirtexII,
Virtex/Virtex-E/SpartanII/SpartanII-E and the CoolrunnerII architectures.


These could be very useful but the SpartanII version has a
code limit of 256 addresses, whereas the VirtexII version has a code
space of 1024 addresses which could potentially make it be much more useful.


I've done a bit of work and have got the VirtexII version working on
a SpartanII. It uses 5 Blockrams, but in a large number of cases this
won't be a limiting factor. The most difficult bit was deriving the
initialisation attributes for the 5 blockrams from the single VirtexII
blockram, but I have a Perl routine to do this.

For details on the conversion, the perl routine and a (very) brief example
project
to run on a BurchED B5-X300 board see the downloads page of my web site
below.


Nial.
------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk



Article: 52178
(removed)


Article: 52179
Subject: Re: Clock Feedback for DDR-SDRAM (XApp200)
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Mon, 03 Feb 2003 17:42:45 -0500
Links: << >>  << T >>  << A >>
On Mon, 27 Jan 2003 18:02:26 -0500, Florian wrote:

> Hello,
> i'm designing a board with a VirtexII that takes masses of data from
> several inputs and stores it in 2 DDR-RAM channels. For the
> ram-controller i'm orientating on xapp200. It says to feed the ddr_clk
> and possibly ddr_clkb back into the fpga. My question is how to route
> this feedback on the pcb? I see several possibilities: - shortest way
> from pad to pad
> - from the series termination resitor - from the ram-socket - from the
> parallel termination resitor And how do i terminate this feedback? (DCI
> is not an option)
> 
> Any help welcome
> 
> Thank You in advance
> Florian
 
XAPP200 is dated, you want XAPP609. It's so new that it's not listed in
the normal place. To get it goto the support page and use the search
engine to search the app notes.

Article: 52180
Subject: Re: Group Multiple tables
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 03 Feb 2003 14:48:08 -0800
Links: << >>  << T >>  << A >>
Roberto Gallo wrote:
 >. . . However  as many as sixteen 256x8 bits
> tables should be used. These tables are equal in content, however they have
> independent indexing.
>     I was wondering about how to group them, so that I could use FPGAs
> memory intead of registers. Is it possible to use a multi-output memory? How
> to?



You could arbitrate the 16 processes to share one or more identical roms,
or or use one rom per process.



  -- Mike Treseler


Article: 52181
Subject: Re: Targeting the VirtexII version of Picoblaze at a SpartanII....
From: Theron Hicks <hicksthe@egr.msu.edu>
Date: Mon, 03 Feb 2003 18:39:09 -0500
Links: << >>  << T >>  << A >>
Thanks,
    It looks very interesting.  I notice that the page also lists a USB
interface module.  What can you tell me about this?  Is it USB or USB2?  I am
interested in a possible USB2 I/O for a project.

Thanks again,
Theron Hicks

Nial Stewart wrote:

> Most of you probably know that the Picoblaze is a free minimal
> processor core that Xilinx provide, see....
>
> http://www.xilinx.com/ipcenter/processor_central/picoblaze/index.htm
>
> There are three different versions targeting the VirtexII,
> Virtex/Virtex-E/SpartanII/SpartanII-E and the CoolrunnerII architectures.
>
> These could be very useful but the SpartanII version has a
> code limit of 256 addresses, whereas the VirtexII version has a code
> space of 1024 addresses which could potentially make it be much more useful.
>
> I've done a bit of work and have got the VirtexII version working on
> a SpartanII. It uses 5 Blockrams, but in a large number of cases this
> won't be a limiting factor. The most difficult bit was deriving the
> initialisation attributes for the 5 blockrams from the single VirtexII
> blockram, but I have a Perl routine to do this.
>
> For details on the conversion, the perl routine and a (very) brief example
> project
> to run on a BurchED B5-X300 board see the downloads page of my web site
> below.
>
> Nial.
> ------------------------------------------------
> Nial Stewart Developments Ltd
> FPGA and High Speed Digital Design
> www.nialstewartdevelopments.co.uk


Article: 52182
Subject: Routing in JBits
From: Florian-Wolfgang Stock <f.stock@tu-bs.de>
Date: Tue, 04 Feb 2003 01:12:24 +0100
Links: << >>  << T >>  << A >>
Hello,

I am working on a small project with jbits (implementing a
Knuth/Morris/Pratt-Search). I found it very good, but one thing is
annoying - the route (I use JRoute2). 
If I have something like this 
          __________
  log(n) |          |
  output | 1-of-2^n |
  lines  |  Encoder |------------
  -------|  Core    |------------ n input lines
  -------|          |------------
         |          |------------
         |          |
         |__________|

I write something like this:

  Bus input=newBus("InputBus", n);
  Bus output=newBus("OutputBus", log2(n));
  Encoder enc=new Encoder("Encoder", input, output);
  enc.implement();
  Bitstream.connect(input);
  Bitstream.connect(output);

and now at execution I got an Error, when Routing the input Bus. The
reason is that the Net at position 0 of the input-Bus has no sinks -
if you look at the function of Encoder you can imagine why, you dont
need it. It gets even more annoying if you got instead of the encoder
a logic function which connects one of the input nets with a output
net.  Then the Router routes input as normal, but when the router
tries to route the output-Bus it gots at the id-Net at recognizes that
the target pin is already used. He doesnt recognize that this net is
already routed. 
The idea to route beyond Ports is good, this way you can optimze the
routing good, for example in this case
           A    B
           |    |
           |    |
           |    |
           |_##_|
             ##

imagine A as the sink for the output-Bus from above, # the function
with the one of the id-nets and B the source of the input-Bus. If you
would route from B to the inputport of the Core, in the core from
inputport to outputport and then from outputport to A you got a
routing distance of 12 (chars), but in this special case you could
route this single signal direct from B to A (and use just 4 (chars)).

Its very annoying that the router doesnt mark nets as routed, and
ignores already routed nets.  From the design its bad to, because you
do the routing (at least) one hierachicle (is it spelled right?) level
above the level where you handle the interiors of the used core. 

And now my Question: Because its complicated always you route
something to look in the interiors of the connected cores, has someone
else experience with JBits and knows an easy solution (except from
catching and ignoring all (maybe true and harmful) exceptions)?

Thx in advance
Florian
-- 
int m,u,e=0;float l,_,I;main(){for(;1840-e;putchar((++e>907&&942>e?61-m:u)
["\t#*fg-pa.vwCh`lwp-e+#h`lwP##mbjqloE"]^3))for(u=_=l=0;79-(m=e%80)&&
I*l+_*_<6&&26-++u;_=2*l*_+e/80*.09-1,l=I)I=l*l-_*_-2+m/27.;}

Article: 52183
(removed)


Article: 52184
(removed)


Article: 52185
Subject: Re: Clock Feedback for DDR-SDRAM (XApp200)
From: b_foelsch@hotmail.com (Boris Foelsch)
Date: 3 Feb 2003 20:19:49 -0800
Links: << >>  << T >>  << A >>
"B. Joshua Rosen" <bjrosen@polybus.com> wrote in message news:<b1mr8t$14kjph$1@ID-78650.news.dfncis.de>...

>  
> XAPP200 is dated, you want XAPP609. It's so new that it's not listed in
> the normal place. To get it goto the support page and use the search
> engine to search the app notes.

http://support.xilinx.com/xapp/xapp609.pdf

Article: 52186
Subject: Re: Clock Feedback for DDR-SDRAM (XApp200)
From: b_foelsch@hotmail.com (Boris Foelsch)
Date: 3 Feb 2003 20:24:50 -0800
Links: << >>  << T >>  << A >>
"B. Joshua Rosen" <bjrosen@polybus.com> wrote in message news:<b1mr8t$14kjph$1@ID-78650.news.dfncis.de>...
> On Mon, 27 Jan 2003 18:02:26 -0500, Florian wrote:
> 
> > Hello,
> > i'm designing a board with a VirtexII that takes masses of data from
> > several inputs and stores it in 2 DDR-RAM channels. For the
> > ram-controller i'm orientating on xapp200. It says to feed the ddr_clk
> > and possibly ddr_clkb back into the fpga. My question is how to route
> > this feedback on the pcb? I see several possibilities: - shortest way
> > from pad to pad
> > - from the series termination resitor - from the ram-socket - from the
> > parallel termination resitor And how do i terminate this feedback? (DCI
> > is not an option)
> > 
> > Any help welcome
> > 
> > Thank You in advance
> > Florian
>  
> XAPP200 is dated, you want XAPP609. It's so new that it's not listed in
> the normal place. To get it goto the support page and use the search
> engine to search the app notes.

This is an interesting app note, but really has very little directly
to do with the question being put to the group.

Anyhow, thanks for letting us know it exists.

-Boris

Article: 52187
Subject: Re: PCI protocol - assigning an address to my device
From: weirdo@bbs.frc.utn.edu.ar (Mauricio Lange)
Date: 3 Feb 2003 20:34:55 -0800
Links: << >>  << T >>  << A >>
Austin, thanks for the reply!

 I will work on that!

Mauricio Lange


 > 
> > I did the following: preset my BAR0 register to 0x00000005 (the
> > BAR0(0) bit indicates the space, memory or i/o) and get, as result,
> > the following address assigned: 0x02000001, what could that possibly
> > mean?
> 
> You get a 4k space starting at 0x0200_0xxx.  BUT, why are you setting bit 0
> to 1 for?  You are asking for 4k of I/O space...and you probably really want
> memory space.  Why are you setting bit 2?  Setting bit 2 and 1 to 10b asks
> the system to locate you in 64 bit address space...
> 
> I'd suggest presetting bit 0 to 0 and bit 2 to 0 as well.  These should not
> be presets, but hard bits...that can't be written.  No need to implement
> them as a register, just use an enablable buffers and tie the inputs to
> ground for the lower 12 bits of the BAR.
> 
> Austin

Article: 52188
Subject: Difference between : CPLD , FPGA , ASICS
From: azim_premjii@yahoo.com (azim premji)
Date: 3 Feb 2003 21:25:37 -0800
Links: << >>  << T >>  << A >>
hi
plz let me know complete Difference between : CPLD , FPGA , ASICS

Article: 52189
Subject: What's the difference: WebPack 5.1 vs. Xilinx Student Edition 4.2i ?
From: "Bill Turnip" <BTurnip@acm.org>
Date: Tue, 04 Feb 2003 06:45:11 GMT
Links: << >>  << T >>  << A >>
Anyone care to comment on the differences between the two?  Is the Student
Edition worth the expense as compared to the free WebPACK?  If WebPACK is
free, why is the SE on the market?

Just curious,
BT



Article: 52190
Subject: Re: xilinx tools: How to convert Schematic design to VHDL code
From: bamini222@yahoo.com (bams)
Date: 3 Feb 2003 22:52:21 -0800
Links: << >>  << T >>  << A >>
Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<3E3EE856.8F0C8739@xilinx.com>...
> Bams,
> 
> With ISE, it always generate VHDL or Verilog file depending on which flow you
> use. XST VHDL generate .VHF(equivalent of .vhd) while XST VERILOG generates .VF
> file(equivalent of .v).
> 
> Regards, Wei

Hello Wei,
thanks for your input.I couldn't locate .vhf file. where do i find
that file inside my project.I didn't get what you mean by "which flow
i use".your help will be greatly appreciated.

regards,
Praveen
> 
> bams wrote:
> 
> > I want to know if we can convert a schematic design to a VHDL file inside a
> > xilinx project.Do I need any external software to do that?
> >
> > --bams

Article: 52191
Subject: Project fits in Leonardo, not in maxplus?!?
From: "David" <gretzteam@hotmail.com>
Date: Tue, 4 Feb 2003 02:51:16 -0500
Links: << >>  << T >>  << A >>
Hi,
I have a design that I synthetize in Leonardo and then compile/fit in
MaxplusII (I would use QuartusII but the web edition doesn't support the
EPF10K20RC240 which is on the University dev. board....I don't get that
one.)
Anyway, I don't understand why MaxplusII says it doesn't fit. Here is the
report from Leonardo (quite encouraring):

***********************************************
Device Utilization for EPF10K20RC240
***********************************************
Resource                Used    Avail   Utilization
-----------------------------------------------
IOs                     35      189      18.52%
LCs                     347     1152     30.12%
DFFs                    97      1344      7.22%
Memory Bits             0       12288     0.00%
CARRYs                  233     1152     20.23%
CASCADEs                7       1152      0.61%
-----------------------------------------------

MaxplusII says that it uses too many logic cells (1978/1152). This number is
way off what leonardo expected. I'm using the .edf file produced by leonardo
and compile it in MaxPlus. I guess this is the usual way to proceed. Could
it be because the design uses LPM components?

Thanks
David




Article: 52192
Subject: Re: Difference between : CPLD , FPGA , ASICS
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Tue, 4 Feb 2003 08:10:31 +0000 (UTC)
Links: << >>  << T >>  << A >>
azim premji <azim_premjii@yahoo.com> wrote:
: hi
: plz let me know complete Difference between : CPLD , FPGA , ASICS

What did you do to learn about the differences?

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 52193
Subject: Re: Group Multiple tables
From: amit_ashara@hotmail.com (Amit)
Date: 4 Feb 2003 00:22:15 -0800
Links: << >>  << T >>  << A >>
Hello

 The best way is to create a vhd file that has a process which uses
one ROM. Instantiate this 16 times by using "generate" statement
during port map and you get the parallel lookup.
 The advantage will be modular design that is easy to work on.

Regards
Amit

Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3E3EF1A8.30908@flukenetworks.com>...
> Roberto Gallo wrote:
>  >. . . However  as many as sixteen 256x8 bits
> > tables should be used. These tables are equal in content, however they have
> > independent indexing.
> >     I was wondering about how to group them, so that I could use FPGAs
> > memory intead of registers. Is it possible to use a multi-output memory? How
> > to?
> 
> 
> 
> You could arbitrate the 16 processes to share one or more identical roms,
> or or use one rom per process.
> 
> 
> 
>   -- Mike Treseler

Article: 52194
Subject: Re: What's the difference: WebPack 5.1 vs. Xilinx Student Edition 4.2i ?
From: "Alex Gibson" <alxx@ihug.com.au>
Date: Tue, 4 Feb 2003 20:48:31 +1100
Links: << >>  << T >>  << A >>

"Bill Turnip" <BTurnip@acm.org> wrote in message
news:XjJ%9.158245$VU6.116350@rwcrnsc52.ops.asp.att.net...
> Anyone care to comment on the differences between the two?  Is the Student
> Edition worth the expense as compared to the free WebPACK?  If WebPACK is
> free, why is the SE on the market?
>
> Just curious,
> BT

At least 2 versions 2.1 and 4.2.
2.1 has a built in simulator.
2.1 is dated 1995.probably before they released the web pack.

4.2 was identical (almost) with version 4.2 of the web pack
except it was from Prentice Hall and for educational purposes only.


don't buy the student edition it comes with various textbooks.
2.1 came Logic and COmputer Design Fundamentals by Mano and Kime 2nd edition
4.2 with Digital Design 3rd edition by Wakerly

For starters either download the webpack or request a cd.
(Even if you request a cd you will need to download the patches as well
usually around 50 - 100Mb)

For the student edition find  library that has the books
or look on ebay or student bookshop.






Article: 52195
Subject: First ISE design...
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Tue, 4 Feb 2003 12:26:56 +0200
Links: << >>  << T >>  << A >>
Do I have to place all pin connections in the top level schematic design?
ISE complains when I try to place them into a lower down schematic symbol. I
assume I am assigning pins correctly (add I/O marker to end of net, then add
LOC attribute to net)... of course, adding an I/O markers on the nets will
automatically create input pins on the symbol I am making, so must this be
traced through to the top level?

Thanks

adrian



Article: 52196
Subject: Re: Difference between : CPLD , FPGA , ASICS
From: "S. Ramirez" <sramirez@cfl.rr.com>
Date: Tue, 04 Feb 2003 11:42:22 GMT
Links: << >>  << T >>  << A >>

"azim premji" <azim_premjii@yahoo.com> wrote in message
news:9afc0e91.0302032125.ba021f1@posting.google.com...
> hi
> plz let me know complete Difference between : CPLD , FPGA , ASICS

CPLD - Complex Programmable Logic Device
FPGA - Field Programmable Gate Array
ASICS-Application Specific Integrated Circuits



Article: 52197
Subject: Re: Spice - Powersupply
From: "svhb" <svhb@pandora.be>
Date: Tue, 4 Feb 2003 12:53:44 +0100
Links: << >>  << T >>  << A >>
use a voltage source and put a resistor in series. If you can't do this with
LSSpice, use decent software

"Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote
in message news:z9G%9.68452$F63.1395409@news.xtra.co.nz...
> Excuse the totally dumb question.
>
> I am using the Linear tech LTSpice program, and cant figure how to model a
> power supply.
>
> There is a current source and a voltage source, but no (as far as I can
> find) no battery type component (eg voltage drops as current increases
past
> what it can supply)
>
> Thanks for any tips
>
> Ralph
>
>



Article: 52198
Subject: Re: Difference between : CPLD , FPGA , ASICS
From: "Jonathan Bromley" <jonathan@oxfordbromley.u-net.com>
Date: Tue, 4 Feb 2003 11:55:10 -0000
Links: << >>  << T >>  << A >>
"S. Ramirez" <sramirez@cfl.rr.com> wrote

> > plz let me know complete Difference between : CPLD , FPGA , ASICS
>
> CPLD - Complex Programmable Logic Device
> FPGA - Field Programmable Gate Array
> ASICS-Application Specific Integrated Circuits

While Simon's gloss is clearly correct, it's perhaps not very
informative to a newby.  A sideways view might be more helpful.

How about...
CPLD:  Middling-to-big programmable doohickey marketed by people
       who still think 22V10s are a pretty neat idea.
FPGA:  Big-to-huge programmable doohickey marketed by people who
       think that it's a pretty neat idea to spend 75 million
       transistors in order to create a million gates of logic.
ASIC:  Huge-to-gigantic non-programmable doohickey designed by
       machos who think that modifying a gate level netlist
       with a 10,000-line Perl script in order to fix one missing
       inverter is a pretty neat way of doing an ECO.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



Article: 52199
Subject: Can't start server quartus_cmp in quartus II 1.0
From: k0sadik@yahoo.com (sadik)
Date: 4 Feb 2003 04:24:09 -0800
Links: << >>  << T >>  << A >>
Hi,
  When i run the tcl script quartus II 1.0 gives the error called
"Can't start server quartus_cmp Beginning attempt 1 of 3 attempts to start server"
But the same project got completed in when fired through GUI!
What could be the problem???
thanks and regds
Sadik



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