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this link should be a solution. Its an encrypted core. It can be parameterized. Its free, if you give your coordinates to ALTERA. http://www.altera.com/products/ip/altera/m-ham-sqroot.html regards Thomas "Sujatha" <sujatha.sriram@philips.com> schrieb im Newsbeitrag news:ee7c2ef.-1@WebX.sUN8CHnE... Can anyone please suggest how can a square root function be implemented in a Altera Apex20K device. Is there any free megafunction for this purpose available.Article: 53176
Steven John Buckley wrote: > > Not sure if this is the right place but here goes! > I have the task of replacing a bunch of ALTERA > EP310 PLDs for a new design but only have the > JED files for them. I need the equation for them. > I have scanned the NET but can only find > JED2EQN.EXE which does not have the EP310 in the library. > I don't care about the format of the equations EQN,CUPL etc. > Does anyone know of a simple utility around that will take > the EP310 JED files and output something that tells me what > the damn things do. > Any help will be gratefullt received. If you have an average/good device programmer, you can create test vectors and save them from the programmer. With the circuit in one hand as a guide, write input combinations for each output, and verify they pass. This file can be used to create sources, and it would be a good audit-step to try and recreate the 310 JEDs. ( checks you have indeed found all the logic terms :) It's clear from the JEDs how many prod terms per MC are used, and they may, or may not 'line up' on an EQN-> exact Prod term ( this depends on the SW, and original eqn form ) - however a text editor can check this, and the fuse--blow counts should be the same. Also, take a look at www.ictpld.com, IIRC they had some migration tools, and the EP310 may be among the devices. -- jgArticle: 53177
XPS generates an XMP file. Edit the xmp file, and load the xmp back into xps. I'm not sure if the gui mode will overwrite what you just edited, but launch xps from comman-line "xps -nw" % load xmp system.xmp % save make % help This will give you run options. Andreas Kugel wrote: > > The newer SPartan2e devices XC2S400e and XS2S600e are unknown to the > EDK3.1 (SP3). Installation of the XC2S400/600 device files for ISE5.1 > doesn't help. Any hints ? > > Andreas -- / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USAArticle: 53178
Ken Chapman <chapman@xilinx.com> wrote in message news:<3E64B9D9.5B894EC6@xilinx.com>... > Dear Basuki, > > The safe answer is just to keep the most significant bits. However, you may well be wasting dynamic range by doing this. > > The best is to calculate the output saturation level. This is the maximum level the output can reach based on the actual coefficients you have used, many of which will relatively small numbers. In this way you can often discard one or more of the MSBs which are not really used and maintain higher precision by keeping some LSBs. > > Needless to say this is covered on the Xilinx DSP Techniques Course which I authored :-) > > Yours sincerely, > > Ken Chapman Dear Basuki, I use: clip_and_amplify : process( s ) begin case s( s'high downto s'high - 3 ) is when B"0000" | B"1111" => s_out <= s( s'high - 2 downto s'high - 2 - 15 ) ; when others => s_out <= ( s( s'high ), others => not s( s'high ) ) ; end case ; end process ; to clip and amplify a signal s of arbitrary width to an output s_out of 16 bits. Both signals are signed signals. Henk van Kampen www.mediatronix.comArticle: 53179
On Tue, 04 Mar 2003 06:22:29 -0500, Tomas wrote: > Hi all, > > I am considering the future hardware platforms for our designs. As our > groups have a wide experience with unix environments (we have been using > Solaris for a while, now), we would like to continue in this world. > > Basically all the EDA tools we need run for either Solaris, HP and some > of them now, Linux. I am not going to list all the pro's and con's of > these platforms, we have already heard enough about it. > > What I am mostly curious about is the feasibility of Mac based FPGA > design. Mac Os X is a nice and SUPPORTED Unix OS, and the Xservers from > Apple are not too expensive compared to equivalent Intel boxes... And > with the rumored advent of the 970 chips from IBM they might become even > more interesting. > > Of course none of EDA tools we use (Modelsim, Leonardo, Synplify, Xilinx > Alliance...) have native versions for Mac OS X. > > What do you all think about this? Should we press the EDA vendors to > come up with yet-another-supported-platform? > > Regards, > Tomas For any serious work your best choice is Linux. The Mac has never been supported by EDA vendors and it's unlikely that they will start now. Most of the major EDA tools are available on Linux. Altera's tools are available as native Linux tools, Xilinx's tools still have to be run under wine but the important ones work fine and Xilinx is planning to have native Linux support in their next major release. The only real use for Mac is as an X server and for documentation.Article: 53180
The RAMB models use the Verilog "parameter" to initialize the INIT strings. Since defparams are based on the scope hierarchy, you would need to know the location of the Rambs in your design. This would work for synthesis/simulation, as XST does read defparams. > $readmem would work for simulation, but not synthesis. The only > synthesizable way to initialize a blockRAM in a Xilinx that is is to use > comments or a particular syntax that the synthesizer passes on to the > place&route tool. The FPGA synthesizers aren't yet smart enough to use > $readmem; they just ignore it completely. -- / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USAArticle: 53181
I am attempting to use the Matlab signal processing toolbox to generate filter coefficients to use as inputs to Xilinx core generator filter tool. As far as I can see, the numerical coefficients from Matlab are always normalized -1 < c < 1. There does not seem to be any sort of a switch on this. Xilinx appears to accept only whole numbers, decimal or hex. Anyone know of a way to make these two talk to each other that does not involve me writing a conversion routine?Article: 53182
Tom, I have used the EDIF flow a long time without any trouble. We have for example a Virtex-II containing two seperate designs, made by two different designers. They share some clock logic so we have a top EDIF file with two black holes, these holes are filled with two EDIF files containing the two designs. These designs again contains several black holes for CoreGen RAM EDIF files. Just drop the EDIF files in the same directory as the top EDIF and, if they are named correctly, they will be absorbed by the Xilinx tool. In this way each component can be synthesized by each designer. Hakon Lislebo Ericsson AS tom1@launchbird.com (Tom Hawkins) wrote in message news:<833030c0.0303050733.235bcc41@posting.google.com>... > I'd just like to hear some opinions and experiences with using > the Xilinx EDIF flow for blockbox instantiation; for instance, > dropping in IP produced by Core Generator. > > Is this flow pretty smooth? What are the common hang-ups? > How well does it work with third-party synthesis tools? > > The reason I'm asking is that we are considering direct FPGA > synthesis of the Confluence design language--Virtex-II would > be the first supported platform. But instead of full chip > synthesis, we plan to generate component EDIF netlists similar > to that produced by Core Generator. This would allow platform > optimized Confluence IP to integrated with a standard HDL flow. > > I'd appreciate any opinions. > > Regards, > TomArticle: 53183
When using Synplify, you have to specify the initial contents twice: using defparams (for the simulator) and using comments (for Synplify). Synplify won't read the defparams for RAM initialization. I think XST works exactly the same way, according to this solution on the Xilinx website: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= 1&getPagePath=10695 -Kevin "Paulo Dutra" <paulo@xilinx.com> wrote in message news:3E665040.225B2306@xilinx.com... > The RAMB models use the Verilog "parameter" to initialize the INIT strings. > Since defparams are based on the scope hierarchy, you would need to know > the location of the Rambs in your design. > > This would work for synthesis/simulation, as XST does read defparams. > > > $readmem would work for simulation, but not synthesis. The only > > synthesizable way to initialize a blockRAM in a Xilinx that is is to use > > comments or a particular syntax that the synthesizer passes on to the > > place&route tool. The FPGA synthesizers aren't yet smart enough to use > > $readmem; they just ignore it completely. > > -- > / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) > \ \ ` Xilinx hotline@xilinx.com > / / 2100 Logic Drive http://www.xilinx.com > \_\/.\ San Jose, California 95124-3450 USAArticle: 53184
> Hello > we are an ASIC/FPGA company currently understaffed but with a very > limited budget; so I wonder under what circumstances and what type of > projects(non crucial?) we could consider outsourcing to some(which?) > developing country team? > Thanks > MA As others have said, why specifically a developing country team? I'm sure you'll find that small American (or European ;-) ) outsourcing companies can be cost effective as they're not paying overheads associated with bigger concerns. I would look at what you're doing. If there are parts of your design which are already well documented and which are well defined 'chunks', these would be ideal candidates for development by an external company. Nial Stewart. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 53185
On 4 Mar 2003 18:45:28 -0800, the renowned anglomont@yahoo.com (TI) wrote: >Hello >we are an ASIC/FPGA company currently understaffed but with a very >limited budget; so I wonder under what circumstances and what type of >projects(non crucial?) we could consider outsourcing to some(which?) >developing country team? I know some clever Russians who are eager to do analog IC design. For a mere 25% I'll match you up and lower their expectations. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.comArticle: 53186
Sorry, I have confirmed this with our in-house expert. XST uses the models located in: %XILINX%\verilog\src\iSE\unisim_comp.v The RAMBs don't have parameters in those models. Kevin, you're correct. Kevin Neilson wrote: > > When using Synplify, you have to specify the initial contents twice: using > defparams (for the simulator) and using comments (for Synplify). Synplify > won't read the defparams for RAM initialization. I think XST works exactly > the same way, according to this solution on the Xilinx website: > > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= > 1&getPagePath=10695 > > -Kevin > > "Paulo Dutra" <paulo@xilinx.com> wrote in message > news:3E665040.225B2306@xilinx.com... > > The RAMB models use the Verilog "parameter" to initialize the INIT > strings. > > Since defparams are based on the scope hierarchy, you would need to know > > the location of the Rambs in your design. > > > > This would work for synthesis/simulation, as XST does read defparams. > > > > > $readmem would work for simulation, but not synthesis. The only > > > synthesizable way to initialize a blockRAM in a Xilinx that is is to use > > > comments or a particular syntax that the synthesizer passes on to the > > > place&route tool. The FPGA synthesizers aren't yet smart enough to use > > > $readmem; they just ignore it completely. > > > > -- > > / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) > > \ \ ` Xilinx hotline@xilinx.com > > / / 2100 Logic Drive http://www.xilinx.com > > \_\/.\ San Jose, California 95124-3450 USA -- / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USAArticle: 53187
Tom, The approach we have tried and had success with is to create a project using the synthesis tool of your choice, and copying the EDIF netlist into the project directory manually. Their is no need to add the netlist to the project, as ngdbuild will pick it up automatically. Hope this helps, regards, Chris tom1@launchbird.com (Tom Hawkins) wrote in message news:<833030c0.0303050733.235bcc41@posting.google.com>... > I'd just like to hear some opinions and experiences with using > the Xilinx EDIF flow for blockbox instantiation; for instance, > dropping in IP produced by Core Generator. > > Is this flow pretty smooth? What are the common hang-ups? > How well does it work with third-party synthesis tools? > > The reason I'm asking is that we are considering direct FPGA > synthesis of the Confluence design language--Virtex-II would > be the first supported platform. But instead of full chip > synthesis, we plan to generate component EDIF netlists similar > to that produced by Core Generator. This would allow platform > optimized Confluence IP to integrated with a standard HDL flow. > > I'd appreciate any opinions. > > Regards, > TomArticle: 53188
Does anyone have a working example of a PowerPC application that uses the Xilinx V2PDK tools with the Memec Virtex-II Pro Development board, and that can complete the FPGA synthesis using XST (not Synplicity).Article: 53189
"Kevin Neilson" <kevin_neilson@removethistextattbi.com> wrote in message news:<jig9a.318855$2H6.6339@sccrnsc04>... > > $readmem would work for simulation, but not synthesis. The only > synthesizable way to initialize a blockRAM in a Xilinx that is is to use > comments or a particular syntax that the synthesizer passes on to the > place&route tool. The FPGA synthesizers aren't yet smart enough to use > $readmem; they just ignore it completely. I was afraid of this. The best I can come up with is some kludges to generate different module source files automatically. Surely Xilinx has had users that needed to do this before, and has provided some mechanism for it.Article: 53190
Hi! I am a new partial reconfiguration user, and I want to develop a small design that involve partial reconfiguration using Xilinx Modular Design flow. I have a fixed module and two reconfiguration modules. The only communication between modules is a simple clock signal. XAPP290 document described that the only the clock signal can be shared among modules without bus macros (Multi-Columns Partial Reconfiguration, Independent Designs section about XAPP290 page 2). The fixed module is a small counter ticks in a time period, showed in a display. A reconfigurable module is a counter that ticks in a different time period than fixed module. A second reconfigurable module only blink some second display leds. Theses reconfigurables modules are showed in a second display next to the fixed module display. I create two top sources (each one of them contain one instance of reconfigurable modules). and three kind of counters: two reconfigurables e one fixed. When I follow the Modular design flow described in XAPP290 document, happens some errors. I synthetized theses files with Leonardo Spectrum Software and it generated EDIF files. So, I use them as entry in a modular design flow. Following, I executed ngdbuild command with |-modular initial| parameters. It happens a lot of errors such as: Line command executed: ngdbuild -p xc2v1000fg456-4 -modular initial top.edf ERROR:XdmHelpers:819 - Modular design: initial mode must have at least one inactive module. ERROR:NgdBuild:558 - Modular Design cannot be annotated. Checking timing specifications ... Checking expanded design ... ERROR:NgdBuild:519 - The EQN value of "((!I3)+(!I0*!I1*!I2))", on the LUT4 symbol "ix194", is not a valid equation. ... Could someone help me? Any help will be accepted with gratefulness! Eduardo Wenzel Brião Catholic University of Rio Grande do Sul State - PUCRS Porto Alegre city BrazilArticle: 53191
"Jonathan Bromley" <jonathan@oxfordbromley.u-net.com> wrote in message news:b45329$pcs$1$830fa78d@news.demon.co.uk... > "Sujatha" <sujatha.sriram@philips.com> wrote > > > Can anyone please suggest how can a square root function > > be implemented in a Altera Apex20K device. Is there any > > free megafunction for this purpose > > Aw, c'mon, give us a clue! Floating-point, fixed-point, integer? > How many bits? How fast do you need it to be? How much FPGA > real-estate can you afford to spend on this function? What > do you intend to do with the extra fraction bits you'll get? Wow, just the reply I was going to make, so I guess I don't need to do it. My favorite implementation for fixed-point software algorithms is Knuth's "Metafont: The Program". I don't know how well they would do in an FPGA, though. How many bits, and fixed or floating point could make a huge difference here. -- glenArticle: 53192
As a consulting engineer I see a lot of money wasted on buying in outside expertise - some of that money paid to me ! I can't count how many times I get asked to start a job then half way through the customer dumps the job. The customer gets zero return on the money spent and no-one inside the company benefits from the knowledge gained. My theory is that you should "own" your workers : they work in your time on your equipment under your roof. Look after your workers so they stay and build up a bank of knowledge - especially in your company's core area. Outsourcing is best when specialist expertise is needed. I have seen companies which are short of cash scrape together enough money to pay some outsider for a specific job - and get very little in return. Much better to search for a very productive, adaptable, enthusiastic, bright person who will enrich the company in the long term. Put a lot of effort into recruiting. Roger "TI" <anglomont@yahoo.com> wrote in message news:18a34598.0303041845.33b150a0@posting.google.com... > Hello > we are an ASIC/FPGA company currently understaffed but with a very > limited budget; so I wonder under what circumstances and what type of > projects(non crucial?) we could consider outsourcing to some(which?) > developing country team? > Thanks > MAArticle: 53193
Eduardo, I'll take a guess at this. With initial setting, make sure Leonardo didn't compile the lower modules into the top level module for you. Also make sure the lower modules are treated as black boxs in the top level module. Make sure only your top.edn is in the directory. You may want to contact Xilinx support as well. Regards, Wei "Eduardo Wenzel Brião" wrote: > Hi! > I am a new partial reconfiguration user, and > I want to develop a small design that involve partial reconfiguration > using > Xilinx Modular Design flow. I have a fixed module and two > reconfiguration modules. > The only communication between modules is > a simple clock signal. XAPP290 document described that the only the > clock signal can be > shared among modules without bus macros (Multi-Columns Partial > Reconfiguration, > Independent Designs section about XAPP290 page 2). > The fixed module is a small counter ticks in a time period, showed in > a display. > A reconfigurable module is a counter that ticks in a different time > period than fixed module. > A second reconfigurable module only blink some second display leds. > Theses reconfigurables modules are showed in a second display next to > the fixed module display. > I create two top sources (each one of them contain one instance of > reconfigurable modules). > and three kind of counters: two reconfigurables e one fixed. When I > follow the Modular design > flow described in XAPP290 document, happens some errors. > I synthetized theses files with Leonardo Spectrum Software and it > generated EDIF files. > So, I use them as entry in a modular design flow. Following, I > executed ngdbuild command > with |-modular initial| parameters. It happens a lot of errors such > as: > > Line command executed: ngdbuild -p xc2v1000fg456-4 -modular initial > top.edf > > ERROR:XdmHelpers:819 - Modular design: initial mode must have at least > one inactive module. > > ERROR:NgdBuild:558 - Modular Design cannot be annotated. > Checking timing specifications ... > Checking expanded design ... > ERROR:NgdBuild:519 - The EQN value of "((!I3)+(!I0*!I1*!I2))", on the > LUT4 symbol "ix194", > is not a valid equation. > > ... > > Could someone help me? Any help will be accepted with gratefulness! > > Eduardo Wenzel Brião > Catholic University of Rio Grande do Sul State - PUCRS > Porto Alegre city > BrazilArticle: 53194
Hi,I am now doing a project on testing Handel-C program. Any experienced user on handel-C can tell me any common mistakes programmer always made when coding ,especially for the new user? I try to find a methodology to detect the bugs.Article: 53195
I agree with all you've said but the sad fact is that you are, by your own words, "a consulting engineer" and American firms have long ago been sold on the notion that "a managerial consultant" is the expert on the subject under discussion. They'll suggest you pay someone outside who has special knowledge but can't see how paying somebody inside to gain, apply, and retain the same special knowledge works. I assume this must mean that the only thing that can be assigned a dollar value is the result of applying special knowledge, not the cost of gaining or the value of retaining the same. Mike Milner MIT BSEE, UofI PhD CS 25 years at Bell Labs downsourced 2001 Roger Lascelles wrote: > > As a consulting engineer I see a lot of money wasted on buying in outside > expertise - some of that money paid to me ! > > I can't count how many times I get asked to start a job then half way > through the customer dumps the job. The customer gets zero return on the > money spent and no-one inside the company benefits from the knowledge > gained. > > My theory is that you should "own" your workers : they work in your time on > your equipment under your roof. Look after your workers so they stay and > build up a bank of knowledge - especially in your company's core area. > > Outsourcing is best when specialist expertise is needed. > > I have seen companies which are short of cash scrape together enough money > to pay some outsider for a specific job - and get very little in return. > Much better to search for a very productive, adaptable, enthusiastic, bright > person who will enrich the company in the long term. Put a lot of effort > into recruiting. > > Roger > > "TI" <anglomont@yahoo.com> wrote in message > news:18a34598.0303041845.33b150a0@posting.google.com... > > Hello > > we are an ASIC/FPGA company currently understaffed but with a very > > limited budget; so I wonder under what circumstances and what type of > > projects(non crucial?) we could consider outsourcing to some(which?) > > developing country team? > > Thanks > > MAArticle: 53196
J. Michael Milner" <jmmilner@wideopenwest.com> wrote in message news:3E66BD67.5B82AAC9@wideopenwest.com... > I agree with all you've said but the sad fact is that you are, by your own > words, "a consulting engineer" and American firms have long ago been sold on > the notion that "a managerial consultant" is the expert on the subject under > discussion. They'll suggest you pay someone outside who has special knowledge > but can't see how paying somebody inside to gain, apply, and retain the same > special knowledge works. I assume this must mean that the only thing that can be > assigned a dollar value is the result of applying special knowledge, not the > cost of gaining or the value of retaining the same. I've often wondered how well a startup company would do, if it were to begin with several dozen to several hundred experienced, skilled engineers (formerly laid off on the advice of fast-talking managing consultants). All of them, of course, committed to the long-term survival and knowledge pool of the company, while fostering new talent and encouraging new research. They wouldn't last a year, of course. Still, an interesting idea.Article: 53197
"Jim Wu" <jimwu88NOOOSPAM@yahoo.com> writes: > "Brendan Lynskey" <brendan@comodogroup.com> wrote in message > news:LJk9a.10170$Vx2.774245@wards... > > Generally an RTL model, right? No timing info? > > Not necessarily an RTL model. It can be written in HDL, or C, or any other > languages, as long as it correctly describes the behavior of the bus and is > able to interact with your DUT. Usually they will contain timing checks, protocol checkers as well as a library to generate bus cycles at a higher level. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 53198
We intend to use an XC2VP4 or XC2VP7 for a system with 4 Rocket-I/O transceivers (2.5GBit), Power-PC and external DDR-memory. External memory and OBP can run at the same frequency (100MHz or 125MHz). Unfortunately the number of available DCMs has been drastically reduced from Virtex-2 to Virtex-2Pro. According to the datasheet a lot of DCMs would be required to build such a system. Are there examples or recommendation how DCMs can be re-used in order to minimise the required resources ? Thanks, AndreasArticle: 53199
I add this message for the one that has difficulty to read the attachments
# Reading C:/Modeltech_ae/tcl/vsim/pref.tcl
# Reading C:/qdesigns/Lancelot_nios/reference_design/nios_sim/modelsim.tcl
# c:/altera/excalibur/sopc_builder
# Sopc_Builder Directory: c:/altera/excalibur/sopc_builder
# ** Warning: (vlib-34) Library already exists at "work".
# @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
# @@
# @@ setup_sim.do
# @@
# @@ Defined aliases:
# @@
# @@ s -- Load all design (HDL) files.
# @@ re-vcom and re-vsim the design.
# @@
# @@ c -- Re-compile memory contents.
# @@ Builds C- and assembly-language programs
# @@ (and associated simulation data-files)
# @@ for refreshing memory contents.
# @@ Does NOT re-generate hardware (HDL) files
# @@
# @@ w -- Sets-up waveforms for this design
# @@ Each SOPC-Builder component may have
# @@ signals 'marked' for display during
# @@ simulation. This command opens a wave-
# @@ window containing all such signals.
# @@
# @@ h -- print this message
# @@
# @@ ***Special VHDL settings***
# @@ StdArithNoWarnings=1 in s command
# @@
# OpenFile "nios_sim.mpf"
# Loading project nios_sim
s
# Model Technology ModelSim ALTERA vcom 5.6a Compiler 2002.04 Apr 29 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling package altera_vhdl_support_lib
# -- Compiling package body altera_vhdl_support_lib
# -- Loading package altera_vhdl_support_lib
# Model Technology ModelSim ALTERA vcom 5.6a Compiler 2002.04 Apr 29 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package altera_vhdl_support_lib
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity nios_fast_output_register
# -- Compiling architecture europa of nios_fast_output_register
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/nios_fast_output_register.vhd(53)
: No default binding for component: "dffe". (No entity named "dffe" was
found)
# -- Compiling entity dma_fifo_module_fifo_ram_module
# -- Compiling architecture europa of dma_fifo_module_fifo_ram_module
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/dma_fifo_module_fifo_ram_module.v
hd(82): No default binding for component: "lpm_ram_dp". (No entity named
"lpm_ram_dp" was found)
# -- Compiling entity cpu_hidden_lcell_46fc
# -- Compiling architecture europa of cpu_hidden_lcell_46fc
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/cpu_hidden_lcell_46FC.vhd(82): No
default binding for component: "apex20k_lcell". (No entity named
"apex20k_lcell" was found)
# -- Compiling entity cpu_hidden_lcell_66fc
# -- Compiling architecture europa of cpu_hidden_lcell_66fc
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/cpu_hidden_lcell_66FC.vhd(85): No
default binding for component: "apex20k_lcell". (No entity named
"apex20k_lcell" was found)
# -- Compiling entity cpu_hidden_lcell_12f0
# -- Compiling architecture europa of cpu_hidden_lcell_12f0
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/cpu_hidden_lcell_12F0.vhd(73): No
default binding for component: "apex20k_lcell". (No entity named
"apex20k_lcell" was found)
# -- Compiling entity cpu_hidden_lcell_4def
# -- Compiling architecture europa of cpu_hidden_lcell_4def
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/cpu_hidden_lcell_4DEF.vhd(88): No
default binding for component: "apex20k_lcell". (No entity named
"apex20k_lcell" was found)
# -- Compiling entity cpu_hidden_lcell_4cef
# -- Compiling architecture europa of cpu_hidden_lcell_4cef
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/cpu_hidden_lcell_4CEF.vhd(84): No
default binding for component: "apex20k_lcell". (No entity named
"apex20k_lcell" was found)
# -- Compiling entity cpu_hidden_lcell_64fc
# -- Compiling architecture europa of cpu_hidden_lcell_64fc
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/cpu_hidden_lcell_64FC.vhd(81): No
default binding for component: "apex20k_lcell". (No entity named
"apex20k_lcell" was found)
# -- Compiling entity cpu_hidden_lcell_30f0
# -- Compiling architecture europa of cpu_hidden_lcell_30f0
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/cpu_hidden_lcell_30F0.vhd(72): No
default binding for component: "apex20k_lcell". (No entity named
"apex20k_lcell" was found)
# -- Compiling entity cpu_hidden_lcell_10f0
# -- Compiling architecture europa of cpu_hidden_lcell_10f0
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/cpu_hidden_lcell_10F0.vhd(69): No
default binding for component: "apex20k_lcell". (No entity named
"apex20k_lcell" was found)
# -- Compiling entity cpu_register_bank_a_module
# -- Compiling architecture europa of cpu_register_bank_a_module
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/cpu_register_bank_a_module.vhd(78
): No default binding for component: "lpm_ram_dp". (No entity named
"lpm_ram_dp" was found)
# -- Compiling entity cpu_register_bank_b_module
# -- Compiling architecture europa of cpu_register_bank_b_module
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/cpu_register_bank_b_module.vhd(78
): No default binding for component: "lpm_ram_dp". (No entity named
"lpm_ram_dp" was found)
# -- Loading package textio
# -- Compiling entity cpu_instruction_decoder_rom_module
# -- Compiling architecture europa of cpu_instruction_decoder_rom_module
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/cpu_instruction_decoder_rom_modul
e.vhd(81): No default binding for component: "lpm_ram_dp". (No entity named
"lpm_ram_dp" was found)
# -- Compiling entity uart_rx_stimulus_source_character_source_rom_module
# -- Compiling architecture europa of
uart_rx_stimulus_source_character_source_rom_module
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/uart_rx_stimulus_source_character
_source_rom_module.vhd(59): No default binding for component: "lpm_rom". (No
entity named "lpm_rom" was found)
# -- Compiling entity boot_rom_lane0_module
# -- Compiling architecture europa of boot_rom_lane0_module
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/boot_rom_lane0_module.vhd(64): No
default binding for component: "lpm_rom". (No entity named "lpm_rom" was
found)
# -- Compiling entity dma_fifo_module
# -- Compiling architecture europa of dma_fifo_module
# -- Loading entity dma_fifo_module_fifo_ram_module
# -- Compiling entity dma_mem_read
# -- Compiling architecture europa of dma_mem_read
# -- Compiling entity dma_mem_write
# -- Compiling architecture europa of dma_mem_write
# -- Compiling entity dma
# -- Compiling architecture europa of dma
# -- Loading entity dma_fifo_module
# -- Loading entity dma_mem_read
# -- Loading entity dma_mem_write
# -- Compiling entity lancelot_pwm
# -- Compiling architecture behavior of lancelot_pwm
# -- Compiling entity pwm_right
# -- Compiling architecture europa of pwm_right
# -- Loading entity lancelot_pwm
# WARNING[1]: C:/qdesigns/Lancelot_nios/reference_design/pwm_right.vhd(88):
Incompatible modes for port nios_irq
# WARNING[1]: C:/qdesigns/Lancelot_nios/reference_design/pwm_right.vhd(88):
A use of this default binding for this component instantiation will result
in an elaboration error.
# WARNING[1]: C:/qdesigns/Lancelot_nios/reference_design/pwm_right.vhd(88):
Incompatible modes for port pwm_out
# WARNING[1]: C:/qdesigns/Lancelot_nios/reference_design/pwm_right.vhd(88):
A use of this default binding for this component instantiation will result
in an elaboration error.
# -- Compiling entity pwm_left
# -- Compiling architecture europa of pwm_left
# WARNING[1]: C:/qdesigns/Lancelot_nios/reference_design/pwm_left.vhd(88):
Incompatible modes for port nios_irq
# WARNING[1]: C:/qdesigns/Lancelot_nios/reference_design/pwm_left.vhd(88): A
use of this default binding for this component instantiation will result in
an elaboration error.
# WARNING[1]: C:/qdesigns/Lancelot_nios/reference_design/pwm_left.vhd(88):
Incompatible modes for port pwm_out
# WARNING[1]: C:/qdesigns/Lancelot_nios/reference_design/pwm_left.vhd(88): A
use of this default binding for this component instantiation will result in
an elaboration error.
# -- Compiling entity sdram_fsm
# -- Compiling architecture europa of sdram_fsm
# -- Compiling entity sdram
# -- Compiling architecture europa of sdram
# -- Loading entity sdram_fsm
# -- Compiling entity cpu_opcode_display_unit
# -- Compiling architecture europa of cpu_opcode_display_unit
# -- Compiling entity cpu_interrupt_control
# -- Compiling architecture europa of cpu_interrupt_control
# -- Compiling entity cpu_address_request
# -- Compiling architecture europa of cpu_address_request
# -- Compiling entity cpu_target_address
# -- Compiling architecture europa of cpu_target_address
# -- Loading entity cpu_hidden_lcell_46fc
# -- Compiling entity cpu_instruction_fetch
# -- Compiling architecture europa of cpu_instruction_fetch
# -- Loading entity cpu_address_request
# -- Loading entity cpu_target_address
# -- Compiling entity cpu_cpu_instruction_fifo_fifo_module
# -- Compiling architecture europa of cpu_cpu_instruction_fifo_fifo_module
# -- Compiling entity cpu_instruction_receive
# -- Compiling architecture europa of cpu_instruction_receive
# -- Loading entity cpu_cpu_instruction_fifo_fifo_module
# -- Compiling entity cpu_wait_counter
# -- Compiling architecture europa of cpu_wait_counter
# -- Compiling entity cpu_subinstruction_unit
# -- Compiling architecture europa of cpu_subinstruction_unit
# -- Compiling entity cpu_instruction_scheduler
# -- Compiling architecture europa of cpu_instruction_scheduler
# -- Loading entity cpu_wait_counter
# -- Loading entity cpu_subinstruction_unit
# -- Compiling entity cpu_commitment_maker
# -- Compiling architecture europa of cpu_commitment_maker
# -- Loading entity cpu_instruction_fetch
# -- Loading entity cpu_instruction_receive
# -- Loading entity cpu_instruction_scheduler
# -- Compiling entity cpu_2ei4_unit
# -- Compiling architecture europa of cpu_2ei4_unit
# -- Compiling entity cpu_constant_generator
# -- Compiling architecture europa of cpu_constant_generator
# -- Loading entity cpu_2ei4_unit
# -- Compiling entity cpu_reg_index_calculator
# -- Compiling architecture europa of cpu_reg_index_calculator
# -- Compiling entity cpu_branch_unit
# -- Compiling architecture europa of cpu_branch_unit
# -- Compiling entity cpu_index_match_unit
# -- Compiling architecture europa of cpu_index_match_unit
# -- Compiling entity cpu_jump_unit
# -- Compiling architecture europa of cpu_jump_unit
# -- Compiling entity cpu_offset_adder
# -- Compiling architecture europa of cpu_offset_adder
# -- Compiling entity cpu_data_master
# -- Compiling architecture europa of cpu_data_master
# -- Loading entity cpu_offset_adder
# -- Compiling entity cpu_op_b_mux
# -- Compiling architecture europa of cpu_op_b_mux
# -- Loading entity cpu_hidden_lcell_66fc
# -- Loading entity cpu_hidden_lcell_12f0
# -- Compiling entity cpu_op_a_mux
# -- Compiling architecture europa of cpu_op_a_mux
# -- Compiling entity cpu_data_forwarding_logic
# -- Compiling architecture europa of cpu_data_forwarding_logic
# -- Compiling entity cpu_op_fetch
# -- Compiling architecture europa of cpu_op_fetch
# -- Loading entity cpu_op_b_mux
# -- Loading entity cpu_op_a_mux
# -- Loading entity cpu_data_forwarding_logic
# -- Compiling entity cpu_aluadder
# -- Compiling architecture europa of cpu_aluadder
# -- Loading entity cpu_hidden_lcell_4def
# -- Loading entity cpu_hidden_lcell_4cef
# -- Compiling entity cpu_op_a_condition
# -- Compiling architecture europa of cpu_op_a_condition
# -- Compiling entity cpu_op_b_condition
# -- Compiling architecture europa of cpu_op_b_condition
# -- Compiling entity cpu_adder_logic_lock_region
# -- Compiling architecture europa of cpu_adder_logic_lock_region
# -- Loading entity cpu_aluadder
# -- Loading entity cpu_op_a_condition
# -- Loading entity cpu_op_b_condition
# -- Compiling entity cpu_alulogic
# -- Compiling architecture europa of cpu_alulogic
# -- Loading entity cpu_hidden_lcell_64fc
# -- Loading entity cpu_hidden_lcell_30f0
# -- Loading entity cpu_hidden_lcell_10f0
# -- Compiling entity cpu_alushifter
# -- Compiling architecture europa of cpu_alushifter
# -- Compiling entity cpu_shiftvalue_conditioner
# -- Compiling architecture europa of cpu_shiftvalue_conditioner
# -- Compiling entity cpu_op_override_unit
# -- Compiling architecture europa of cpu_op_override_unit
# -- Compiling entity cpu_byteshift_control_unit
# -- Compiling architecture europa of cpu_byteshift_control_unit
# -- Compiling entity cpu_aluzerocheck
# -- Compiling architecture europa of cpu_aluzerocheck
# -- Compiling entity cpu_skip_unit
# -- Compiling architecture europa of cpu_skip_unit
# -- Loading entity cpu_aluzerocheck
# -- Compiling entity cpu_control_register_unit
# -- Compiling architecture europa of cpu_control_register_unit
# -- Loading entity cpu_skip_unit
# -- Compiling entity cpu_compact_alu
# -- Compiling architecture europa of cpu_compact_alu
# -- Loading entity cpu_adder_logic_lock_region
# -- Loading entity cpu_alulogic
# -- Loading entity cpu_alushifter
# -- Loading entity cpu_shiftvalue_conditioner
# -- Loading entity cpu_op_override_unit
# -- Loading entity cpu_byteshift_control_unit
# -- Loading entity cpu_control_register_unit
# -- Compiling entity cpu_cwp_adder
# -- Compiling architecture europa of cpu_cwp_adder
# -- Compiling entity cpu_register_file
# -- Compiling architecture europa of cpu_register_file
# -- Loading entity cpu_cwp_adder
# -- Loading entity cpu_register_bank_a_module
# -- Loading entity cpu_register_bank_b_module
# -- Compiling entity cpu_rom_decoder_unit
# -- Compiling architecture europa of cpu_rom_decoder_unit
# -- Loading entity cpu_instruction_decoder_rom_module
# -- Compiling entity cpu_instruction_decoder
# -- Compiling architecture europa of cpu_instruction_decoder
# -- Loading entity cpu_rom_decoder_unit
# -- Compiling entity cpu_pipeline
# -- Compiling architecture europa of cpu_pipeline
# -- Loading entity cpu_interrupt_control
# -- Loading entity cpu_commitment_maker
# -- Loading entity cpu_constant_generator
# -- Loading entity cpu_reg_index_calculator
# -- Loading entity cpu_branch_unit
# -- Loading entity cpu_index_match_unit
# -- Loading entity cpu_jump_unit
# -- Loading entity cpu_data_master
# -- Loading entity cpu_op_fetch
# -- Loading entity cpu_compact_alu
# -- Loading entity cpu_register_file
# -- Loading entity cpu_instruction_decoder
# -- Compiling entity cpu
# -- Compiling architecture europa of cpu
# -- Loading entity cpu_opcode_display_unit
# -- Loading entity cpu_pipeline
# -- Compiling entity pio_led_display
# -- Compiling architecture europa of pio_led_display
# -- Compiling entity lancelot_vga
# -- Compiling architecture behavior of lancelot_vga
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/lancelot_vga.vhd(183): No default
binding for component: "lancelot_dpram_256x24". (No entity named
"lancelot_dpram_256x24" was found)
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/lancelot_vga.vhd(204): No default
binding for component: "lancelot_fifo". (No entity named "lancelot_fifo" was
found)
# -- Compiling entity lancelot_fifo
# -- Compiling architecture behavior of lancelot_fifo
# WARNING[1]:
C:/qdesigns/Lancelot_nios/reference_design/lancelot_fifo.vhd(63): No default
binding for component: "lancelot_dpram_160x32". (No entity named
"lancelot_dpram_160x32" was found)
# -- Loading package altera_mf_components
# -- Compiling entity lancelot_dpram_160x32
# -- Compiling architecture syn of lancelot_dpram_160x32
# -- Loading entity altdpram
# -- Compiling entity lancelot_dpram_256x24
# -- Compiling architecture syn of lancelot_dpram_256x24
# -- Compiling entity vga
# -- Compiling architecture europa of vga
# -- Loading entity lancelot_vga
# -- Compiling entity pio_ps2
# -- Compiling architecture europa of pio_ps2
# -- Compiling entity uart_tx
# -- Compiling architecture europa of uart_tx
# -- Compiling entity uart_rx_stimulus_source
# -- Compiling architecture europa of uart_rx_stimulus_source
# -- Loading entity uart_tx
# -- Loading entity uart_rx_stimulus_source_character_source_rom_module
# -- Compiling entity uart_rx
# -- Compiling architecture europa of uart_rx
# -- Loading entity uart_rx_stimulus_source
# -- Compiling entity uart_regs
# -- Compiling architecture europa of uart_regs
# -- Compiling entity uart
# -- Compiling architecture europa of uart
# -- Loading entity uart_rx
# -- Loading entity uart_regs
# -- Compiling entity boot_rom
# -- Compiling architecture europa of boot_rom
# -- Loading entity boot_rom_lane0_module
# -- Compiling entity dma_control_port_slave_arbitrator
# -- Compiling architecture europa of dma_control_port_slave_arbitrator
# -- Compiling entity dma_write_master_arbitrator
# -- Compiling architecture europa of dma_write_master_arbitrator
# -- Compiling entity dma_read_master_arbitrator
# -- Compiling architecture europa of dma_read_master_arbitrator
# -- Compiling entity pwm_right_avalons_arbitrator
# -- Compiling architecture europa of pwm_right_avalons_arbitrator
# -- Compiling entity pwm_left_avalons_arbitrator
# -- Compiling architecture europa of pwm_left_avalons_arbitrator
# -- Compiling entity sdram_s1_arbitrator
# -- Compiling architecture europa of sdram_s1_arbitrator
# -- Compiling entity cpu_data_master_arbitrator
# -- Compiling architecture europa of cpu_data_master_arbitrator
# -- Compiling entity cpu_instruction_master_arbitrator
# -- Compiling architecture europa of cpu_instruction_master_arbitrator
# -- Compiling entity pio_led_display_s1_arbitrator
# -- Compiling architecture europa of pio_led_display_s1_arbitrator
# -- Compiling entity vga_avalons_arbitrator
# -- Compiling architecture europa of vga_avalons_arbitrator
# -- Compiling entity pio_ps2_s1_arbitrator
# -- Compiling architecture europa of pio_ps2_s1_arbitrator
# -- Compiling entity uart_s1_arbitrator
# -- Compiling architecture europa of uart_s1_arbitrator
# -- Compiling entity ext_bridge_avalon_slave_arbitrator
# -- Compiling architecture europa of ext_bridge_avalon_slave_arbitrator
# -- Loading entity nios_fast_output_register
# -- Compiling entity boot_rom_s1_arbitrator
# -- Compiling architecture europa of boot_rom_s1_arbitrator
# -- Compiling entity nios
# -- Compiling architecture europa of nios
# -- Loading entity dma
# -- Loading entity pwm_right
# -- Loading entity pwm_left
# -- Loading entity sdram
# -- Loading entity cpu
# -- Loading entity pio_led_display
# -- Loading entity vga
# -- Loading entity pio_ps2
# -- Loading entity uart
# -- Loading entity boot_rom
# -- Loading entity dma_control_port_slave_arbitrator
# -- Loading entity dma_write_master_arbitrator
# -- Loading entity dma_read_master_arbitrator
# -- Loading entity pwm_right_avalons_arbitrator
# -- Loading entity pwm_left_avalons_arbitrator
# -- Loading entity sdram_s1_arbitrator
# -- Loading entity cpu_data_master_arbitrator
# -- Loading entity cpu_instruction_master_arbitrator
# -- Loading entity pio_led_display_s1_arbitrator
# -- Loading entity vga_avalons_arbitrator
# -- Loading entity pio_ps2_s1_arbitrator
# -- Loading entity uart_s1_arbitrator
# -- Loading entity ext_bridge_avalon_slave_arbitrator
# -- Loading entity boot_rom_s1_arbitrator
# -- Compiling entity test_bench
# -- Compiling architecture europa of test_bench
# -- Loading entity nios
# vsim test_bench
# Loading C:/Modeltech_ae/win32aloem/../win32aloem/convert_hex2ver.dll
# Loading C:/Modeltech_ae/win32aloem/../std.standard
# Loading C:/Modeltech_ae/win32aloem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_ae/win32aloem/../ieee.numeric_std(body)
# Loading altera_vhdl_support.altera_vhdl_support_lib(body)
# Loading C:/Modeltech_ae/win32aloem/../ieee.std_logic_arith(body)
# Loading C:/Modeltech_ae/win32aloem/../ieee.std_logic_unsigned(body)
# Loading work.test_bench(europa)
# Loading work.nios(europa)
# Loading work.dma(europa)
# Loading work.dma_fifo_module(europa)
# Loading work.dma_fifo_module_fifo_ram_module(europa)
# ** Warning: (vsim-3473) Component 'lpm_ram_dp_component' is not bound.
# Time: 0 ps Iteration: 0 Region:
/test_bench/dut/the_dma/the_dma_fifo_module/dma_fifo_module_fifo_ram
# Loading work.dma_mem_read(europa)
# Loading work.dma_mem_write(europa)
# Loading work.pwm_right(europa)
# ** Failure: Default binding had errors for entity "lancelot_pwm" on the
component declaration of line 88. See the compiler messages.
# Time: 0 ps Iteration: 0 Region: /test_bench/dut/the_pwm_right
# Fatal error at C:/qdesigns/Lancelot_nios/reference_design/pwm_right.vhd
line 96
# while elaborating region: /test_bench/dut/the_pwm_right
# Load interrupted
# Error loading design
# ERROR: parsing expression ""
# Null argument. refScope
# Error in macro ./virtuals.do line 2
# parsing expression ""
# Null argument. refScope
#
# while executing
# "virtual signal {
/test_bench/DUT/the_cpu/sim_generate5/instruction_display/opcode[6:0] }
instruction_opcode_bits
# "
# 1
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