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For my research purposes, I'm considering what effects a corner turning interconnect has, by comparing apples to apples with Virtex family interconnect (long story). One disadvantage is that less frequently used inputs and outputs cost relatively more (since inputs and outputs connect to ALL possibilities, its a different logical depopulation). So I want to, in my comparisons, remove a couple of outputs for modeling my logic block. So the question is, how often and WHY are the carry chains driven to the XB and YB outputs. According to the slice internals, they are only capable of being driven by the carry chain (XB) or carry chain or routhrough (YB). What logic tends to use these outputs beyond the top carry out? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 46501
When people are wanting to use TEC's with this type of resolution, it usually means they are temperature stabilizing a laser in an optical signaling link. This leads to better stability in laser frequency, and is mandatory for DWDM systems. See for example this canned solution from Maxim, that claims .001 degree C control: http://www.maxim-ic.com/view_press_release.cfm/release_id/600 See the data sheet for more details and application education. Since these apps also need some power FETs as well, their solution at $7.50 to $9.00 would seem to beat any FPGA attempt. Philip On Sun, 01 Sep 2002 18:40:18 GMT, Peter Alfke <palfke@earthlink.net> wrote: >Masoud, can you please explain to me and other non-experts: >What is a thermo-electric cooler? >Do you mean an electronic Peltier-effect device? Yes >Or do you mean a fan? No >Where do you get the sub-one-degree accuracy from, and why does it >matter? I would think that the purpose is to cool the IC, and the >difficulty is measuring the junction temperture. And at significant >localized power dissipation, where and how do you measure the >temperature? See above >Lots of questins before we start arguing PWW frequency... >Maybe I just do not understand the basics. >Peter Alfke, Xilinx Applications > >Masoud Naderi wrote: > >> Hi, >> Did anyone build a controller for thermoelectric coolers by PWM method >> and FPGAs? >> I want to do this, but i didn't know pwm frequency for 0.01C >> resolution. I guess there are other potential problems. please let >> know them >> best regards >> masoud naderi Philip Freidin FliptronicsArticle: 46502
On Sun, 1 Sep 2002 17:47:44 +0100, "Niv" <niv@ntlworld.com> wrote: >Hi, any thoughts on muxing a tristate bus? > >I have the following scenario in a Virtex design: > >About 10 blocks that all communicate to a CPU via a single tristate bus, one >at a time of course. >However, two of these blocks are deemed "safety critical". So, to enhance >the design safety, it has been decided that these two blocks should be >isolated from the rest. >To this end, their outputs will be permanently enabled, and fed to a mux., >but what to do with the other 8 or so blocks? I think I understand what "safety critical" may mean, but I don't know how permanently enabeling their outputs and feeding it to a mux is any more reliable than feeding the outputs to the tristate bus the same way as the rest of your blocks. Either your block select logic works and whether you are controlling muxes or tristate-enables, the system will work. Or, your block select logic is not trustworthy, and muxes are not going to help you get a more reliable system behavior than with a tristate interface. This is particularly equivalent in the Virtex family, and all following families, as I believe none of them actually have internal tristate busses. Although you can implement internal tristate busses (and even see them if you look in the FPGA editor), they are in fact emulated by muxes and apropriate control logic. The following MIGHT be interesting: www.uspto.gov Patent 5847480 >It is a major redesign to make them all permanent outputs and mux all 10 >buses. (Not difficult, but very time consuming). > >So, is it a "safe" design to put the 8 block tristate bus into the mux; the >mux thus having 3 bus inputs and a single bus output to the CPU? If you control the tristates and the mux correctly, yes. >Any help much appreciated, NIV. Philip Philip Freidin FliptronicsArticle: 46503
Hello, I have two data buses running at two different but constant clock frequencies. Each byte on the slower bus must be moved onto the faster bus. Therefore not every clock of the faster bus will carry data. How do I latch the data with the higher speed clock reliably ? I do not want to clock data when the slower bus is changing state and therefore undefined. I also need to know which clock cycles on the high speed bus will be unused. I assume this is a common problem, hopefully with a known and reliable solution. Thank you. DanArticle: 46504
I notice you are using the xc18v04 instead of the xc18v02, which is the recommended device for the spartan2 xc2s200. Is there a reason for this? How are you filling up the rest of the unused memory? That may confuse the checksum calculation. I believe there is a way to select the "fill" bit. Also is the right device selected when you generate the bit file? Nicolas Matringe wrote: > arvind wrote: > >>i am trying to configure the sprtan2 xc2s200 pq208 fpga with >>xc18v04 prom in "master serial mode" but the done pin is not >>getting high. >>the prom is programmed successfully but the chacksum is not >>matching when i am trying to read chacksum from PROM it is not >>matching by desired chacksum. >> > > Hi > Have you used the same bitstream for the PROM and the JTAG configuration? > The startup clock must be "cclk" for a PROM and "JTAG Clk" for the JTAG > configuration. > >Article: 46505
Wow, this is really what I needed. I am printing it out as I type this. I still haven't gotten an eval licence for ModelSim, the licence generator did not work (and the latest webpack crashes the Win2000 system boot so I use the second-latest), but at least this will get me going. Funny how it *does* work in XP under VMware. It's a driver problem. I am working on a program that plays the game of go, and I want to make the life-death analysis in a Spartan II. It will be a week before I'll get the eval board. How do you recommend going about a rather large design when you can only simulate 500 lines of VHDL in the eval version of ModelSim? Would you recommend using a logic analizer on the 'real thing' instead? Frank (utter newbie) "Al Williams" <alw@al-williams.com> wrote in message news:a9835df1.0209010723.3ddbbd53@posting.google.com... > Wow, after posting, I did a quick google search and dug for some I had > not seen before. This site has an excellent looking tutorial in PDF: > http://www.trenz-electronic.de/down/tc-XC2S-SoC-2.pdfArticle: 46506
--------------5C571DDA8A7DDE6E3E800EC3 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Look at http://www.xilinx.com/support/techxclusives/MovingData-techX16.htm Peter Alfke, Xilinx Applications Dan wrote: > Hello, > > I have two data buses running at two different but constant clock > frequencies. Each byte on the slower bus must be moved onto the faster bus. > Therefore not every clock of the faster bus will carry data. How do I latch > the data with the higher speed clock reliably ? I do not want to clock data > when the slower bus is changing state and therefore undefined. I also need > to know which clock cycles on the high speed bus will be unused. I assume > this is a common problem, hopefully with a known and reliable solution. > Thank you. > > DanArticle: 46507
I'm using virtex2 xcv4000 fpga. the programming is done in serial mode using 4 proms. during the configuration proccess , at the last ~250 ms I detect a high pulse on all outputs of the device. what can cause it ?Article: 46508
John_H wrote: > o <= (sel ? a : c) > + (sel ? b : 0); Thank you, thank you, thank you! That works beautifully under Synplicity. And since Synplicity names every synthesized carry net "*_cry_*", the following set of time specs seem to work for me for the single addmux-between-FFs case: net clk period = whatever ns; net "c[*]" tpthru=c; net "*_cry_*" tpthru=cry; timespec TScryign=from ffs thru c thru cry to ffs 100; The timespec specs don't seem to promise that two or more 'thru's in a given timespec will be honored, but the tools took it, and my experiments seem to indicate it has the desired effect. For example, constrained as shown, c[i] input nets are no longer incurring carry delays in routing through to o[i] output nets, and do not carry into o[j], j>i. And yet a[i] and b[i] nets do seem to participate in carry paths as desired. [Xilinx: please confirm that a timespec can have more than one 'thru' and yet the "right thing" happens (constraint only applies to those paths that go through all the 'thru' points).] Note that since the same source FFs source logic for both the a[], b[], and c[] nets above, I could not do this with a simpler timespec. The only paths I wanted to ignore were those specifically coming into the addmux on the 'c' nets and then generating false paths through "*_cry_*" nets. Also, to get Synplify to always do the "right thing" in generating the netlist, I also had to attribute the c[] nets with /* synthesis syn_keep=1 */; So I now have a (nonportable) way to get what I want, although I have to add a timespec (each with two tpthrus) for every addmux in my design (could be dozens). This is much better than any alternative I have yet seen, though. Xilinx, it would be nice if there was a better way to do this, but this will do. Thanks again, John. Jan Gray, Gray Research LLCArticle: 46509
Hello, there is a second field of application calling for very accurate TEC (Peltier Cooler/Heater), the infra red camera based on micro bolometer technology (will be main stream in a few years in the car industry). The question to use or not to use a FPGA for a TEC controller is depending on the design or application environment. If, as it's often the case, a FPGA is already used in a design, it could be cheaper to use some gates than to place a discrete micro. But, the TEC controller is a closed loop one. You have a temperature sensor, you have do digitise its data, and there is the peltier TEC as the actor element. Some feature of the FPGA could argue for its use like high speed high tap filter banks. So, it would be interesting to see what level of performance an FPGA based TEC controller core would reach (e.g. serial data input, PID controller, PWM output). Holger Venus "Peter Alfke" <palfke@earthlink.net> schrieb im Newsbeitrag news:3D725F1E.85EFF2D2@earthlink.net... > Masoud, can you please explain to me and other non-experts: > What is a thermo-electric cooler? > Do you mean an electronic Peltier-effect device? > Or do you mean a fan? > > Where do you get the sub-one-degree accuracy from, and why does it > matter? I would think that the purpose is to cool the IC, and the > difficulty is measuring the junction temperture. And at significant > localized power dissipation, where and how do you measure the > temperature? > > Lots of questins before we start arguing PWW frequency... > Maybe I just do not understand the basics. > Peter Alfke, Xilinx Applications > > Masoud Naderi wrote: > > > Hi, > > Did anyone build a controller for thermoelectric coolers by PWM method > > and FPGAs? > > I want to do this, but i didn't know pwm frequency for 0.01C > > resolution. I guess there are other potential problems. please let > > know them > > best regards > > masoud naderi >Article: 46510
I designed an SDRAM controller by Verilog using in Altera APEX20KE. But the timing analyser report tell me, the crtical path is about 15ns. I think that my Verilog module design is not good. Maybe too combine logic. Which book or reference can tell me how to do design high-speed logic? Best RegardsArticle: 46511
> > i am trying to configure the sprtan2 xc2s200 pq208 fpga with > > xc18v04 prom in "master serial mode" but the done pin is not > > getting high. > > the prom is programmed successfully but the chacksum is not > > matching when i am trying to read chacksum from PROM it is not > > matching by desired chacksum. Maybe boundary scan has been invoked. Verify that the TMS is high and that the TCK is not moving. This problem is described at support.xilinx.com. PiotrArticle: 46512
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<akq75t$1k46rp$1@ID-84877.news.dfncis.de>... > "Jianrong Wang" <goodpanda35@sohu.com> schrieb im Newsbeitrag > news:9b325b3d.0208310154.6f673fd8@posting.google.com... > > Dear Sir: > > I like the fpga design. This is the first time i login in the > > news gruop by google.com. But i think it is very complex to use google > > to login.Can you tell me a simple way to use MS-outlook express to > > login. > > Just find a news server, create a account in Outlook for news, you are done. > I use a free news server from germany > > http://news.cis.dfn.de/ > > You need to register, but its all free. Does this allow posting too? The news server I've been using news.cn99.com does not allow posting, only reading. Anyway, I've already registered and waiting for the response. --NeerajArticle: 46513
The renowned Holger Venus <Holger.Venus@dlr.de> wrote: > there is a second field of application calling for very accurate TEC > (Peltier Cooler/Heater), the infra red camera based on micro bolometer > technology (will be main stream in a few years in the car industry). > The question to use or not to use a FPGA for a TEC controller is > depending on the design or application environment. If, as it's often the > case, a FPGA is already used in a design, it could be cheaper to use > some gates than to place a discrete micro. But, the TEC controller is a > closed loop one. You have a temperature sensor, you have do digitise > its data, and there is the peltier TEC as the actor element. > Some feature of the FPGA could argue for its use like high speed high tap > filter banks. So, it would be interesting to see what level of performance > an FPGA based TEC controller core would reach (e.g. serial data input, > PID controller, PWM output). What's missing is some kind of number for how fast the controlled object can change temperature (and any demand or setpoint changes that have to be tracked). The PWM count frequency will be orders of magnitude higher than the control response in any case. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com 9-11 United we StandArticle: 46514
You might take a look at the mem_ctrl (inc SDRAM) project over at www.opencores.org It is a well designed core (IMHO) and you could relatively easily cut it down to do just the SDRAM portion of what it offers and use your own interface rather than the wishbone bus that it currently interfaces to. IMHO the use of reusing open rows rather than closing and then reopening is a huge performance improver for SDRAM if your data is in any way localised. Its verilog only which is a shame for us VHDL souls. PS using a PLL for your memory clock may improve things as will pipelining the design. For a relatively simple SDRAM controller (Altera's one available in VHDL or verilog from their site for free) the Apex20ke is clocking at over 120MHz in my temp design. Since I have a fairly simple sequential data block movement job I have just ended up with my own simple state machine controller than clocks (registered perf) at over 150MHz (though I'm only using it at 120MHz). "Arguo" <s9323090@cc.ncu.edu.tw> wrote in message news:52758910.0209020319.70d66511@posting.google.com... > I designed an SDRAM controller by Verilog using in Altera APEX20KE. > But the timing analyser report tell me, the crtical path is about 15ns. > I think that my Verilog module design is not good. Maybe too combine logic. > Which book or reference can tell me how to do design high-speed logic? > > Best RegardsArticle: 46515
Thanks, taking the x least significant bits seems to have sorted things out. My code still won't compile due to variable scoping issues with macro procs. I've searched in Help but nonetheless I'll post a separate thread on this once I can give a bit more information. Govind Andy.Nisbet@cs.tcd.ie (Dr. Andy Nisbet) wrote in message news:<b34653f8.0208300219.77841f27@posting.google.com>... > Hello, > the solution is to only supply the 9 least significant bits ... > > i<-9 means take the 9 LSBs of i. > > Go to help in DK1 and search on operators and you will find a description. > > Cheers, > Andy >Article: 46516
Hello. I'm doing a thesis on digital design and one of the areas i'm interested in is filter design using FPGA's. My knowledge of FPGA's is very basic I'm afraid. In my Verilog design file for a FIR filter, the filter constants are hard coded into a serial shift register using the Initial statement. The output of the shift register is fed back to the serial input. This way the registers will produce the coeffesients serialy ad infinitum. The Verilog code looks something like this: module something() output,input ect. reg sR [12:0]; initial sR=12'b011010101101; assign out=sR[0]; always @(posedge c0) begin sR=sR >> 1; ect. The reg statement will probably syntehsize into RAM on the FPGA, the initial statement will not synthesize at all ( I'm using Leonardo targeting Altera's FLEX devices). The initial statement probably implies some sort of ROM for the numbers and then loading the contents of that ROM into the serial shift registers at startup.(?) What is the best strategy for writing a syntesizable Veriloge code that does this ? I am grateful for any help.Article: 46517
I read about Transmeta's Crusoe chip some time back, which has something called the Code Morphing Software. This code morphing s/w actually reads hex from its code memory, and at run-time translates the hex code into equivalent native machine language instructions. So the whole system itself is like a Java Virtual Machine (or a run-time cross-assembler), only there is no partitioning between the H/W and the system S/W. The whole thing is a overhead, of course, but its highly optimized and parallelized in hardware wherever possible. Last I read, they had code morphing software for 8086 instructions, i.e the Code Morphing Software could only "understand" 86 hex. This system also allows you to run programs compiled for different processors at the same time, i.e it decides at run-time which instruction set is supported. Ok here's an idea... how about code-morphing HARDWARE? A pretty challenging VLSI project actually, possible too. Here's how I think it may work: This Code Morphing (CM) chip would be placed on the bus in between the target uC and the code memory (ROM, flash wotever). It would route the addresses generated by the uC to the code memory, and translate the returned contents into hex code of the target uC, and send the translated version back to the uC. This is pretty much what the JVM does, but this virtual machine is a HARDWARE virutal machine, i.e. the mapping between various instruction sets is HARD-WIRED. Ok, maybe we could make it more generic, and endow the CM chip with large register sets and/or memory areas, which can be dynamically loaded with the target and foreign instruction sets and the mapping between them. In fact maybe later on we could add a number of code-mappings onto a single device. Since all the translation happens in hardware, there can be virtually no overheads (I think!). It will be especially easy when dealing with similar instruction sets, like CISC-to-CISC and RISC-to-RISC. Even if it is CISC-to-RISC, the performance will not be truly affected, because it will simply replace the CISC instruction with the equivalent CISC instructions, and may actually end up saving code memory. Since we have software cross-assemblers, it is conceivable that they can be implemented in hardware. Of course, there are a LOT of issues here, and operation may be slowed down slightly, but it IS possible. The biggest problem would be mapping between specific registers, but we can leave that to the application programmer or the source assembler / compiler. The applications of such a device would be very interesting indeed. A code-morph for Java bytecode is only the beginning.... Backward Compatibility will not be an issue anymore. This, I understand, is keeping them from using all the features on the latest Intel chips. We can load protocol-translation mappings to, transperently converting from, say RS-232 to I2C (we already have hardware TCP/IP stacks). We could port the hex code itself to other processors, instead of re-writing the source code and re-compiling. Programmers can include useful language features from other instructions sets without having to worry about implementing them in the target processor code. Ok that's enough speculation for now, but could anyone well-versed in VLSI design tell me how feasible this is? I don't think it will be very difficult to implement, but the design of such a chip would be very challenging. Also I need to know from experienced embedded systems designers how truly useful such a device would be, and would all the effort of developing it pay off, in terms of financial returns and intellectual property rights. kundiArticle: 46518
As a Verilog user, I currently create parametric Xilinx RPMs in a
meta-language (Python). I have always admired Ray Andraka et al's use of
VHDL generate statements to build parametric RPMs in the HDL itself.
So I was pleased to read that the latest version of Synplicity has support
for Verilog 2001 language features, including generate statements.
Alas, this feature is next to useless for building Verilog RPMs. In VHDL,
the RLOC attributes can be computed, and *attributed*, to the generated
primitives. In (Synplify) Verilog, the RLOC attributes are attached as /*
synthesis ... */ comments so there does not appear to be a way to
parametrically generate something like this:
module fde4v2(clk, ce, d, q) /* synthesis syn_hier="hard" */;
input clk, ce;
input [3:0] d;
output [3:0] q;
FDE r0(.C(clk), .CE(ce), .D(d[0]), .Q(q[0]))
/* synthesis RLOC="X0Y0" */;
FDE r1(.C(clk), .CE(ce), .D(d[1]), .Q(q[1]))
/* synthesis RLOC="X0Y0" */;
FDE r2(.C(clk), .CE(ce), .D(d[2]), .Q(q[2]))
/* synthesis RLOC="X0Y1" */;
FDE r3(.C(clk), .CE(ce), .D(d[3]), .Q(q[3]))
/* synthesis RLOC="X0Y1" */;
endmodule
I'll stick with Python.
Jan Gray, Gray Research LLC
Article: 46519Do you get offended if someone label you as IT consultant? Sadly a lot of talented engineering graduates ended up in IT department. Cheers! Duy K DoArticle: 46520
Hello all Im new to this FPGA design stuff so appreciation in advance for all help or redirection. How do I configure an IOB to divide the applied clk of 100MHz by 2 and feed the rest of the FPGA with 50MHz. I am coding in verilog. I also need to gate the 100MHz clock with an enable signal. I can do this with an AND gate. Do I need to feed two clock inputs with the 100MHz signal. Denis PS I am targeting xilinx XCS05XLArticle: 46521
"Kunal" <kundi_forever@yahoo.com> wrote in message news:cd714c44.0209020625.5b892675@posting.google.com... > I read about Transmeta's Crusoe chip some time back, which has > something called the Code Morphing Software. This code morphing s/w > actually reads hex from its code memory, and at run-time translates > the hex code into equivalent native machine language instructions. So > the whole system itself is like a Java Virtual Machine (or a run-time > cross-assembler), only there is no partitioning between the H/W and > the system S/W. > > The whole thing is a overhead, of course, but its highly optimized and > parallelized in hardware wherever possible. Last I read, they had code > morphing software for 8086 instructions, i.e the Code Morphing > Software could only "understand" 86 hex. This system also allows you > to run programs compiled for different processors at the same time, > i.e it decides at run-time which instruction set is supported. > > Ok here's an idea... how about code-morphing HARDWARE? > How about chips like the Intel P4 which hardware translates the X86 code that sits in memory into the instruction set for the different microprocessor that actually runs the code? Works well enough for Intel to make lots of money selling them. -- - Stephen Fuld e-mail address disguised to prevent spamArticle: 46522
"Kunal" <kundi_forever@yahoo.com> schrieb im Newsbeitrag news:cd714c44.0209020625.5b892675@posting.google.com... [Code morphing in microprocessors and FPGAs ] I never understood what the hell is the advantage of putting some kind of realtime compiler into expensive silliy-cone? Wouldnt those Transmeta guys be much smarter (and nowadays much richer) if the had done a nice optimiced RISC or whatever CPU and wrote a "simple" piece of software "aka translator, compiler whatever) to translate a x86 code to native RISC just before executing it, then load the RISC-code into RAM and execute it.? Anyone can enlighten me? -- MfG FalkArticle: 46523
"Denis Gleeson" <dgleeson@utvinternet.com> schrieb im Newsbeitrag
news:6f080894.0209020758.6940960@posting.google.com...
> Hello all
>
> Im new to this FPGA design stuff so appreciation in advance for
> all help or redirection.
>
> How do I configure an IOB to divide the applied clk of
> 100MHz by 2 and feed the rest of the FPGA with 50MHz.
> I am coding in verilog.
Aha, Mr. Clock enable again. First, the division cant directly be done in
the IOB, you must use a normal CLB FlipFlop. But this is no problem.
The task is simple, but I dont speak verilog, so that a task for other guys
around here.
> I also need to gate the 100MHz clock with an enable signal.
> I can do this with an AND gate.
in VHDL
gated_clock <= clk_100M AND ena; -- the clock gating
process(clk_100M)
begin
if clk='0' and clk'event then -- generate
enable on the FALLING edge
ena <= ena_requested; -- your logic must
drive ena_requested as you need it
end if;
end process;
> Do I need to feed two clock inputs with the 100MHz signal.
No. Just connect the 100 MHz to a global (her called primary) clock input.
This will connect directly to a global (primary) clock buffer. After
division you can route (its done automatically unless you prevent it) the 50
MHz clock to a second global clock buffer (SpartanXL has 8)
--
MfG
Falk
Article: 46524"Neeraj" <neeraj_varma@yahoo.com> schrieb im Newsbeitrag news:141db5c.0209020332.20d172fb@posting.google.com... > > http://news.cis.dfn.de/ > > > > You need to register, but its all free. > > Does this allow posting too? The news server I've been using Sure. Its a news-SERVER, not a news-PAPER ;-))) > news.cn99.com does not allow posting, only reading. Anyway, I've > already registered and waiting for the response. I dont know how long it took for me, can be a few days. -- MfG Falk
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