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Hi Yan,
> It is possible to save simulation results with modelsim, instead of running
> the simulation again when needed?
> Yan
Yes, it is possible. Modelsim saves the result of the simulation in a
file called *.wlf (typically "vsim.wlf" if you do not choose another
file name for it). You can load this file with "vsim -view <filename>.wlf".
To view this file choose the signals and add them with "add wave <signal>"
(typically done with a little *.do file which also preserves the signal
ordering".
Hope this helps,
Markus Sponsel
(To answer me directly remove "nospam" from the e-mail address)
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"Yan" <chan_jurgens@planet.nl> schrieb im Newsbeitrag news:allf4h$qek$1@reader13.wxs.nl...
> Hi,
> It is possible to save simulation results with modelsim, instead of running
> the simulation again when needed?
> Yan
Article: 46901Hello, I'm working on a Xilinx XC2V6000 design which will make use of nearly all (144) of the embedded multipliers and am trying to use Chipscope at the same time. I believe that Chipscope uses the block ram in a x36 configuration, because I am getting PAR "unroutable" errors now that the number of multipliers is growing, due to design module integration. When the number of multipliers + the number of Chipscope block rams is about 144, or less, there are no PAR errors. Also, I've read (in Google and the Xilinx datasheets) that if a block ram and the adjacent multiplier are used, then the width of the block ram is limited to x18 or less, so that the multiplier can be used, due to routing between the multiplier and block ram. The basic flow is: VHDL -> synthesis -> Chipscope Inserter -> Xilinx tools. I've looked at the fpga using FPGA editor and it does seem that the block ram is used in a x36 configuration. Could anyone tell me if this sort of issue is true when using the embedded multipliers and Chipscope? If so, is there a work-around, for validation/debugging? Can Chipscope use the block ram in a different configuration? Thank you for your time, MarkArticle: 46902
> I meant this as a alternative for the first, single D register - ie the > clock domain syncroniser - wondering if there was benefit in two > registers, over one with a longer delay. I didn't see any comments on this so I'll take a try... Suppose you have the classic pair of FFs as a synchronizer. Use that as a straw man, a base case for goodness. Now suppose you put some logic in there. How about a simple AND gate. Does that make things better? Take the simple case of tying one side of the AND gate high. That prop time through the gate subtracts from the metastability settling time. That settling time is in an exponent in the goodness formula. It's hard to beat something in an exponent. Go back and check Peter's numbers that started this thread. More time is good. Kludgery is not good. Anything other than a wire is probably kludgery. You might be able to do something by putting a FF in there. But that takes an extra clock cycle. Then you would be better off with a slower clock or clocking on every other cycle. Suppose you clocked the middle FF on the falling edge so it didn't cost you an extra cycle. Now the clock-out time through the FF gets subtracted off from the settling time. Again, that's exponential and a step in the wrong direction. Back to the simple AND gate... If things are going to get better, the other side of that AND gate has to be connected to something "good". Well, if we could do that, we could solve the metastability problem. You have to take my word for it that we can't solve that. The classic picture is rolling a ball over a bump. If you push the ball hard it easily goes over. If you push it gently, it goes up to the bump and bounces off. But in the middle it might get stuck on top for a while. The important point about metastability is that you can't win. There is some time or some energy-of-push for the ball that is the "bad" case that turns into metastability. There is no free lunch. Fixing metastability takes time. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 46903
> No sorry. Most of my references are walking around. John Treichler has > written a book or two. You can search a bit on the web. But I have not > read it, but I can't imagine it is not good. It also helps to work with > a bunch of other guy (or gals) who are learning the stuff too. I > learned a lot from our group discussions. Thanks for the help... unfortunately, have no money to buy books , and I think I am the only person doing this in the nearest 1000 kms! Searching the web has yielded not many, if any, results. Thanks anyway Adrian Dept. Physics and Electronics Rhodes University Grahamstown South AfricaArticle: 46904
Hi Jim, Another idea would be to have several very simple processors (like a 6502) working in parallel. I just found out that my Beta-license to FORGE will expire just as I get the FPGA board, so I'll have to do it another way I'm afraid. FRank "Jim Granville" <jim.granville@designtools.co.nz> wrote in message news:3D7E69BF.4953@designtools.co.nz... > > Sounds like you would be better to try and code in parallel as much as > possible, and work with a view to deploy it to multiple processors. > If the code is not stable, then FPGA migration is unlikely to be > usefull.Article: 46905
George Eccles wrote: > On Tue, 10 Sep 2002 17:00:05 GMT, Troy Schultz <tschultz@canada.com> > wrote: > > >>George Eccles wrote: >> >>>I am considering using an Atmel ATF15xx series CPLD. This would be my >>>first PLD of any sort, and I'm a little bit floundering. For >>>instance, the part data sheet says that outputs can be configured for >>>"open-collector" (open drain?) operation; but, I don't find any >>>mention of that in the "Programmer's Reference Guide". >>> >>>Is there other documentation on these parts? Or, is there a better >>>way to learn this stuff? >>> >>>Thanks, >>>George >>> >>> >>>-----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- >>>http://www.newsfeeds.com - The #1 Newsgroup Service in the World! >>>-----== Over 80,000 Newsgroups - 16 Different Servers! =----- >> >>Last spring I started out with the Atmel ATF15xxx series, mostly due to >>their logic doubling feature. I ran into a large number of problems >>with their software. > > > Was that WinCUPL? If so, do you know what rev it is? They're > currently at 5.2.16. > > Thanks, > George > > > > > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- > http://www.newsfeeds.com - The #1 Newsgroup Service in the World! > -----== Over 80,000 Newsgroups - 16 Different Servers! =----- Yes that was the WinCUPL package, I removed it from my system so unfortunately I can't tell you what version it was. I can however tell you that is does not behave well and you can not always trust what the fitter tells you. With WinCUPL you will be programming in an older language called ABELL, and although well suited for PLDs, you have more options available with the Xilinx software, you can still use ABEL, but also have Verilog and VHDL. There is a bit of a learning curve, but VHDL is a good choice for the CPLDs, it also makes code reuse much easier for future projects. I can't say that the Xilinx software is perfect, but it worked much better for me. I think it also makes sense to stick with one of the largest makers of programmable logic such at Xilinx. Originally I did not look at Xilinx because I was unaware that the free webpack had as many capabilities as it had. I also looked at the list price of the starter software of US$900 and it scared me off a bit. Have a discussion with the local Xilinx rep and you will get a much better feeling for what their focus is. As for the logic doubling, I had done my design with a 36 macrocell Atmel part and replaced it with a 72 macrocell Xilinx part. The Xilinx part came in at US$2.40 each, half of the price of the Atmel part. No matter what you choose there is a learning curve, but I must say that the time it took for me to have a working design with the Xilinx part was minimal. Also thier software has a very nice testbench (simulator) that makes things much easier for anyone starting out, and the results are very accurate. Best of luck with your design. - TroyArticle: 46906
Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3D7CCB51.13EB320@xilinx.com>... > Rick, > > I am saying it has nothing to do with yield. Yield is not a factor. > I defer to Peter's answer. So do I: > Peter Alfke wrote: > 2. Lower yield due to defect density on the wafer. That increases the cost > for any die faster than the growth of the die area. > (Semiconductor Physics 101) I fail to why "lower yield" has nothing to do with "yield" Some information: 1. I do not know the routing architecture of the coolrunner family, but older CPLDs where fully routable using a reqular switch matrix. With this design a 50% increase in logic cells results in a 125% increase in switch matrix area. 2. The formula for yield contains an exponential term. (Do the math: If you have a chance of p that one square milimeter of chip is undamaged, than you have a chance of p^n that your n square milimeter chip is undamaged. If this where in fact the dominating term in the production cost function, one could estimate the original yield: DISCLAIMER: VERY ROUGH ESTIMATE!!! For a yield of the original chip of 1-q and a 4 times cost explosion for the 50% larger chip you get the equation 1 - q^(1,5) = 1/4 (1 - q) q = 0.69, yield=0.31 For the 125% area increase the result is q=0.77, yield=0.23 A yield of 33% percent is not absurd, but I guess that for a 256 Macorcell CPLD Xilinx can do much better. So it seems that the price is not dominated by yield in this case. The price has more likely to do with shareholder value. CU, Kolja SulimmaArticle: 46907
Hello everybody,
I got really confused somehow, and it would be very helpful if someone
could answer this question:
(before, the preliminaries)
I am designing a PCI board, using a Xilinx FPGA, specifically the
XC4010XL as the controller (target only). The board schematic is
ready, the PCB layout is ready too.
The idea is to clock the FPGA with the PCIClk. From the beggining I
thought that was the way to go, but I am considering now the
possibility of clocking the FPGA with a crystal, or deriving a higher
frecueny of the PCIclk (using a Cyrix clock driver, maybe), and using
the PCIclk only to synchronize the signals coming in.
My doubt, specifically is: Do I need to clock the FPGA with a higher
clock than the PCIclk? Doing this will improve the performance of the
design?
To be more graphical:
------------------
PCIClk-->GCk1 |
| XC4010XL |
| |
| |
------------------
Is this allright?
Thank you very much.
You are in your right to think bad of me if this question is too
stupid.
Mauricio Lange
Article: 46908> do > add wave -r /* > > to see everything. Thats the problem. If I type add wave -r /* it seems to take hours and yet produces nothing. I have to kill the process in the end. > Search for the signals you want, and copy the names for a script like: > > ############## > add wave * > # Top level signals > add wave /test_hdlc/ck_bytes/dut/octet_valid > > # My buried signal > > run -all > ############# > > > > How do people using Modelsim for gate level simulations troubleshoot > > their gate level designs ? > > > Do static timing first and you may not have to. > The static timer gives much more specific data on problem delays. > Once static timing is working you should see no problems at the > gate level for synchronous designs. Would the static timing analyzer in Quartus 2 be good enough for the purpose you mention above ? > > Gate level debug tools include code breakpoints, > wave watching and temporarily inserting print or report statements. > > > -- Mike TreselerArticle: 46909
Hi, I'm trying to develop a design and prototype on the A15E board from Altera. This is the design flow I plan to follow. 1. Write RTL. 2. Synthesize RTL in Quartus 2. 3. Simulate the design using Quartus 2 simulator. 4. After the simulation looks correct, program the device on the board. I have seen a lot of people recommend Modelsim for simulations and Leonardo/Synplicity for synthesis. I understand the reasons for using these tools. But, instead if I followed the route of synthesis, place & route and simulation in Quartus 2, would my design work in the FPGA on the board ? I believe it should. Is there anything I should be careful about ? Do let me know. Thanks, PrashantArticle: 46910
Actually, given the complexity of MP3 decoding, the cost of the likely FPGA chip (and power for it), the need to configure the FPGA (i.e. another configuration memory or control chip), the need to clean up the digital noise from the DAC output... Why not use one of the many DSPs with on-board DACs? That's what they're designed for. You can also load the FPGA with the firmware for not only MP3 but OggVorbis and other audio formats as well. Your cell phone works that way - and not by coincidence. Just a thought... Jim Horn (I use FPGAs every day - and CPUs, DSPs, etc.)Article: 46911
Prashant wrote: > I'm trying to develop a design and prototype on the A15E board from > Altera. This is the design flow I plan to follow. > > 1. Write RTL. > 2. Synthesize RTL in Quartus 2. > 3. Simulate the design using Quartus 2 simulator. > 4. After the simulation looks correct, program the device on the > board. Except for the simplest of designs, you need to run simulation before syntheis to find logical errors. Quartus has no way to simulate RTL code. -- Mike TreselerArticle: 46912
Hi Mauricio, Do you actually need a higher speed clock for some parts of the design? You certainly don't for the PCI interface, it should (MUST) be synchronous with the PCI clock. I have done over 20 PCI interfaces in Xilinx FPGAs, and have always simply hooked the clock from the PCI bus to a clock input of the chip...making sure I keep the trace length precisely as outlined in the PCI spec (2.5" if I remember right), and have never had any problem. I do typically run the back end at a different speed than the PCI interface, using FIFOs between the two to synchronize the data. You also should know on the PCB layout to not cross other signals over the PCI to FPGA trace region, and don't cross the PCI signals from the PCI bus to the FPGA (it's best to set the FPGA pinout so the signals literally line right up...but I'd say you can be liberal with the reset, and route that to the appropriate pin near the GSR)...and to provide decoupling caps for all power pins (even unused ones)...as well as not remove any of the gold fingers of unused pins...and to keep the maximum trace length of any PCI signal (except clock and reset typically doesn't matter either...) to 1.5" I believe (see the spec for specifics...). Keep in mind the voltage/slot keying/VIO requirements too... Austin "Mauricio Lange" <weirdo@bbs.frc.utn.edu.ar> wrote in message news:2f938098.0209110554.30afe4cc@posting.google.com... > Hello everybody, > > I got really confused somehow, and it would be very helpful if someone > could answer this question: > > (before, the preliminaries) > I am designing a PCI board, using a Xilinx FPGA, specifically the > XC4010XL as the controller (target only). The board schematic is > ready, the PCB layout is ready too. > The idea is to clock the FPGA with the PCIClk. From the beggining I > thought that was the way to go, but I am considering now the > possibility of clocking the FPGA with a crystal, or deriving a higher > frecueny of the PCIclk (using a Cyrix clock driver, maybe), and using > the PCIclk only to synchronize the signals coming in. > > My doubt, specifically is: Do I need to clock the FPGA with a higher > clock than the PCIclk? Doing this will improve the performance of the > design? > > To be more graphical: > > ------------------ > PCIClk-->GCk1 | > | XC4010XL | > | | > | | > ------------------ > Is this allright? > > > Thank you very much. > You are in your right to think bad of me if this question is too > stupid. > > > Mauricio LangeArticle: 46913
(4.1i) Constraints Guide, TSidentifier, Defining Intermediate Points (UCF) http://toolbox.xilinx.com/docsan/xilinx4/data/docs/cgd/t11.html#1018081 Just saw it - had to share. - John_H Jan Gray wrote: > [Xilinx: please confirm that a timespec can have more than one 'thru' and > yet the "right thing" happens (constraint only applies to those paths that > go through all the 'thru' points).]Article: 46914
Dears, Thank for your responses. But I didn't find any PRACTICAL approach for fault-tolerant FPGA design yet! 1 - Proposed methods such as TMR (majority) have very high overhead (despite their potential problems). As you know, in classical fault-tolerant design techniques overhead is not the main issue, at least it is not the most important one. 2 - The other problem is due to PHYSICAL implementation of a VHDL code. How is it implemented and how designers can control mapping process precisely without involving in too much details. Please note, in traditional design methodes mapping is done by designner rather than by a machine, therefore so many factors would be under control. 3 - There are systems that require high availabity without radiation hardness or other special effects. For example, in Telecomm. %99.999 availability is of concern. What about designing for these systems? 4 - In classical methodes "fault masking" is more important than "fault detection", because reconfiguration requires high overhead and high hardware resources (redundant process elements and redundant links).But reconfiguration in fpga is not so difficult and the required hardware for it is always implemented at no extra cost (routing matrix). I would like to use routing matrix as an active system element rather than as a one-time-used element. 5 - Other unknow issues! Please let me know what you think. Best Regards. Masoud Naderi. "Steve Casselman" <sc@vcc.com> wrote in message news:<KwRe9.109$C07.12776813@newssvr21.news.prodigy.com>... > Look at > http://support.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Military+%2 > 6+Aerospace > http://support.xilinx.com/xapp/xapp216.pdf > > Steve > > > > > "Masoud Naderi" <naderimisc@yahoo.com> wrote in message > news:2ba3bbea.0209080545.464b6185@posting.google.com... > > Dear sir, > > I study paper abstracts at MAPLD conference, but nothing on > > fault-tolerant desing in NORMAL enviroment. can you give me other > > online resources? > > Best Regards. > > Masoud Naderi > > > > Ray Andraka <ray@andraka.com> wrote in message > news:<3D7A8CE7.BAFA7BEB@andraka.com>... > > > I highly recommend attending the MAPLD (Military Applications of > > > Programmable Logic Devices) conference in Laurel Maryland next week for > > > fault tolerance with FPGAs. Probably the first thing you need to do is > > > identify what faults are to be detected and what measures are to be > > > taken when a fault is detected. There are a number of fault mechanisms > > > that need to be considered, and a lot depends on your environment, the > > > device and the application. > > > > > > Masoud Naderi wrote: > > > > > > > Hi, > > > > I am looking for PRACTICAL fault-tolerant fpga design methodes. Can > > > > you help me in this regards? > > > > I am familiar with traditional fault-tolerant design methodes, but > > > > specificly I am looking for fpga fault tolerant design methodes. > > > > > > > > Best Regards. > > > > Masoud Naderi > > > > > > -- > > > --Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com > > > > > > "They that give up essential liberty to obtain a little > > > temporary safety deserve neither liberty nor safety." > > > -Benjamin Franklin, 1759Article: 46916
Troy Schultz wrote: > > Yes that was the WinCUPL package, I removed it from my system so > unfortunately I can't tell you what version it was. I can however tell > you that is does not behave well and you can not always trust what the > fitter tells you. We have hundreds of designs here compiled in CUPL. We set it up as a command line compiler, from a Programmer Editor - so it's very similar in flow to ASM/C embedded development. CUPL is similar to, but not the same as ABEL. It is somewhat like 'structured assembler' : lowish level, but precise. CUPL has conditional compile controls, good State/Table/optimise, and very good floorplanning controls. It is not strong at maths,as the 'higher languages' but does have very good correlation to PLD resource. VHDL is more a 'design request' language, in that what you get out is highly vendor/synthesis dependant, but it can be good for larger designs. CUPL can create HW test vectors, and when used with a good programmer, you can pull the silicon inside the design loop. It's a bit like the old ASM vs C vs C++ vs Java chestnut : sometimes it is good to see the trees, sometimes you don't need to. > > With WinCUPL you will be programming in an older language called ABELL, > and although well suited for PLDs, you have more options available with > the Xilinx software, you can still use ABEL, but also have Verilog and > VHDL. There is a bit of a learning curve, but VHDL is a good choice for > the CPLDs, it also makes code reuse much easier for future projects. > I can't say that the Xilinx software is perfect, but it worked much > better for me. I think it also makes sense to stick with one of the > largest makers of programmable logic such at Xilinx. Unless you happened to be buying 22V10's when they pulled the plug !:) ( the downside of being fabless, is trailing technology sting ) Xilinx also have no SPLDs - Atmel have very good power/price points for SPLD. <snip> > > As for the logic doubling, I had done my design with a 36 macrocell > Atmel part and replaced it with a 72 macrocell Xilinx part. The Xilinx > part came in at US$2.40 each, half of the price of the Atmel part. Marshall currently show the ATF1502 from $1.07, and the ATF1504 from $2.20 ? They also show : 5V XC9572-15PC44I is $4.34 XC9536-15PC44C $3.13 3.3V XC9572XL-10VQ44C is $2.09 XC9536XL-10PC44C $1.08 1.8V XC2C32-6PC44 $1.54 1.8V XC2C64-7PC44 $3.68 All pretty much on the industry price/performance curves... We like the ATF150xASL devices, because their sub mA static Icc allow smaller SMD regulators, and 5V devices are not in the EOL/NFND price-bin. ( compare the 9572's above ) -jgArticle: 46917
Noddy wrote: > > > No sorry. Most of my references are walking around. John Treichler has > > written a book or two. You can search a bit on the web. But I have not > > read it, but I can't imagine it is not good. It also helps to work with > > a bunch of other guy (or gals) who are learning the stuff too. I > > learned a lot from our group discussions. > > Thanks for the help... unfortunately, have no money to buy books , and I > think I am the only person doing this in the nearest 1000 kms! Searching the > web has yielded not many, if any, results. > > Thanks anyway Yes, DSP is not easy to learn without taking a class or two and buying books. There are a few sites on the web, perhaps you should try posting to comp.dsp. I am sure I have seen similar questions there about web education resources. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46918
One thing to note about PCI's clock is that, in theory, for 33
MHz PCI (But not for 66 MHz PCI.), it can be stopped at any time, and
can be anywhere between 0 MHz to 33MHz. (i.e., Frequency like 25 MHz is
allowed.)
That means if you have a device like a DRAM chip that requires constant
refreshing attached to your FPGA, you will need a separate clock source
on the PCI card to do DRAM refreshing.
However, in practice, almost no motherboards actually stop the PCI clock
I am told, so if you don't care about obeying the specification, you can
take a risk and use the PCI clock for whatever purposes, but let's say
if you are using PCI's clock for DRAM refreshing, I will definitely use
an on-board clock oscillator.
The PCI state machine should be clocked with PCI's clock, and I
don't see any advantage of using the doubled clock for the PCI interface
because it will probably make your PCI interface more complicated, but
for the backend logic, it can be clocked with any frequency as long as
you pass the data through two clock domains correctly.
Another thing to comment about is that, why not use a newer FPGA
like Spartan-II, which still supports 5V PCI rather than XC4000XL?
Spartan-II is newer, has more features, and probably is cheaper than
XC4000XL per LUT.
I used Insight Electronics Spartan-II PCI Development Kit a while ago
for my own PCI IP core project, and the Spartan-II PCI board worked fine
when I tested it with my PCI IP core.
The kit itself costs only about $250.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 46919
One more thing I forgot to mention.
If you are designing your own PCB, I still recommend that you use the
standard LogiCORE PCI pin out rather than your own.
If you are already planning to use LogiCORE PCI, the pin out issue
shouldn't be a problem, but even if you are not using LogiCORE PCI, I
still recommend the using the same one because you should have less PCB
related problems with it rather than picking your own.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 46920
I recommend not bothering with a waveform simulator (Quartus
II's built-in simulator), and stick with ModelSim-Altera.
That's because you can simulate larger designs effectively with ModelSim
than a waveform simulator, although you need to learn how to write
testbench code to simulate on ModelSim.
A book called Writing Testbenches: Functional Verification of HDL Models
(ISBN: 0-7923-776-4) gives you some hints on writing testbench code, but
it is not a perfect book.
Most of your simulation should be done in RTL because the simulation
speed is fast, and gate and post P&R simulation should be done when you
are ready to fire up the chip.
Even if your design works fine in RTL, you still have to do gate and
post P&R simulation to make sure the synthesis tool correctly
synthesized your design because I have seen one synthesis tool (WebPACK
ISE 3.3's XST) not correctly synthesizing my design, and have wasted two
and a half weeks troubleshooting . . .
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Prashant wrote:
>
> Hi,
>
> I'm trying to develop a design and prototype on the A15E board from
> Altera. This is the design flow I plan to follow.
>
> 1. Write RTL.
> 2. Synthesize RTL in Quartus 2.
> 3. Simulate the design using Quartus 2 simulator.
> 4. After the simulation looks correct, program the device on the
> board.
>
> I have seen a lot of people recommend Modelsim for simulations and
> Leonardo/Synplicity for synthesis. I understand the reasons for using
> these tools.
>
> But, instead if I followed the route of synthesis, place & route and
> simulation in Quartus 2, would my design work in the FPGA on the board
> ? I believe it should. Is there anything I should be careful about ?
>
> Do let me know.
>
> Thanks,
> Prashant
Article: 46921"Kevin Brace" <kevinbraceusenet.4killspam@killspam4.hotmail.com> wrote in message news:alotj8$sjk$2@newsreader.mailgate.org... > One more thing I forgot to mention. > If you are designing your own PCB, I still recommend that you use the > standard LogiCORE PCI pin out rather than your own. > If you are already planning to use LogiCORE PCI, the pin out issue > shouldn't be a problem, but even if you are not using LogiCORE PCI, I > still recommend the using the same one because you should have less PCB > related problems with it rather than picking your own. Not to mention less internal timing problems... AustinArticle: 46922
Two problems with scan are: If you have a design with multiple clocks, it's hard to keep them phased so that data can shift through the scan chain reliably. Other things making it hard are gated clocks, and flops that clock on the negative edge as well as the positive edge. A design that is strictly synchronous avoids these problems. If you have an internal tri-state bus, as data shifts through the scan chain, the bus might be momentarily be turned off (bad) or multiple drivers turned on (worse.) A way to avoid these problems is to not have tri-state busses at all. But tell me, why would anyone implement scan in an FPGA? Scan is usually used at wafer probe, and presumably Xilinx tests them using their own test configuration at wafer probe. -Stan "hristo" <hristostev@yahoo.com> wrote in message news:b0ab35d4.0209070712.a1013b9@posting.google.com... > <<The design is strictly synchronous with positive edge clocking and > no internal tri-state buffers; therefore scan insertion is easily > feasible.>> > i took that fron xilinx code data sheet > can someone explain me what it means by scan insertion is easily > feasible? > and how this is linked with the TBUF use > > thanksArticle: 46923
Hi, "Frank Andreas de Groot" <nospam@nospam.com> wrote:. > Has anyone experience with C++ to Verilog/VHDL convertors? A little bit, I used some during study. > I thought that as a C++ programmer and a total FPGA newbie with just a > minimum of > digital design experience, this avenue would be very interesting, especially > because > I seek to implement a medium-complex software algorithm into a FPGA, and > this algorithm will be subject to gradual refinement. Two points: 1. It is possible to use C/C++ to describe HW using a few additional libraryelements. 2. It is _impossible_ to use C/C++ to describe HW without thinking in HW! You should first learn about clock and parallel processes in HW, before you should start using C/C++ for ASICdesign [1]. If you allready seen some structural digital cirquits, I see no problem without solution *g*. I used cynaps, basicaly a library introducing time, clock, bitvector and so on in C/C++. The company also provides you a tool to use very vhdl/verilog close terms to desrcibe HW. The Code is then compiled by e.g. gcc to get a cycleaccurate simulation and synthesised to a structural verilog-code. I think the main effort of cynapps is not to help you converting C into HW but to help HW-designer to integrate their ideas in surounding C/C++ Code. Even if the company may try do tell you the other way ;-). > 1) Price > 2) Capability ( in terms of supported C/C++) > 3) Capability ( in terms of what it can produce) > 4) Efficiency in using the FPGA resources. 1. Don't know 2. Forget about supported C/C++, you have to think the other way. 3. Should afford all you can imagine with verilog/VHDL 4. Very depending on your synthesistool bye Thomas [1] ASIC means cellbased or fpgabased or similar HW-design.Article: 46924
I have been using Quartus II design flow as you described. It works fine. If you want just the RTL simulation set Processing->Simulator settings->Functional simulation. Actually, it's not "true" RTL simulation - it simulates the synthesized output, but works much faster than timing simulation. I had no major troubles so far, but haven't tried very large designs. I work with Nios processor and simulate only the peripherals. For simulation, you don't have to compile the design - just run check&synthesize. Works faster after changing source code. I have also had some problems with Modelsim speed - seems to work quite slow for designs with lots of signals... and the custom and trial versions are additionally slowed down on purpose, just to force you buy the full licensed version... Matjaz "Prashant" <prashantj@usa.net> wrote in message news:ea62e09.0209110814.2178ee93@posting.google.com... > Hi, > > I'm trying to develop a design and prototype on the A15E board from > Altera. This is the design flow I plan to follow. > > 1. Write RTL. > 2. Synthesize RTL in Quartus 2. > 3. Simulate the design using Quartus 2 simulator. > 4. After the simulation looks correct, program the device on the > board. > > I have seen a lot of people recommend Modelsim for simulations and > Leonardo/Synplicity for synthesis. I understand the reasons for using > these tools. > > But, instead if I followed the route of synthesis, place & route and > simulation in Quartus 2, would my design work in the FPGA on the board > ? I believe it should. Is there anything I should be careful about ? > > Do let me know. > > Thanks, > Prashant
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