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Messages from 47150

Article: 47150
Subject: xilinx jtag chain question
From: "douglas" <do@vcom.com>
Date: Wed, 18 Sep 2002 22:03:42 -0600
Links: << >>  << T >>  << A >>
Hello,

I have a question regarding JTAG ...

I have 2 Virtex II devices in a JTAG chain. The chain is configured with TDI
of the first device going to TDO of the second device. TMS and TCK go to
both devices in parallel. I am using the 4.2WP3.x version of IMPACT that I
received with the latest WebPack (downloaded yesterday).

I can successfully configure the first device in the chain. When I do this,
its current consumption is about 700 mA. The problem is that if I configure
the second device then the first device stops working and its current
consumption drops to about 70 mA. It does not matter what the bitfile for
the second one contains. I even made a very basic bitfile which had one
input pin and one output pin, neither of which connect to anything, and
tried to load it. There was no difference.

I can successfully check the Device ID as well as perform IDCODE looping on
the second FPGA without affecting the first. However, if I try programming
it, then the first one quits.

Any ideas?

Thanks,

Doug



Article: 47151
Subject: Re: Feasibility of 100 tap adaptive FIR design on FPGA
From: dhan@ecel.ufl.edu (Dongho)
Date: 18 Sep 2002 21:39:58 -0700
Links: << >>  << T >>  << A >>
Actually I'm trying to implement LMS FIR filter with 100 input
channels.
So there will be 100 adaptive FIR filters(with 10 taps) and
adder(which will sum the 100 FIR output and subtract the desired input
from there).
And I need to update the weights(coef) of each 100 FIR filter.
sampling rate : 10Hz(100ms) so I need to update weights within 100ms.
precision : input(16bits), coefficient(24bits)

thanks

Ray Andraka <ray@andraka.com> wrote in message news:<3D88F8FE.C559AC67@andraka.com>...
> You don't mention the required performance.  It makes a huge difference.
> Particularly, you need to state the sample rate as well as the
> coefficient update rate.  It would also help to know the precision (bits)
> of the inputs and coefficients.  There are ways to do this, subject to
> certain restrictions.  Let's see what your requirements are first.
> 
> Dongho wrote:
> 
> > Hi,
> >
> >    I'd like to implement adaptive FIR filter with 100 tap in FPGA.
> >    To implement this, I need 100 multiplier to multiply weight.
> >    How to measure the area(or gate?) to measure this filter so that I
> > can find appropriate chip?
> > Thanks in advance for your response.
> >
> > -Regards
> >
> > dongho
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

Article: 47152
(removed)


Article: 47153
Subject: Re: C\C++ to VHDL Converter
From: "Sameer D. Sahasrabuddhe" <sameerds@it.iitb.ac.in>
Date: Thu, 19 Sep 2002 11:19:01 +0500
Links: << >>  << T >>  << A >>
On Thu, 19 Sep 2002 00:09:23 +0000, mike wrote:

> I can't claim to be an expert, but what I think you want to do isn't
> going to work.  You can't take any arbitrary C/C++ program and convert it
> into VHDL code that will run on an FPGA.

Check out Handel-C ... which can convert most ANSI C programs into
VHDL/EDIF suitable for FPGA's. They also have some great extensions to the
C language that are useful in hardware design.

http://www.celoxica.com/home.htm

Sameer.
-- 
   MTech Student,
   Reconfigurable Computing Lab,
   KReSIT, IIT-Bombay.

----------------------------------------------------------------------
Your supervisor is thinking about you.


Article: 47154
Subject: VHDL : Lookup Table
From: Bruce <bruce@bytes.co.za>
Date: Thu, 19 Sep 2002 00:02:26 -0700
Links: << >>  << T >>  << A >>
I am a newcomer to VHDL and I need to design an MP3 decoder. Can anyone tell me what would be the best way to implement the really large lookup tables I need for the nonlinear calculations?

A second problem I have is that I need to read information as a bitstream for simulating my VHDL code, but I need to read a variable number of bits depending where I am in the code? Can anyone tell me a neat way to do this?

Please reply to my email address 

Thanks in advance
Regards,
Bruce

Article: 47155
Subject: Re: using CPLD's inverter in oscillator circuit
From: Marcin E. Hamerla <mehamerla@pro.onet.pl>
Date: Thu, 19 Sep 2002 10:01:16 +0200
Links: << >>  << T >>  << A >>
Peter Alfke napisal(a):

>Investigate it well, for people have been "burnt".

A friend of mine used spare gate of Altera 7128 to built an
oscillator. Everything worked Ok up to next purchase of crystals. Some
Altera's stoped working after shipping to client. I helped him to
investigate the problem and I found that there was about 10V sine
signal amplitude on the inverter input.

>I would go for a canned oscillator package. Look at Maxim's ( formerly
>Dallas) ultra-accurate oscillator.
>
>> I'm going to use a Xilinx CoolRunner XPLA3, and am planning on making
>> an oscillator circuit do drive the clock. The circuit is a basic one
>> I've found for a 32.768kHz signal and consists of the crystal, two
>> resistors, two capacitors, and an inverter.
>> I am aiming for a low-power, low-cost design, and it seems that
>> external inverters cost around 50 cents. Would it be okay to use one
>> of the CPLD's inverters? I know that for my oscillator circuit the
>> inverter must be unbuffered (ie one inverter in the package instead of
>> the standard three) to avoid distortion. Would I have too much
>> distortion using the CPLD? If so, is anyone aware of any alternate
>> solutions (aside from a pre-built oscillator circuit.. these seem to
>> require too much power)? Thanks a lot!

-- 
Pozdrowienia, Marcin E. Hamerla

"Nienawidze turystow."

Article: 47156
Subject: XST ROM Synthesis
From: kolja@bnl.gov (Kolja Sulimma)
Date: 19 Sep 2002 01:41:19 -0700
Links: << >>  << T >>  << A >>
I was wondering wether I could infer Block-ROMs in XST (Foundation
4.1). So I wrote up a character ROM in VHDL that looks similar to the
Block-RAM template. (See below)

I was not surprised, when XST did not infer the Block-ROM, but I was,
when I saw the synthesis results: 3500 4-LUTs for a 4-kBIT ROM.
Synthesis is set to optimize for area with high effort. 

The entity is a 12-Input function. The straight forward implementation
of an arbitrary 12-Input function would use 256 4-LUTs followed by a
256-to-1 MUX using at most 255 4-LUTs.

But this is not an arbitrary function, it is a character ROM with tons
of implications between internal nodes, so the result should be much
smaller.

So, what is going wrong that the logic gets 7 times larger than the
worst case estimate?

Kolja Sulimma

--------------------------------------------------------------------


architecture arrayrom of characterrom is
signal read_a : std_logic_vector(11 downto 0); 
type rom_type is array (0 to 64*8*8-1) of std_logic; 
constant ROM : rom_type := (
		--0x20	' '
	'0','0','0','0','0','0','0','0',
[...]
	'1','1','1','1','1','1','1','1'
	); 
begin
  process (clk) 
  begin 
 	if rising_edge(clk) then  
 		read_a <= a; 
 	end if; 
  end process; 
	pixel <= ROM(conv_integer(read_a));
end arrayrom;

Article: 47157
Subject: Re: GCLK pin used like an standard input
From: rrr@ieee.org (Rajeev)
Date: 19 Sep 2002 05:48:09 -0700
Links: << >>  << T >>  << A >>
Laurent,

As I understand it, 
(1) IBUFG does not drive a global clock net (that's BUFG's job)
(2) IBUFG output can drive non-clock inputs
so you can use IBUFG for your enable signal, as I did with an eval
board where the reset button was wired to a GCLK pin.  You get a
warning message (IBUFG driving non-clock inputs) which may be ignored.

Hope this helps,
-rajeev-
------------------
Laurent Gauch <laurent.gauch@amontec.com> wrote in message news:<3D8825C8.90009@amontec.com>...
> Hi all,
> 
> I am designing on XCV600 and I have to use an GCLK input as a standard 
> input.
> 
> On VCV600 we have 4 IBUFG
> My design uses 3 GCLK pins for 3 different clocks, these 3 GCLK pins are 
> directly connected to 3 IBUFG.
> I divide one of my 3 Clocks by two via a Flip-flop (I cannot use DLL 
> part because I have to produce an ASIC of this design and the customer 
> don't want specific logic). The result of this division is connected to 
> a IBUFG too.
> Now my problem is to connect and to use my last GCLK pin like a standard 
> input.
> Is There a way to use a GCLK pin without passing through an IBUFG. If 
> yes, which constraint will do that for me.

<...>

Article: 47158
Subject: Re: ISE 5.1 Linux?
From: Petter Gustad <newsmailcomp3@gustad.com>
Date: 19 Sep 2002 15:00:54 +0200
Links: << >>  << T >>  << A >>
Petter Gustad <newsmailcomp1@gustad.com> writes:

> Is ISE 5.1 a native Linux port or does it run under Wine like 4.2?

http://www.xilinx.com/ise/products/alliance_config.htm#platform

Says Red Hat 7.2 and nothing about Wine, does that mean a native Linux
port? 

Petter
-- 
________________________________________________________________________
Petter Gustad         8'h2B | ~8'h2B        http://www.gustad.com/petter

Article: 47159
Subject: What software package
From: Simon Gornall <simon@gornall.net>
Date: Thu, 19 Sep 2002 14:07:11 +0000 (UTC)
Links: << >>  << T >>  << A >>
Up until now I've been using the Webpack software available free from 
Xilinx. I'm actually pretty happy with it - the sole problem is that I 
have to reboot into Windows to run it ... this is a major reason for me 
choosing to "do something else" :-)

I noticed that ISE 5.1 is available under linux (hurrah!) at last, and 
was wondering:

  o If ISE 5.1 is available under Linux, can we expect to see the
    webpack also available for linux ? Please ? Pretty please ? Oh
    go on :-)

  o Is the major difference between Alliance & BaseX the time-limited
    licence, or are there other drawbacks? 450/year is (just!) about
    in my price range (I can think of it as 9/week :-). Coughing up
    1000 is not on  - I'll put up with windows instead of paying that
    much... Presumably you'd have to pay maintenance to get the updates
    on the s/w anyway, even if you paid for Alliance ?

  o None of the ISE products seem to support the Virtex-2 line, just
    Virtex (or does 'Virtex Series' include Virtex-2 ?). This isn't a
    problem atm, I'm using an Spartan2E/300 board, but you never know.

In case it's not obvious, this is for hobbyist use - I'm not trying to
get professional-level service (although the support may come in handy, 
I've always been impressed with the Xilinx web-support that you get for 
free anyway!)

Experiences, reasoning, advice all gratefully accepted.

Simon


Article: 47160
Subject: slightly OT: does anyone know free parallel flash programmer schematics?
From: t.t.withaar@student.etc.etc (Thijs)
Date: Thu, 19 Sep 2002 15:52:34 GMT
Links: << >>  << T >>  << A >>
Hi,

i need to program a flash eeprom device
it's a 256kb Flash chip.

I can't find any decent schematic on the internet
do you know one ?

I'd prefer one with a pcb layout.

Greetz,

Thijs

Article: 47161
Subject: Re: Xilinx ISE5.1 and Windows NT
From: kolja@bnl.gov (Kolja Sulimma)
Date: 19 Sep 2002 08:59:21 -0700
Links: << >>  << T >>  << A >>
Kamal Patel <kamal.patel@xilinx.com> wrote in message news:<3D88F370.6080106@xilinx.com>...
> Giuseppe,
> 
> This is correct.  Windows XP and Windows 2000 will
> be the only supported Microsoft operating systems
> for 5.1i, although 5.1i should still install and
> run fine on Windows NT.

In multi user environments not even the versions that officially
support windows NT install and run fine under Windows NT.

Do you happen to know whether Version 5.1 finally sets all file
permissions correctly under windows XP? (Documented bug at least since
F1.5)

And Hey: Do you think I can install it into directories with unusual
names like "C:\Program Files\Xilinx\"?

My Sysop everytime gets angry at me when I tell him that I need extra
permissions to install it somewhere else.

Kolja Sulimma

Article: 47162
Subject: Re: GCLK pin used like an standard input
From: Laurent Gauch <laurent.gauch@amontec.com>
Date: Thu, 19 Sep 2002 18:11:11 +0200
Links: << >>  << T >>  << A >>
Rajeev,

(1) Fro me , the IBUFG drives the global clock. These global clock may 
come from an internal FPGA signal or from the 4 specific GCLK pads (for 
XCV). But a IBUFG is dedicated for each GCLK pads, also each GCLK pads 
can ONLY be routed to the IBUFG.

Maybe : if 3 GCLK pads are used as clock inputs, in this case 3 
corresponding IBUFGs are used. IF I use the last IBUFG for an internal 
clock source, the Reset signal (or other asynchronous signal) on the 
corresponding last GCLK pad can not be routed!

Is that true?

Laurent Gauch, Amontec



Rajeev wrote:

> Laurent,
> 
> As I understand it, 
> (1) IBUFG does not drive a global clock net (that's BUFG's job)
> (2) IBUFG output can drive non-clock inputs
> so you can use IBUFG for your enable signal, as I did with an eval
> board where the reset button was wired to a GCLK pin.  You get a
> warning message (IBUFG driving non-clock inputs) which may be ignored.
> 
> Hope this helps,
> -rajeev-
> ------------------
> Laurent Gauch <laurent.gauch@amontec.com> wrote in message news:<3D8825C8.90009@amontec.com>...
> 
>>Hi all,
>>
>>I am designing on XCV600 and I have to use an GCLK input as a standard 
>>input.
>>
>>On VCV600 we have 4 IBUFG
>>My design uses 3 GCLK pins for 3 different clocks, these 3 GCLK pins are 
>>directly connected to 3 IBUFG.
>>I divide one of my 3 Clocks by two via a Flip-flop (I cannot use DLL 
>>part because I have to produce an ASIC of this design and the customer 
>>don't want specific logic). The result of this division is connected to 
>>a IBUFG too.
>>Now my problem is to connect and to use my last GCLK pin like a standard 
>>input.
>>Is There a way to use a GCLK pin without passing through an IBUFG. If 
>>yes, which constraint will do that for me.
>>
> 
> <...>
> 


Article: 47163
Subject: Re: ISE 5.1 Linux?
From: Kamal Patel <kamal.patel@xilinx.com>
Date: Thu, 19 Sep 2002 10:25:46 -0600
Links: << >>  << T >>  << A >>
Petter,

Wine still needs to be used for 5.1i.
I'll have this page changed to be more
clear about that.

Regards,
Kamal Patel
Xilinx Apps

Petter Gustad wrote:
> Petter Gustad <newsmailcomp1@gustad.com> writes:
> 
> 
>>Is ISE 5.1 a native Linux port or does it run under Wine like 4.2?
> 
> 
> http://www.xilinx.com/ise/products/alliance_config.htm#platform
> 
> Says Red Hat 7.2 and nothing about Wine, does that mean a native Linux
> port? 
> 
> Petter


Article: 47164
Subject: Re: xilinx jtag chain question
From: "douglas" <do@vcom.com>
Date: Thu, 19 Sep 2002 11:04:22 -0600
Links: << >>  << T >>  << A >>
Hello,

Sorry.  Stupid typo.  I meant to say that TDO of the first goes to TDI of
the second.

I still have the problem.

Any ideas?

Thanks,

Doug


"douglas" <do@vcom.com> wrote in message
news:uoiitr6a5eih05@corp.supernews.com...
> Hello,
>
> I have a question regarding JTAG ...
>
> I have 2 Virtex II devices in a JTAG chain. The chain is configured with
TDI
> of the first device going to TDO of the second device. TMS and TCK go to
> both devices in parallel. I am using the 4.2WP3.x version of IMPACT that I
> received with the latest WebPack (downloaded yesterday).
>
> I can successfully configure the first device in the chain. When I do
this,
> its current consumption is about 700 mA. The problem is that if I
configure
> the second device then the first device stops working and its current
> consumption drops to about 70 mA. It does not matter what the bitfile for
> the second one contains. I even made a very basic bitfile which had one
> input pin and one output pin, neither of which connect to anything, and
> tried to load it. There was no difference.
>
> I can successfully check the Device ID as well as perform IDCODE looping
on
> the second FPGA without affecting the first. However, if I try programming
> it, then the first one quits.
>
> Any ideas?
>
> Thanks,
>
> Doug
>
>



Article: 47165
Subject: Re: VHDL : Lookup Table
From: rrr@ieee.org (Rajeev)
Date: 19 Sep 2002 10:48:45 -0700
Links: << >>  << T >>  << A >>
Bruce <bruce@bytes.co.za> wrote in message news:<ee790ca.-1@WebX.sUN8CHnE>...
> I am a newcomer to VHDL and I need to design an MP3 decoder. Can anyone tell me what would be the best way to implement the really large lookup tables I need for the nonlinear calculations?

I use Xilinx LogiCore ROM with a .coe file.  The bulk of the COE file is the
initialization vector, I do cut-and-paste from Excel.

<...>

-rajeev-

Article: 47166
Subject: Apex unused pins voluntarily assigned by Quartus?
From: "Mikhail Matusov" <matusov@ANNTIsquarepegSPPAMM.ca>
Date: Thu, 19 Sep 2002 18:46:27 GMT
Links: << >>  << T >>  << A >>
Hi all,

I am looking into a report file generated by Quartus for an Apex design and
I see several unused in the design pins to be called GND+ and GND*. I asked
the tools to tri-state all the unused pins and it worked for 95% of them but
there are these 7 pins assigned to GND+ and 2 to GND*. Three of them are
dedicated Fast pins, the forth Fast pin is actually used in the design.
Others are dedicated clock pins such as CLK4p, CLKLK_FB1p, etc. So, does
anyone know why this is happening and what the hell GND+ and GND* is
supposed to mean? I can't find this explained anywhere...

Thanks,
/Mikhail



Article: 47167
Subject: Re: Apex unused pins voluntarily assigned by Quartus?
From: Rene Tschaggelar <tschaggelar@dplanet.ch>
Date: Thu, 19 Sep 2002 20:53:50 +0200
Links: << >>  << T >>  << A >>
I had a discussion about exactly that subject today.
 From MaxPlus2 :
^ means dedicated pin
+ means reserved configuration pin, which is tristated
   during user mode
* means reserved configuration pin, which drives out in
   user mode

I guess it means you have to connect them to GND.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Mikhail Matusov wrote:
> Hi all,
> 
> I am looking into a report file generated by Quartus for an Apex design and
> I see several unused in the design pins to be called GND+ and GND*. I asked
> the tools to tri-state all the unused pins and it worked for 95% of them but
> there are these 7 pins assigned to GND+ and 2 to GND*. Three of them are
> dedicated Fast pins, the forth Fast pin is actually used in the design.
> Others are dedicated clock pins such as CLK4p, CLKLK_FB1p, etc. So, does
> anyone know why this is happening and what the hell GND+ and GND* is
> supposed to mean? I can't find this explained anywhere...


Article: 47168
Subject: Re: Apex unused pins voluntarily assigned by Quartus?
From: "Mikhail Matusov" <matusov@ANNTIsquarepegSPPAMM.ca>
Date: Thu, 19 Sep 2002 19:17:23 GMT
Links: << >>  << T >>  << A >>
Thanks for your quick reply, Rene!

However, pins marked with GND+ are not configuration pins in my case. They
are either dedicated Fast I/O or clock related pins. The one that bothers me
the most is actually a Fast I/O. I have a customer who has this pin
connected to something on his board and the board doesn't work. So, I need
to know whether I am driving it by any chance... The design is proven to
work on our own card and on other customer's card, so I know it should
work...

/Mikhail





"Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message
news:3D8A1D3E.9010404@dplanet.ch...
> I had a discussion about exactly that subject today.
>  From MaxPlus2 :
> ^ means dedicated pin
> + means reserved configuration pin, which is tristated
>    during user mode
> * means reserved configuration pin, which drives out in
>    user mode
>
> I guess it means you have to connect them to GND.
>
> Rene
> --
> Ing.Buero R.Tschaggelar - http://www.ibrtses.com
> & commercial newsgroups - http://www.talkto.net
>
> Mikhail Matusov wrote:
> > Hi all,
> >
> > I am looking into a report file generated by Quartus for an Apex design
and
> > I see several unused in the design pins to be called GND+ and GND*. I
asked
> > the tools to tri-state all the unused pins and it worked for 95% of them
but
> > there are these 7 pins assigned to GND+ and 2 to GND*. Three of them are
> > dedicated Fast pins, the forth Fast pin is actually used in the design.
> > Others are dedicated clock pins such as CLK4p, CLKLK_FB1p, etc. So, does
> > anyone know why this is happening and what the hell GND+ and GND* is
> > supposed to mean? I can't find this explained anywhere...
>



Article: 47169
Subject: Modelsim XE question
From: at@cloanto.com (tony)
Date: 19 Sep 2002 12:36:13 -0700
Links: << >>  << T >>  << A >>
I have just downloaded the Modelsim XE simulator form the Xilinx
site, and I am trying to understand how it works.

I would like to instantiate a CLKDLL and I have found out that 
the simprims_ver library has a part called X_CLKDLL and I used 
that one although I am at loss to explain the leading X_. The 
instantiation looks like this:

X_CLKDLL clkdll1( .CLK0(), 
                  .CLK90(), 
                  .CLK180( clk_90), 
                  .CLK270(),
                  .CLK2X( clk_out ),
                  .CLKDV(),
                  .LOCKED(),
                  .CLKIN( clk ),
                  .CLKFB( clk ),
                  .RST( rst ) );

Now what happens is that when I compile the design (the file plus the 
testbench) everything works smoothly, but when I load the design for 
simulation, the X_CLKDLL instantiation generates an error, and won't 
continue. Here is the output

# Loading work.test_counter
# Loading work.counter
# ERROR: C:/Projects/Modelsim/verilog/counter/counter.v(37): Instantiation
  of 'X_CLKDLL' failed (design unit not found).
#       Region: /test_counter/dut
#         Searched libraries:
#             work
# Error loading design

Apparently Modelsim is not using the XILINX libaries (which, based on 
what I found on the Xilinx knowledge base, are precompiled in the XE 
simulator).

My first attempt was to add a library path before compiling the source 
code. I did this using the compile dialog box, and clicking on the 
"Default Options..." button. I pointed the directory to 

C:/"Program Files"/Modelsim/xilinx/verilog/simprims_ver

where the X_CLKDLL module is. But even in this case, I had no luck. 
Further search on the internet proved also useless. I am left with the 
question of how to use library part for simulating verilog code with 
Modelsim XE. 

Can anybody help out with this?

Thanks a lot
Tony

Article: 47170
Subject: Re: Has ISE 5.1i shipped?
From: qlyus@yahoo.com (qlyus)
Date: 19 Sep 2002 12:56:53 -0700
Links: << >>  << T >>  << A >>
I do not think it shipped, since there is no flooding of Answers yet,
and no SP-1 released yet.

lyqin@cti.com.cn (Leon Qin) wrote in message news:<23c59085.0209162319.10c85494@posting.google.com>...
> any one knows?

Article: 47171
Subject: Re: C\C++ to VHDL Converter
From: pierrotlafouine@hotmail.com (Pierre Lafrance)
Date: 19 Sep 2002 14:24:06 -0700
Links: << >>  << T >>  << A >>
I currently try to convert a real time software C algorytme I
develloped (Bayer images to RGB) to Handle C, but yet far from
routing.  I do VHDL, C, and C++ fluently, so I was the chosen one to
evaluate Celoxica.

Handle C is a nice language, but is not done to devellope hardware
interface like DDR, or PCI-X interface.

So if you want to interace real hardware, real time, then I recomand
you to code VHDL for these component, even if Celoxica claim they can
do it (but they don't support DDR at all for now).

When data is in the chips, then you can use Handle-C
compiler/component to devellope the algo.  Celoxica can translate
Handle-C to VHDL or to EDIF target.

Celoxica compiler has a Visual Studio feeling, and they made an
amazing job to translate harware concept and terms to software concept
and terms.  You can instantiate dual port ram in block ram in few
lines :

#define DEF_BPP			8
#define DEF_NB_PIXEL_PER_LINE	1024
set clock = "myProcessingClock";

typedef mpram myDualPort
{
   wom unsigned int DEF_BPP wPort[DEF_NB_PIXEL_PER_LINE];// Write only
   rom unsigned int DEF_BPP rPort[DEF_NB_PIXEL_PER_LINE];// Read only 
} DUAL_PORT;

// Dual port RAM instantiation, in block RAM
static DUAL_PORT m_DualPort with { block = 1};


But still, you have to know FPGA architecture, and try to understand
what a pointer to an array of RAM means...

To route the chips, you still need ISE.  So to do a complete project,
you need editor/simulator (Active HDL), Syntesis tool (Synplicity),
router (ISE) and Celoxica.  This is big $$$

Good luck
Pierre

"Sameer D. Sahasrabuddhe" <sameerds@it.iitb.ac.in> wrote in message news:<pan.2002.09.19.06.18.54.446454@it.iitb.ac.in>...
> On Thu, 19 Sep 2002 00:09:23 +0000, mike wrote:
> 
> > I can't claim to be an expert, but what I think you want to do isn't
> > going to work.  You can't take any arbitrary C/C++ program and convert it
> > into VHDL code that will run on an FPGA.
> 
> Check out Handel-C ... which can convert most ANSI C programs into
> VHDL/EDIF suitable for FPGA's. They also have some great extensions to the
> C language that are useful in hardware design.
> 
> http://www.celoxica.com/home.htm
> 
> Sameer.

Article: 47172
Subject: Re: Modelsim XE question
From: Duane Clark <junkmail@junkmail.com>
Date: Thu, 19 Sep 2002 14:40:50 -0700
Links: << >>  << T >>  << A >>
tony wrote:
> I have just downloaded the Modelsim XE simulator form the Xilinx
> site, and I am trying to understand how it works.
> 
> I would like to instantiate a CLKDLL and I have found out that 
> the simprims_ver library has a part called X_CLKDLL and I used 
> that one although I am at loss to explain the leading X_. The 
> instantiation looks like this:

The simprims library is intended for post route simulation, though I 
don't know why Modelsim XE comes with it's own version... whatever.

In any case, wherever you have the Xilinx software installed, there 
should be a library xilinx\vhdl\src\unisims that contains the correct 
libraries to use for your simultation.

-- 
My real email is akamail.com@dclark (or something like that).


Article: 47173
Subject: Altera A+PLUS software
From: russmay@ditmco.com (Russell May)
Date: Thu, 19 Sep 2002 21:42:34 GMT
Links: << >>  << T >>  << A >>
I am interested in documentation or a distribution diskette for
Altera's obsolete A+PLUS EPLD programming software. I have several
designs from about 1987 to 1993 which used it. I can import designs
into MAXPLUS II but I have forgotten some of the terminology and
format for the NETWORK section. If I had some of the documentation or
if I could run the APLUS program, I could clarify meanings in this
section.

I have the program but not the distribution diskette, which is
required to run the APLUS program. If I had or could simulate a
distribution diskette, I could use the help files to find out what I
would like to know.

My documentation and distribution diskette have disappeared over the
years. Apparently the same is true at Altera. Their tech support could
not help.

Russell May


Article: 47174
Subject: Overheat with XCV-600E
From: pierrotlafouine@hotmail.com (Pierre Lafrance)
Date: 19 Sep 2002 14:55:31 -0700
Links: << >>  << T >>  << A >>
Hi all
I respined a product, changing the old Xilinx XV-300 with a XCV-600E.
Of course, I had to change voltage regulator from 2.5 to 1.8 volts,
and few 5 volts CPLD to 3.3v.

The problem is : the XCV-600E overheat, and 1 of the prototype just
died.
I tried to find any hardware signal that would exceed voltage but
couldn't.  Hardware seems to be just fine.  I suspect the chips itself
to overheat.  I just put a heatseak temporarly, but would like to
solve the problem if I can.

Simulation with XPower estimate the chips temperature to be 50C, but I
measure up to 65C.

The disign use 75% of BRAM, and 75% of FF of the XCV-600E.
Clock is 82MHz.

Anybody experienced overheat with 600E ?

Cheers !

Pierre



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