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Static RAM is easy. 32K X 8 - $5 singles. A no brainer. On the other hand if you are writing code in C++ 64MB may not be enough. Simon ================================================================= ludwig@pa.dec.com (Stefan Ludwig) wrote: >Stefan (another one), > >> thanks for the pointer, it is helpful for my understanding. But I don't >> quite understand your remark, >> >> > Synch SRAM was a wonderful addition to Xilinx parts; let's thank >> > Xilinx by using it. >> >> Are you talking about internal SRAM cells (using CLBs)? Or does Xilinx >> provide synch SRAM? -- My original question referred to _external_ >> memory. > >Bob was talking about INTERNAL SRAM in the CLBs. His comments about write >pulses hold also for external SRAM. Sync RAMs (S or D) are much more >convenient than async RAMs. With sync RAMs, you (only) have to >handle the clock signal carefully, whereas with async RAMs, there are the >write pulses, ras/cas and the address lines, which have to be delay matched. > >Regards, > >Stefan Ludwig > >Systems Research Center >Compaq Computer Corporation >130 Lytton Ave >Palo Alto, CA 94301-1044 >USA > >Tel: ++1 650 853 2227 Fax: ++1 650 853 2235 >mailto:ludwig@pa.dec.com http://www.research.digital.com/SRC Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.Article: 11901
In article 1@nnrp1.dejanews.com, sam@palmnet.net writes: > I would like to Use an Atmel configuration EEPROM for my Xilinx Spartan > device in a deliverable product, and maintain the ability to reprogram the > EEPROM after the Xilinx is booted through the use of an onboard > microcontroller and a Compact Flash card that will contain the new MCS file > for the new Xilinx configuration. Has anyone done this before, and if so, are > there any things I need to be wary of? Does anyone have any C-code for a > similar application they could share with me to get me started? Thanks. > > Steve Mitchell Do you mean the Atmel serial EEPROM? Atmel has source code for the program that runs their small EEPROM programming board. The board just uses a few lines in a PC's printer port to program the part (which can be substituted with control lines from your Xilinx or microcontroller) so the code should be adaptable to your needs. -tom ---Article: 11902
Jon: Note 1: Using both edges is an acceptable in synchronous design.... 0. Have Row_Addr presented 1. Edge: Present RAS 2. Next Edge: Present Col_Addr 3. Next Edge: Drop CAS 4. Next Edge: Raise RAS and CAS and capture read data (change column addr) repeat steps 3 and 4 for fast page mode ops. Note 2: the trick is changing CAS from step 3 and 4. But I don't want to solve the whole problem for the teacher :) -- Ed McCauley Bottom Line Technologies Inc. http://www.bltinc.com Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817 Jonathan Bromley wrote: > > In a previous post I wrote: > > > > To all you battle-hardened experts out there, > > and then illustrated my problem with *the wrong example*, sorry. > Just goes to show how confused I was. Getting adequate data hold > after /CAS trailing edge is easy - causality does the job for you. > The problem _is_ important, however, when trying to guarantee > validity of addresses (and write data) before and/or after a > strobe edge. The basic question posed in my post stands; the > example I used to illustrate it was faulty. Apologies. > > Jonathan Bromley > -- > ----------------------------------------------------------------- > Electronics is fun. If you want me to take it seriously, > call and we'll talk consultancy rates. > -----------------------------------------------------------------Article: 11903
Is it possible to program a Xilinx (4000) via an RS-232 channel? If so, how would I go about it? I couldn't see anything about it at Xilinx's web site. thanks, hamish -- Hamish Moffatt, StudIEAust hamish@debian.org, hamish@moffatt.nu Student, computer science & computer systems engineering. 4th year, RMIT. http://hamish.home.ml.org/ (PGP key here) CPOM: [******* ] 73% "Note that in C++, as in life, friendship is not transitive" -- TC++3 manualArticle: 11904
sam@palmnet.net wrote: > > I would like to Use an Atmel configuration EEPROM for my Xilinx Spartan > device in a deliverable product, and maintain the ability to reprogram the > EEPROM after the Xilinx is booted through the use of an onboard > microcontroller and a Compact Flash card that will contain the new MCS file > for the new Xilinx configuration. Has anyone done this before, and if so, are > there any things I need to be wary of? Does anyone have any C-code for a > similar application they could share with me to get me started? Thanks. I don't have any code to share with you, but I would like to warn you not to put the Xilinx in the download path for the EEPROM. If you have any problem in downloading the EEPROM or download a bad file, you will not be able to boot the Xilinx again and therefore won't be able to download a new file to fix the problem. It would be good to be able to download the EEPROM directly from the microcontroller without booting the Xilinx. Just in case you didn't think of that. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 11905
Ed McCauley wrote: > > Jon: > > Note 1: Using both edges is an acceptable in synchronous design.... > > 0. Have Row_Addr presented > 1. Edge: Present RAS > 2. Next Edge: Present Col_Addr > 3. Next Edge: Drop CAS > 4. Next Edge: Raise RAS and CAS and capture read data (change column addr) > > repeat steps 3 and 4 for fast page mode ops. > > Note 2: the trick is changing CAS from step 3 and 4. But I don't want to solve the whole problem for > the teacher :) > > -- > Ed McCauley > Bottom Line Technologies Inc. > http://www.bltinc.com > Specializing Exclusively in Xilinx Design, Development and Training > Voice: (500) 447-FPGA, (908) 996-0817 > FAX: (908) 996-0817 > > Jonathan Bromley wrote: > > > > In a previous post I wrote: > > > > > > To all you battle-hardened experts out there, > > > > and then illustrated my problem with *the wrong example*, sorry. > > Just goes to show how confused I was. Getting adequate data hold > > after /CAS trailing edge is easy - causality does the job for you. > > The problem _is_ important, however, when trying to guarantee > > validity of addresses (and write data) before and/or after a > > strobe edge. The basic question posed in my post stands; the > > example I used to illustrate it was faulty. Apologies. That is a good description of the general timing Ed. When I attempted to design this sort of interface I found that the problem of optimizing the timing was the uncertainty of delay through the Row/Col address mux. So you had to leave enough time to allow the address to change from Row to Col, but not so much that you impacted the access time by delaying the CAS strobe. A six clock access cycle would get you close to optimal, and an 8 clock access cycle gets you there very well if your mux is fast enough. I always wanted to control the mux with the RAS strobe, but I couldn't get enough Row address hold time. With an FPGA it would be even tougher. Johathan, I don't think there are too many special rules to follow that you haven't come across. The fully synchronous design rules cover most everything important. But it is perfectly acceptable to use both edges of the clock to speed up a circuit without using a faster clock. In some earlier posts some people were confusing the concept of asynchronous data and synchronous design. This is an example where the access time can be lowered by using transparent latches for the address. As far as I am concerned this does not violate the principles of synchronous design. And in this case it can save you many nanoseconds in trying to meet the Row address setup time. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 11906
I forgot to mention speed - 12nS . msimon@tefbbs.com wrote: >Static RAM is easy. 32K X 8 - $5 singles. A no brainer. > >On the other hand if you are writing code in C++ 64MB may not be >enough. > >Simon > >================================================================= >ludwig@pa.dec.com (Stefan Ludwig) wrote: > >>Stefan (another one), >> >>> thanks for the pointer, it is helpful for my understanding. But I don't >>> quite understand your remark, >>> >>> > Synch SRAM was a wonderful addition to Xilinx parts; let's thank >>> > Xilinx by using it. >>> >>> Are you talking about internal SRAM cells (using CLBs)? Or does Xilinx >>> provide synch SRAM? -- My original question referred to _external_ >>> memory. >> >>Bob was talking about INTERNAL SRAM in the CLBs. His comments about write >>pulses hold also for external SRAM. Sync RAMs (S or D) are much more >>convenient than async RAMs. With sync RAMs, you (only) have to >>handle the clock signal carefully, whereas with async RAMs, there are the >>write pulses, ras/cas and the address lines, which have to be delay matched. >> >>Regards, >> >>Stefan Ludwig >> >>Systems Research Center >>Compaq Computer Corporation >>130 Lytton Ave >>Palo Alto, CA 94301-1044 >>USA >> >>Tel: ++1 650 853 2227 Fax: ++1 650 853 2235 >>mailto:ludwig@pa.dec.com http://www.research.digital.com/SRC Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.Article: 11907
First of all, when I opened the Floorplanner the first time I was positively surprised, it looked realy nice with it carry chains and all. But after having used it, the only thing that really works for me, it guided placement of a few time critical FF's, and this I can just as well do in the UCF file. The place&route time for my design is between 1.5 and 3 hours depending on the effort level. I suspect that this is alright for a design consuming 80% of a 4062XL running at 32MHz. However, I have often found it annoying that I had to a completly new implementation, whenever i made a small modification on my design. Why couldn't place&route learn from the previous versions and then start the new place&route from the layout it generated then. I know that Xilinx has had a guided layout option for some time now, but whenever I have tried to use it, it results in a "Dr. Watson"-fault of some kind, I don't remember. I realize that it is not a easy problem to solve for Xilinx, especially because I use VHDL/Synthesis to generate the design. This is also why I was very glad to see the new Xilinx 1.5. I had read an article about it in a electronics magazine (I don't remember which) where exactly the problem about reusing unchanged sections of a design was mentioned as an area where xilinx 1.5 was becomming much better. I realize that the article was probably founded by Xilinx, and that was also why I a little suspicious when they promized a 2-3 time speed-up due to their new "A.K.A. speed technology" - I am still waiting 2-3 hours, but the timing analyzer has speeded up. In Xilinx Alliance 1.5 it is possible to both make guided implementation and floorplan guided implementations. I read in the Quick Start Guide for Xilinx Alliance 1.5 that guided implementations was not recommended for synthesis based designs, so I decided to use floorplan guiding instead. The way I use it is: 1 : Make a new design and implement it in the FPGA without any guiding at all. the I make some small modifications on my design. My design consists of approx. 20 entities, and I only make modifications in one of these entites - and we are talking very small modifications. 2: In the florplanner I copy the placement of all cells in the first version, and the removes the entity that has been modified. Then I save a floorplan guide file "design.mfp". 3: I make a new implementation where I use "design.mfp" as Floorplan Guide File. Sometimes this works, and I saves me 1-2 hours, but mostly the Mapping fails with a "Dr. Watson". Has anyone else tried to use the Floorplaner with succes, is the Floorplanner still a beta version, or is it my who are using it wrong ?Article: 11908
This message is in MIME format. Since your mail reader does not understand this format, some or all of this message may not be legible. ------_=_NextPart_001_01BDE2F2.05EA4FDB Content-Type: text/plain; charset="koi8-r" Yes, it is possible, if you use RS-232 Data signal along with additional RS-232 signals (RTS ...) to control Data In, Configuration clock CCLK and PGM signals. In this case you should issue a long sequence of RS-232 signal control commands to program XILINX. Please, take into account, that you can not just send a byte to RS-232 COM port to load it into configuration. An other method, which I prefer - using a small AT89C2051 microprocessor chip, connected with RS-232 Transceiver chip (e.g. ADM203E) and certainly, with XILINX XC4000E chip. Regards, Alex Sherstuk -----Original Message----- From: hamish@moffatt.nu (Hamish Moffatt) [mailto:hamish@moffatt.nu] Posted At: Friday, September 18, 1998 3:57 AM Posted To: comp.arch.fpga Conversation: programming via RS-232 Subject: programming via RS-232 Is it possible to program a Xilinx (4000) via an RS-232 channel? If so, how would I go about it? I couldn't see anything about it at Xilinx's web site. thanks, hamish -- Hamish Moffatt, StudIEAust hamish@debian.org, hamish@moffatt.nu Student, computer science & computer systems engineering. 4th year, RMIT. http://hamish.home.ml.org/ (PGP key here) CPOM: [******* ] 73% "Note that in C++, as in life, friendship is not transitive" -- TC++3 manual ------_=_NextPart_001_01BDE2F2.05EA4FDB Content-Type: text/html; charset="koi8-r" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN"> <HTML> <HEAD> <META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; = charset=3Dkoi8-r"> <META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version = 5.5.2232.0"> <TITLE>Re:programming via RS-232</TITLE> </HEAD> <BODY> <BR> <P><FONT SIZE=3D2>Yes, it is possible, if you use RS-232 Data signal = along with additional RS-232 signals (RTS ...) </FONT> <BR><FONT SIZE=3D2>to control Data In, Configuration clock CCLK and PGM = signals. In this case you should issue</FONT> <BR><FONT SIZE=3D2>a long sequence of RS-232 signal control commands to = program XILINX. Please, take</FONT> <BR><FONT SIZE=3D2>into account, that you can not just send a byte to = RS-232 COM port to load it</FONT> <BR><FONT SIZE=3D2>into configuration.</FONT> </P> <P><FONT SIZE=3D2>An other method, which I prefer - using a small = AT89C2051 microprocessor</FONT> <BR><FONT SIZE=3D2>chip, connected with RS-232 Transceiver chip (e.g. = ADM203E) and certainly,</FONT> <BR><FONT SIZE=3D2>with XILINX XC4000E chip.</FONT> </P> <P><FONT SIZE=3D2>Regards,</FONT> <BR><FONT SIZE=3D2> Alex Sherstuk</FONT> </P> <P><FONT SIZE=3D2>-----Original Message-----</FONT> <BR><FONT SIZE=3D2>From: hamish@moffatt.nu (Hamish Moffatt) [<A = HREF=3D"mailto:hamish@moffatt.nu">mailto:hamish@moffatt.nu</A>]</FONT> <BR><FONT SIZE=3D2>Posted At: Friday, September 18, 1998 3:57 AM</FONT> <BR><FONT SIZE=3D2>Posted To: comp.arch.fpga</FONT> <BR><FONT SIZE=3D2>Conversation: programming via RS-232</FONT> <BR><FONT SIZE=3D2>Subject: programming via RS-232</FONT> </P> <BR> <P><FONT SIZE=3D2>Is it possible to program a Xilinx (4000) via an = RS-232 channel?</FONT> <BR><FONT SIZE=3D2>If so, how would I go about it? I couldn't see = anything about it at</FONT> <BR><FONT SIZE=3D2>Xilinx's web site.</FONT> </P> <BR> <P><FONT SIZE=3D2>thanks,</FONT> <BR><FONT SIZE=3D2>hamish</FONT> <BR><FONT SIZE=3D2>-- </FONT> <BR><FONT SIZE=3D2>Hamish Moffatt, = StudIEAust &n= bsp; hamish@debian.org, hamish@moffatt.nu</FONT> <BR><FONT SIZE=3D2>Student, computer science & computer systems = engineering. 4th year, RMIT.</FONT> <BR><FONT SIZE=3D2><A HREF=3D"http://hamish.home.ml.org/" = TARGET=3D"_blank">http://hamish.home.ml.org/</A> (PGP key = here) &= nbsp; CPOM: [******* ] 73%</FONT> <BR><FONT SIZE=3D2>"Note that in C++, as in life, friendship is = not transitive" -- TC++3 manual</FONT> </P> </BODY> </HTML> ------_=_NextPart_001_01BDE2F2.05EA4FDB--Article: 11909
In article <6tr814$26e$1@nnrp1.dejanews.com>, sam@palmnet.net wrote: > I would like to Use an Atmel configuration EEPROM for my Xilinx Spartan > device in a deliverable product, and maintain the ability to reprogram the > EEPROM after the Xilinx is booted through the use of an onboard > microcontroller and a Compact Flash card that will contain the new MCS file > for the new Xilinx configuration. Has anyone done this before, and if so, are > there any things I need to be wary of? Does anyone have any C-code for a > similar application they could share with me to get me started? Thanks. > > Steve Mitchell > Senior Electrical Engineer > eMERGE Vision Systems > Thanks to Tom Biggs and Rick Collins for your responses. I've found the source code (pretty simple really), and the suggestion of keeping the Xilinx out of the HW path shall be considered. Thanks again. Steve Mitchell -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11910
When synthesising the design below, I receive a warning that input pin pul
is not needed. WHY!!!!
The idea of the design is to make a pulse four clock-cycles wide. Is there a
better way of doing it?
Sincerely
Reza
library ieee;
use ieee.std_logic_1164.all;
entity pulse is
port(pul : in std_logic;
clk, reset : in std_logic;
pulse_4times : out std_logic
);
end pulse;
architecture rtl of pulse is
signal state : integer range 0 to 7;
begin
process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
state <=0;
else
case state is
when 0 => if pul = '1' then
state <= 1;
end if;
pulse_4times <= '0';
when 1 to 6 => pulse_4times <= '0';
state <= state + 1;
when 7 => pulse_4times <= '0';
state <= 0;
end case;
end if;
end if;
end process;
end rtl;
Article: 11911Reza Bohrani wrote: > When synthesising the design below, I receive a warning that input pin pul > is not needed. WHY!!!! > The idea of the design is to make a pulse four clock-cycles wide. Is there a > better way of doing it? > > Sincerely > Reza > > library ieee; > use ieee.std_logic_1164.all; > > entity pulse is > port(pul : in std_logic; > clk, reset : in std_logic; > pulse_4times : out std_logic > ); > end pulse; > > architecture rtl of pulse is > signal state : integer range 0 to 7; > begin > process(clk) > begin > if clk'event and clk = '1' then > if reset = '1' then > state <=0; > else > case state is > when 0 => if pul = '1' then > state <= 1; > end if; > pulse_4times <= '0'; > > when 1 to 6 => pulse_4times <= '0'; > state <= state + 1; > when 7 => pulse_4times <= '0'; > state <= 0; > end case; > end if; > end if; > end process; > end rtl; Well, I don't know if the synthesis tool you use is that clever, but try to apply a '1' on pulse_4times in the "1 to 6" state. Your design actually doesn't do anything and that is why pul isn't needed. StenArticle: 11912
Reza Bohrani wrote: > When synthesising the design below, I receive a warning that input pin pul > is not needed. WHY!!!! [...] This looks pretty good, but I have a question : When does the pulse_4times output go high ? ;-) -- Nicolas MATRINGE DotCom SA Conception électronique 16 rue du Moulin des Bruyères Tel: 00 33 1 46 67 51 00 92400 COURBEVOIE Fax: 00 33 1 46 67 51 01 mail reply : remove one dot from the address (guess which :-)Article: 11913
1)For an XC4000 or Spartan, is there any problem with allowing the programming clock run beyond the min required after the last config bit. ie let it run continuous? 2)The Xilinx app note "FPGA configuration Guidelines" says in one paragraph that it is permissible to add or delete leading ones and at the end is says to not add or delete preamble-leading ones. Now the preamble is a fixed bit pattern of b"0010" so what are the preamble leading ones? Mabey the fill byte at the beginning of the bit stream? I am programming 3 XC4000 fpgas all configured as slaves from a microprocessor serial port. If the number of leading ones (the ones in the fill byte) are indeed important, I should mabey gate the serial port generated clock? Thanks BruceArticle: 11914
For internal (CLB) RAM, use the sync ram. There is virtually no reason to use the Async modes other than in porting an old design. Newer devices (eg Spartan) do not even support the async modes. I rather suspect you were referring to external ram, and that really works out to a big depends. Let's assume SRAM for the time being. If you need to do interleaved reads and writes, you will get more memory bandwidth from asynchronous parts because there is a dead cycle between a read and write cycle using the synchronous parts. If your application requires interleaved reads and writes, you'll waste a lot of clocks in dead time. On the other hand, using synchronous SRAMs provides a considerably higher burst access rate than async parts due to the pipelining achieved. This means that as long as you are not switching between reads and writes all the time, the sync part will do much better (and is easier to interface too). It also costs more. Stefan Rave wrote: > What is the best choice for use with an XC4000XL FPGA: synchronous or > asynchronous SRAM? What's the advantage of synchronous SRAM, anyway? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11915
Talk to Peter Alfke (peter@xilinx.com). He can tell you exactly how to access and use a diode on a xilinx part to measure the junction temperatures. > > I am designing a system using a Xilinx XC4K-XL part, and have a > > few unused pins. I remember that there is some way to measure the junction > > temperature using an unused pin, but I cannot find the reference. I thought > > that Peter Alfke had posted something, but I could not find the post. > > > > Thanks for any replies- > > > > Alan Sieving > > ars@quickware.com > > > > I -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11916
Daniel K Elftmann wrote: > In article <6t73nl$nj0@nntp1.erinet.com>, > "Eric W Braeden" <braeden@erinet.com> wrote: > > >Q: Lets say I were going to use a Xilinx Spartan XCS40 in a design. > > That would probably mean I would use the XC17S40 SPROM. > > How would you keep anyone who want to from cloning your design? > > I don't see any mention of security in the Xilinx pages. How do you > > load your FPGA without exposing your loadable image to hardware > > hackers? > > > >TIA > > > >Eric > > > > > > > > The following is a very good article on protecting your designs. Antifuse is the most secure > technology for protecting your design. > > http://www.actel.com/events/protect_copyright.pdf Actually, using an SRAM device with a battery backup is even more secure. The bitstream is loaded into the device at the factory and maintained with a battery so that there is no external ROM. The configuration leaves no physical traces that can be examined with the lid popped off this way. Of course there is the issue of making sure the power never gets interrupted. BTW, this security issue is the reason Xilinx does not publish the bitstream information. It makes reverse engineering the design from the bitstream hard enough to be unlikely. However, theft of the bitstream as it is loaded into the devices cannot be stopped with the current devices. Sooo, xilinx, how about a bitstream decryption with a non-volatile key built into the FPGA? I suspect the volume of users requiring this is too small to justify the extra fab steps and resulting cost. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11917
Austin Franklin wrote: > You can supply two clocks to the FPGA, one 40 and one 80 that are > guaranteed synchronized by using a PLL...like the one Motorola > makes....that provides a clock/2 output that is skewed within ps of the > 80MHz clock output. Then you don't have to 80ns for the logic that doesn't > need to. > > Austin This is the way I do it (in fact, I use one of the knock-offs of the motorola 88915, I think it is IDT's version). By the time you get the clock inside the FPGA you lose the tight tolerance on the clock to clock skew, so you will have to be careful about how you cross the clock domain boundaries. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11918
In article <N8vM1.101$jD5.488241@typhoon.mbnet.mb.ca> "Bruce" <bruce@bozo.ca> writes:
>1)For an XC4000 or Spartan, is there any problem with allowing the
>programming clock run beyond the min required after the last config bit. ie
>let it run continuous?
The CCLK signal is an input only pin. You can clock it as much as you like.
>2)The Xilinx app note "FPGA configuration Guidelines" says in one paragraph
>that it is permissible to add or delete leading ones and at the end is says
>to not add or delete preamble-leading ones. Now the preamble is a fixed bit
>pattern of b"0010" so what are the preamble leading ones? Mabey the fill
>byte at the beginning of the bit stream?
Yes it is.
The string of '1' bits before the '0010' can be as long as you like.
You can add '1' bits after the 4 bit CRC field at the end of each frame,
and before the '0' at the start of the next frame.
You can add '1' bits at the end of the bit stream.
When you add these '1' bits, you need to adjust the length count field to
account for the extra bits (except for the extra ones at the end, if any).
>I am programming 3 XC4000 fpgas all configured as slaves from a
>microprocessor serial port. If the number of leading ones (the ones in the
>fill byte) are indeed important, I should mabey gate the serial port
>generated clock?
The number of bits sent ('1' or '0') is very important. The FPGAs are
counting rising edges on CCLK, from the time INIT goes high, and will
match it against the 24 bit length count that will follow the '0010' at
the begining of your bitstream. Since the rising edge of INIT is
ASYNCHRONOUS to your system (no, you CAN'T change this), you must NOT
have a free running CCLK.
The correct way to do this is:
Set CCLK LOW
Set Program LOW
Wait a few microseconds
Set Program HIGH
Wait till INIT goes high
Wait at least 6uS
Start generating CCLK Cycles, changing your data on the falling edge,
so that the data has a nice long setup and hold time to the rising edge
of CCLK
>Thanks
>Bruce
Your Welcome.
Philip
Article: 11919To all who answered my original post, either to the NG or directly, THANKYOU for some very interesting stuff. Further ruminations will be welcomed - perhaps by e-mail if you feel the NG has wearied of this thread. As a follow-up, I would be extremely intrigued to hear views from experienced designers and employers about how successfully the universities provide (or not!) the right skill-set in fresh-from-college EE graduates. My institution is far from being an ivory tower and it's very important to us to stay in tune with what the industry wants in our "product" (horrible idea!). Presumably, perspectives on this will be a strong function of geography: not necessarily a good thing in these days of the global market. Once again, thanks for the stimulating input. Jonathan Bromley -- ----------------------------------------------------------------- Electronics is fun. If you want me to take it seriously, call and we'll talk consultancy rates. -----------------------------------------------------------------Article: 11920
Reza Bohrani wrote:
>
> When synthesising the design below, I receive a warning that input pin pul
> is not needed. WHY!!!!
> The idea of the design is to make a pulse four clock-cycles wide. Is there a
> better way of doing it?
>
> Sincerely
> Reza
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity pulse is
> port(pul : in std_logic;
> clk, reset : in std_logic;
> pulse_4times : out std_logic
> );
> end pulse;
>
> architecture rtl of pulse is
> signal state : integer range 0 to 7;
> begin
> process(clk)
> begin
> if clk'event and clk = '1' then
> if reset = '1' then
> state <=0;
> else
> case state is
> when 0 => if pul = '1' then
> state <= 1;
> end if;
> pulse_4times <= '0';
>
> when 1 to 6 => pulse_4times <= '0';
> state <= state + 1;
> when 7 => pulse_4times <= '0';
if pul = '1' then
> state <= 7;
else
> state <= 0;
end if;
> end case;
> end if;
> end if;
> end process;
> end rtl;
The other posts noted that you never set pulse_4times to a '1'. Another
thing to consider is that you don't wait for the falling edge of pul
before resetting your counter. So if pul stays high for longer than your
FSM cycle time, it will trigger another ouput pulse.
Of course if pul is never longer than the FSM cycle time this is not a
problem. It is also not a problem if you intended this multiple ouput
pulse operation. Otherwise you might modify the code as above or
similar.
Also keep in mind that as you have coded it, pulse_4times is a
registered output which depends on the current state. So the output will
follow the state by one clock cycle, assuming you change one of the
assignments to a '1'...
You also might want to specify the reset state for pulse_4times.
--
Rick Collins
redsp@XYusa.net
remove the XY to email me.
Article: 11921I remember there being some posts on info from the Xilinx web site on the configuration process. Can someone repost where I can find that data. I have searched using their search tool and can't find what I am looking for. All I can find is the section out of the data book on configuration. I thought there was an app note on downloading from a uC. I need to put together a clear enough description that the software developer can code it. That can be quite a job sometimes. ;) -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 11922
> works out to a big depends. Let's assume SRAM for the time being. If you > need to do interleaved reads and writes, you will get more memory > bandwidth from asynchronous parts because there is a dead cycle between a > read and write cycle using the synchronous parts. If your application > requires interleaved reads and writes, you'll waste a lot of clocks in > dead time. You can use ZBT (zero bus turnaround) sync SRAMs. They have no dead cycles and are just wonderful. Micron, Motorola and IDT make them. StefanArticle: 11923
Wade D. Peterson wrote:
<snip>
> The biggest problems that I've run into are (a) race conditions (often
> causing 'glitches'), (b) metastability (where flip-flops cause
> glitches or oscillate after a clock edge) and (c) the guarentee of
> timing constraints (where you don't have a clock to coordinate
> activity).
<snip>
What about SRAM based FPGAs causing glitches? For example, a classic
combinatorial feedback loop like the following:
OUT = START
# HOLD & OUT;
may not work due to the gates themselves being implemented using SRAM
lookup tables. The output may glitch or even fail to latch at all (to
see this think what happens when the logic latches - once latched it
should be invariant to transitions on START, but since it's an SRAM
there is a settling time when OUT will be invalid as the new 'address'
is looked up. This invalid state is fed back causing more invalid
states). Also using gray coded signals and ORing them to form glitch
free outputs can also cause problems. SRAM based FPGAs such as Xilinx
4000 type devices should be avoided if the design contains any
combinatorial logic that is to remain glitch free (this goes for clock
domain resynchronizing too if gray coded FIFO flags are decoded and used
for resynchronization).
Mark.
Article: 11924On Fri, 18 Sep 1998 11:37:01 +0200, "Sten Søgaard" <soeg@kom.auc.dk> wrote: >I know that Xilinx >has had a guided layout option for some time now, but whenever I have >tried to use it, it results in a "Dr. Watson"-fault of some kind, I >don't remember. I thought this had been fixed recently (a few months ago?), but I haven't tried the patches on the website. >Has anyone else tried to use the Floorplaner with succes, is the >Floorplanner still a beta version, or is it my who are using it wrong ? I asked Xilinx for a beta a few months ago, but they said I should wait for the 'proper' release in 1.5, so I guess (hope) it's not beta any more. I can't help, since I haven't got 1.5 yet, but I would be interested to hear some more about what you're doing: 1) What synthesiser are you using? 2) After you've changed your entity, how much of the design do you re-synthesise? Just that one entity/all dependent entities/all 20 entities? 3) You say you remove the modified entity from the floorplan. How do you do this? Have you already floorplanned so that the entity is in one section of the device, or do you have to remove parts of the entity from all over the device? 4) If you had to re-synthesise any other entities, do you know if the XNF/EDIF signal names in those entities changed? I guess that the success of a guided or floorplan mapping will depend very much on how many signal names have changed (this is presumably why guided mapping is not recommended for synthesis designs). Mapping will be a problem if a small change in an entity results in name changes throughout the entity (which will happen with some synthesisers) - is this happening in your case? Evan
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