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n#:
31379: 01/05/21: Re: Maximum clock frequency to expect in Xilinx Virtex FPGA ?
31381: 01/05/21: RLocs on Inferred registers??
31409: 01/05/22: Re: RLocs on Inferred registers??
N. Gat:
5439: 97/02/16: The TechExpo Calendar of Science & Technology Events
8656: 98/01/16: Re: Call for Papers: FPL-98
9310: 98/03/05: CFP -- Save the date: On-Line Calendar of Science & Technology Events.
N.O.V.:
46246: 02/08/22: Re: Downloading bit streams in Xilinx
-N.RAMESH:
2275: 95/11/16: Any user experiences with Exemplar VHDL synthesis for FPGA
N.V. Chandramouli:
121141: 07/06/26: regarding the montavista linux preview kit
121548: 07/07/07: Re: New with FGPAs
122719: 07/08/04: EDK =>"Virtex4_PPC_Example_9_1" on ubuntu, not able to change LEDs blinking through minicom hyperterminal
122720: 07/08/04: EDK =>"Virtex4_PPC_Example_9_1" on ubuntu, not able to change LEDs blinking through minicom hyperterminal
122721: 07/08/04: xps error never seen before: google reveals nothing; help!
122773: 07/08/06: Re: xps error never seen before: google reveals nothing; help!
122774: 07/08/06: Re: xps error never seen before: google reveals nothing; help!
n1089240:
45074: 02/07/11: Using DLL's for 90 Degree Phase Shift
n2684172:
58413: 03/07/23: Re: processing `ifdef in Xilinx ISE 5.2i
<n4mwd@dont.spam.me.flinet.com>:
10916: 98/07/01: Xlinx CPLD bitstream format
n5ac:
145785: 10/02/23: data2mem and rodata/data (Xilinx)
145786: 10/02/23: Re: Data2Mem ? BlockRAM ? Init BMM and MEM
145799: 10/02/24: Re: data2mem and rodata/data (Xilinx)
n_d_solanki:
35519: 01/10/09: Re. gate count comparison of diff tap size for PDA FIR filter
NA:
118757: 07/05/03: Wait-for / until won't work ? Xilinx Spartan 3
118760: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
118762: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
119602: 07/05/23: Binary to BCD
119621: 07/05/24: Re: Binary to BCD
Nabeel Robert Ibrahim:
4036: 96/09/05: *** EE/CS Mother Site ***
Nabeel Shirazi:
11012: 98/07/10: Research Position Available at Imperial College
53639: 03/03/18: Re: Modelsim - FPGA - Simulink integration
Nachiket Kapre:
38117: 02/01/05: how do i program a Spartan FPGA
49910: 02/11/25: Re: Spartan IIe - DLL Max Input Clock Frequency
49937: 02/11/26: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49976: 02/11/27: Re: problems programming/verifying fpga using ISE 5.1
49980: 02/11/27: Re: State Machine Coding....
49981: 02/11/27: Re: clock difference between DLL input and output?
50047: 02/11/29: Re: programmable FSM
50064: 02/11/30: Re: Where can I find low cost 3rd party Xilinx j-tag programmer?
50065: 02/11/30: RAM and IO Standards
50066: 02/11/30: Re: programmable FSM
50169: 02/12/04: Re: Leonardo and Clock Buffer
50170: 02/12/04: Re: PROM for XC2S300
50171: 02/12/04: Re: ISE Impact 4.2 and Windows XP parallel port - works then it doesn't?
50172: 02/12/04: Re: clock difference between DLL input and output?
50896: 02/12/22: distributed computing with Modesim
50936: 02/12/23: Re: distributed computing with Modesim
50981: 02/12/24: Re: distributed computing with Modesim
51008: 02/12/25: Re: Question from newbie of WebPACK
51010: 02/12/26: probing modesim simulator state
51028: 02/12/26: Re: distributed computing with Modesim
51063: 02/12/29: Re: probing modesim simulator state - elaborated question
55094: 03/04/26: visualising a shift register using an LUT
60349: 03/09/10: test signals for testing of leaf level entities in a design
65018: 04/01/18: par problems with modular design for partial reconfiguration
65075: 04/01/19: Re: par problems with modular design for partial reconfiguration
65076: 04/01/19: Re: par problems with modular design for partial reconfiguration
65167: 04/01/21: mapping issues => Re: par problems with modular design for partial reconfiguration
65185: 04/01/21: map gives yet another error!
65410: 04/01/27: modular design routing returns 1 unrouted net GLOBAL_PSEUDO/CLK
65545: 04/02/01: Re: One bit Virtex BRAM.
68364: 04/04/02: Re: XAPP134's VHDL code
68421: 04/04/04: Re: XAPP134's VHDL code
71237: 04/07/12: Re: Programable Logic & Video stuff
Nacho:
6714: 97/06/18: Help, FPGA Information
48209: 02/10/14: VHDL & OBUFE8
nachum:
78869: 05/02/09: laptop for fpga design - acer ferrari?
78870: 05/02/09: quartus - Linux or Windows
78929: 05/02/10: Re: quartus - Linux or Windows
141242: 09/06/12: Verilog "for loop" - exit by setting i to exit value?
141654: 09/07/02: Verilog module parameter generating ports in module declaration?
141674: 09/07/03: default modelsim vsim options for verilog simulation
142345: 09/08/05: xilinx ise verilog constraint with concatenated string name
nachumk:
141246: 09/06/12: Re: Verilog "for loop" - exit by setting i to exit value?
141249: 09/06/12: Re: Verilog "for loop" - exit by setting i to exit value?
141267: 09/06/14: Re: Verilog "for loop" - exit by setting i to exit value?
Nad:
140854: 09/05/27: Cyclone3 and AT45DB serial flash
Nadav Rotem:
136916: 08/12/13: Online C-to-FPGA tool
136922: 08/12/13: Re: Online C-to-FPGA tool
Nadeem Douba:
63474: 03/11/22: LF: Affordable Development Board
Nadeem Sarwar:
3719: 96/07/21: Information on Actel
3722: 96/07/21: Actel information
Nadidjka:
141809: 09/07/10: more than one core of microblaze on EDK and ISE
<nadson@aol.com>:
11455: 98/08/16: Looking for this Digital Design Book
Naftaly Blum:
8478: 97/12/19: Re: Engineers Wanted
nagaraj:
114688: 07/01/22: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP
114697: 07/01/23: Re: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP
114706: 07/01/23: Re: Difference between virtex 4 rocketio MGT and viretex 5 rocketio GTP
114850: 07/01/25: IP Protection
116135: 07/03/01: Re: xilinx block ram synthesis
116222: 07/03/05: Re: xilinx block ram synthesis
125529: 07/10/27: total equivalent gate count
Nagaraj:
43165: 02/05/15: Processor interface to memory mapped FPGA
43675: 02/05/29: place and route simulation time
44328: 02/06/17: what's the use of BlockRAM
44387: 02/06/18: Re: what's the use of BlockRAM
44437: 02/06/19: Re: what's the use of BlockRAM
44624: 02/06/24: FPGA to ASIC migration
45057: 02/07/10: Read Delay
47464: 02/09/26: Dual Port RAM
47519: 02/09/27: Re: Dual Port RAM
49905: 02/11/24: Using DLL output offchip
49940: 02/11/26: Timing with ISE5.1i
49986: 02/11/27: Re: Timing with ISE5.1i
50533: 02/12/12: MTBF Calculation
50579: 02/12/12: Re: MTBF Calculation
50914: 02/12/22: Digital Resampling
50959: 02/12/23: DLL wave shape
51246: 03/01/08: internal nets
51404: 03/01/13: FPGA to ASIC migration - Help
56875: 03/06/17: Re: An All Digital Phase Lock Loop
56876: 03/06/17: FPGA to Custom ASIC ??
58224: 03/07/17: Direct Digital Converter
59620: 03/08/25: Which Adder?
60114: 03/09/05: Filter Output Quantization in Digital Down Converter
60303: 03/09/10: Crystal Input to FPGA
60357: 03/09/11: Time Killing Post P&R Simulation
62129: 03/10/20: Re: ISE5.2 to ISE6.1
62645: 03/11/03: Tools Tree
62704: 03/11/05: Re: Tools Tree
62850: 03/11/10: Re: ASIC vs FPGA
65322: 04/01/24: Power Cosumption of a Memory Unit
135953: 08/10/23: Altera - clock to output (pin) delay
142469: 09/08/12: System gates: Altera <-> Actel
144660: 09/12/21: FFT Ccre
NAGARAJAN BALAKRISHNAN:
335: 94/10/23: Xilinx ROMS
Nagesh:
103570: 06/06/06: Re: Help on DDR SDRAM contoller generated by MIG1.5
111275: 06/10/31: Re: Xilinx MIG 1.6 doesn't launch
Nahid:
78974: 05/02/10: NIOS - newbie
Nahum Abramovitch:
38128: 02/01/06: 4 fpga configuration using 1 EPROM
Nahum Barnea:
40403: 02/03/06: max frequency of obuf_lvdci_dv2_18
40507: 02/03/08: suggestion to comp.arch.fpga
40712: 02/03/13: minimum value for clock to output
40731: 02/03/14: use virtex2 DCM as delay line
40866: 02/03/17: Re: minimum value for clock to output
40986: 02/03/19: Re: minimum value for clock to output
42901: 02/05/06: clock multiplication in xilinx
43607: 02/05/26: footprint competabilty in virtex-II devices
45819: 02/08/06: parameterized / variable ucf
45833: 02/08/06: xilinx: map -k
45854: 02/08/07: xilinx RLOC usage
45923: 02/08/10: Re: xilinx RLOC usage
47846: 02/10/05: DCM outputs skew question
50299: 02/12/08: XIL_PAR_SKIPAUTOCLOCKPLACEMENT question
50348: 02/12/09: Xilinx DCM status bits
50640: 02/12/15: virtex PRO migration cost
52977: 03/02/27: several fpga high bandwidth questions
53050: 03/03/01: Re: several fpga high bandwidth questions
53052: 03/03/01: Re: several fpga high bandwidth questions
54282: 03/04/07: DCM input duty cycle constraint
57842: 03/07/08: workstation for virtex2 - 8000
60554: 03/09/16: Virtex2 - HSTL interface
61800: 03/10/11: Re: pci-x133 to parallel pci-66
61817: 03/10/13: PCI-X bridge from Xilinx LogiCORE and half bridge
61855: 03/10/14: Re: PCI-X bridge from Xilinx LogiCORE and half bridge
61921: 03/10/15: Re: PCI-X bridge from Xilinx LogiCORE and half bridge
62409: 03/10/29: LogiCORE PCI-X question
64152: 03/12/18: Xilinx IOSTANDARD for PCI-X 100MHz interface
64185: 03/12/19: Re: Xilinx IOSTANDARD for PCI-X 100MHz interface
66556: 04/02/22: TCP offload fpga core
67847: 04/03/21: Xilinx map -timing through ise gui
69252: 04/05/03: Re: Slack gets worst as I relax timing
74101: 04/10/04: does ISE 6.3 improve timing vs. ISE 6.2 ?
76116: 04/11/25: PCI interrupt negation
86959: 05/07/11: Re: design does not fit in device
<nahum@oksi.com>:
92665: 05/12/03: Looking for FPGA Programming consultant
<nahum_barnea@yahoo.com>:
77113: 04/12/23: constraint for PCI & PCI-X core
86936: 05/07/10: design does not fit in device
87823: 05/08/02: fpga- DDR or DDR2
89220: 05/09/08: burn xcf16p through PCI jtag
89586: 05/09/20: program prom by the fpga
89590: 05/09/20: Re: Reprogramming FPGA over PCI???
naim32:
141192: 09/06/10: Re: Doubt about a Microblaze Based Multiprocessor SoC
141206: 09/06/11: Re: Doubt about a Microblaze Based Multiprocessor SoC
141223: 09/06/11: Re: Doubt about a Microblaze Based Multiprocessor SoC
141230: 09/06/11: Re: Doubt about a Microblaze Based Multiprocessor SoC
Naimesh:
70568: 04/06/21: Spartan: How to select device as Spartan/SpartanXL
70571: 04/06/21: Spartan/SpartanXL Device Selection
70607: 04/06/21: Re: Spartan/SpartanXL Device Selection
70810: 04/06/28: Re: Spartan/SpartanXL Device Selection
71454: 04/07/19: Warning During Simulation
73173: 04/09/15: Simulation Warning
74212: 04/10/06: ActGen to use or not to use?
75422: 04/11/05: Clock loading in XC9572 CPLD
75451: 04/11/05: Re: Clock loading in XC9572 CPLD
75496: 04/11/07: XST Question
Naive_Algorithm:
125965: 07/11/10: Re: FPGA Clock signal
Nak:
22162: 00/04/28: [HELP] - Express Mode for XC5000
22183: 00/04/29: Re: [HELP] - Express Mode for XC5000
naliali:
126999: 07/12/08: problem interfacing AD9510 via serial controller
127109: 07/12/11: Re: Chipscope 7.1 and JTAG TAP
Nalini Ratha:
2868: 96/02/20: FPGA usage distribution
naluzzi filippo:
48978: 02/10/28: programming flex10k
NAM MIN WOO:
2037: 95/10/05: Need Some Test Data
2038: 95/10/05: Need Some Test Data
2232: 95/11/07: I find large VHDL code(for my partition system)
2262: 95/11/14: Looking for large circuit
name:
8244: 97/12/03: Re: what is metastability time of a flip_flop
8295: 97/12/06: Re: what is metastability time of a flip_flop
8312: 97/12/08: Re: what is metastability time of a flip_flop
30168: 01/03/26: Re: Logic trimmed (XCS40 F3.1)
30194: 01/03/27: Re: hybrid design entry
41994: 02/04/12: Re: DDR SDRAM Controller
51226: 03/01/07: Running Synplify under Windows XP
51228: 03/01/07: Re: dualport ram instantiation in Spartan IIE
Name Deleted:
5924: 97/03/26: Looking for a Digital Design Job!
@Name@:
5109: 97/01/24: Re: GATEFIELD from Zycad
nameiswolf:
62052: 03/10/17: Re: Italy is out of FPGA world?
namit:
141275: 09/06/15: bidirectional buffer
<namth299@gmail.com>:
141033: 09/06/02: error with xps_ll_temac
nana:
111174: 06/10/30: xup virtex2 pro
111981: 06/11/14: xupv2p
112451: 06/11/22: Aurora and Chipscope
114050: 07/01/03: Chipscope
115183: 07/02/01: read fpga
nana_7488:
153815: 12/05/25: Read output from external chip using microblaze
153897: 12/06/26: Re: Read output from external chip using microblaze
<nanaware_amit@rediffmail.com>:
124419: 07/09/21: how interfacing of cpld and cpu done?
Nancy Donahue:
9104: 98/02/20: Re: crossbar switch
Nancy Kotecki:
9518: 98/03/20: Canadian Career Opportunity
Nanda Katikaneni:
4542: 96/11/11: Suggest an interesting but manageable undergrad project.
<nandigits@gmail.com>:
97175: 06/02/17: Find and fix critical paths in gate level netlist by GOF
Nandini:
35828: 01/10/18: map,place &route
36115: 01/10/30: timing difference
Nanditha:
86737: 05/07/05: Re: aurora framing
92494: 05/11/30: Re: Successful use of MGT on Virtex 4
92516: 05/11/30: Re: Successful use of MGT on Virtex 4
<nandits11@gmail.com>:
119577: 07/05/22: M-RAM allocation in Stratix EPS125B672C6
nanotech:
143402: 09/10/09: foundation 2.1 - 3.1 sharing...
Naohiko Shimizu:
31517: 01/05/29: My80-- i8080A instruction compatible processor core
31735: 01/06/05: Re: My80-- i8080A instruction compatible processor core
43070: 02/05/12: Announce:GPLed 6502 IP core
44296: 02/06/17: [ANN] Free SFL to Verilog converter (with 6502/z80 core)
56742: 03/06/13: PDP11/40 Compatible CPU on an FPGA
Nap:
57719: 03/07/04: About BRAM in VirtexII
napier_surf:
27222: 00/11/16: Re: ViewLogic ViewDraw questions
nappy:
69226: 04/04/30: Re: Looking for a USB-enabled flash-based microcontroller with CPLD/FPGA
69227: 04/04/30: Correction
nara_chak45:
83727: 05/05/05: re:IPIF
83728: 05/05/05: re:How to control peripheral say a small DC motor using ML300
83729: 05/05/05: EDK "libSecurity.dll"
83730: 05/05/05: How to control peripheral say a small DC motor using ML300
83934: 05/05/10: re:How to control peripheral say a small DC motor using ML300
84420: 05/05/18: where are the PAO files for the system.bsp stored???
naran:
120383: 07/06/06: Reg:Clock to pad Delay of the System Clock.
<narashimanc@gmail.com>:
94966: 06/01/19: Quadrature Encoder ::
95448: 06/01/23: Re: Quadrature Encoder ::
Narasimha:
72368: 04/08/17: Re: Spartan 3 Xilinx IO Standards
72373: 04/08/17: Re: Spartan 3 Xilinx IO Standards
72404: 04/08/17: Re: Spartan 3 Xilinx IO Standards
Narayan:
85777: 05/06/15: convert vhdl to edif
89067: 05/09/04: Problem with interfacingT-VPACK with ALTERA QUIP5.0
89090: 05/09/05: Re: Problem with interfacingT-VPACK with ALTERA QUIP5.0
Narc?s Nadal:
69222: 04/04/30: Re: transport applications
69223: 04/04/30: Re: transport applications
Narcis Nadal:
69010: 04/04/25: Re: transport applications
Naren:
75196: 04/10/28: Xilinx Platform Studio- I don't get C source code error messages.
Narendra Sisodiya:
129169: 08/02/17: Video Over RF - using bluetooth and Xilinx Video Starter Kit
129173: 08/02/17: Re: Video Over RF - using bluetooth and Xilinx Video Starter Kit
129233: 08/02/19: Which Linux Distro to use for Xilinx tools
129244: 08/02/19: Re: Which Linux Distro to use for Xilinx tools
129268: 08/02/19: Re: Which Linux Distro to use for Xilinx tools
129278: 08/02/19: Re: Which Linux Distro to use for Xilinx tools
129279: 08/02/19: Re: Which Linux Distro to use for Xilinx tools
129405: 08/02/22: Re: Video Over RF - using bluetooth and Xilinx Video Starter Kit
131519: 08/04/24: will there be any problem with diffrent version of sysgen & EDK
131520: 08/04/24: video stream transfer via UART and Bluetooth in FPGA
131531: 08/04/24: Re: video stream transfer via UART and Bluetooth in FPGA
131541: 08/04/24: Re: video stream transfer via UART and Bluetooth in FPGA
131542: 08/04/24: Re: will there be any problem with diffrent version of sysgen & EDK
131546: 08/04/24: Re: will there be any problem with diffrent version of sysgen & EDK
132157: 08/05/16: LwBT port for microblaze
132379: 08/05/24: Video stream over bluetooth
132391: 08/05/25: Re: Video stream over bluetooth
132449: 08/05/27: Re: Video stream over bluetooth
Narendran Kumaraguru Nathan:
74439: 04/10/12: Re: VHDL help needed ($)
74416: 04/10/11: Re: VHDL help needed ($)
<narenvarmap@gmail.com>:
75247: 04/10/30: Re: Xilinx Platform Studio- I don't get C source code error messages.
naresh:
126490: 07/11/24: Xilinx Dual processor design
<nareshgbhat@gmail.com>:
133879: 08/07/18: Problem creating the ML403 project using Xilinx tool
133888: 08/07/18: ml403_emb_ref_ppc_81.zip problem
133889: 08/07/18: Re: Problem creating the ML403 project using Xilinx tool
133891: 08/07/18: Re: Problem creating the ML403 project using Xilinx tool
133893: 08/07/18: Re: Problem creating the ML403 project using Xilinx tool
133974: 08/07/20: Re: Problem creating the ML403 project using Xilinx tool
Narsi:
124718: 07/10/01: Test and Measurements - Large FPGA
124719: 07/10/02: Re: Planning to switch to FPGA domain, any advice would be highly appreciated
124745: 07/10/02: Re: Test and Measurements - Large FPGA
nashafi:
83107: 05/04/23: how to put an FIR in an FPGA?
Nashit Ashraf:
141611: 09/06/30: help needed regarding NOR Flash
nasif4003@gmail.com:
120441: 07/06/07: verilog HDL problem
<natarajan.jayaram@gmail.com>:
133650: 08/07/08: Altera FPGA and data from matlab workspace.
nate:
69221: 04/04/30: programming the mach231
69324: 04/05/06: Re: programming the mach231
Nate D. Tuck:
46575: 02/09/03: Re: Hardware Code Morphing?
Nate Goldshlag:
15209: 99/03/13: Re: Actel FPGA
33291: 01/07/22: Re: Measuring power consumption
35372: 01/10/01: barrel shifter in Xilinx Virtex-E
39741: 02/02/18: Re: Power estimation for Virtex-2 device
61179: 03/09/29: Anybody have any experience with Altera Stratix 840 Mbps LVDS?
62826: 03/11/08: Re: latch and shift 15 bits.
76878: 04/12/15: Altera Quartus II 4.2 broke our simulation!
nath:
68529: 04/04/07: nios on-chip RAM
nathan:
78214: 05/01/26: Re: 60Hz clock on XC9572
78260: 05/01/27: Re: 60Hz clock on XC9572
Nathan Baulch:
44852: 02/07/03: Could someone please simplify Synplify for me...
Nathan Bialke:
104453: 06/06/27: Re: RS232 to access TX registers of Aurora using PPC (EDK)
105041: 06/07/12: Re: Programming the Spartan-3E Starter Kit using Linux?
126086: 07/11/14: Re: Xilinx Virtex-II Newbie
126115: 07/11/14: Re: Xilinx Virtex-II Newbie
126116: 07/11/14: Re: Xilinx Virtex-II Newbie
127451: 07/12/26: Re: Spartan 3 FPGA verification via readback
131907: 08/05/06: Re: FPGA dev kit with 4-8 Cyclones or Spartans
134842: 08/09/03: Re: XST bug on illigal states of a FSM ?
135601: 08/10/09: Re: More Actel 'Funnies'
135730: 08/10/13: Re: sensitive fpga
135813: 08/10/16: Re: Using GCK pin as both clock and signal (Spartan 2)
135821: 08/10/16: Re: Using GCK pin as both clock and signal (Spartan 2)
135827: 08/10/16: Re: Using GCK pin as both clock and signal (Spartan 2)
135833: 08/10/16: Re: Using GCK pin as both clock and signal (Spartan 2)
137233: 09/01/05: Re: beginner synthesize question - my debounce process won't
137909: 09/02/02: Why the second flip-flop in Virtex-6?
137974: 09/02/03: Re: Implementation of Xilinx Aurora protocol with error correction
138627: 09/03/02: Re: ODDR output to use internally
138923: 09/03/14: Re: Virtex 5 LVDS
139249: 09/03/24: Re: Using SelectIO LVDS to drive 40 inch backplane trace
140512: 09/05/15: Re: Virtex 5 clocking
140515: 09/05/15: Re: Virtex 5 clocking
140763: 09/05/25: Re: passing data from fast to slow time domain
141215: 09/06/11: Re: Safe margin in FPGA static timing analysis
141634: 09/07/01: Re: Cheapest FPGA with decent PCI- e interface ?
142032: 09/07/22: Re: gate capacity between old Virtex-II and newer Virtex-4
146106: 10/03/05: Re: Is an inout reg allowed
Nathan Hunsperger:
71402: 04/07/17: Re: Spartan3 Dev Boards
71583: 04/07/23: Re: Looking for ways to keep diagnostic signal from being optimized out (Xilinx)
Nathan Jachimiec:
1146: 95/05/04: copy
Nathan Knight:
53894: 03/03/26: Re: Altera EPXA1 Development Kit - problems with the GNUPro Insight Debugger
73585: 04/09/24: Re: NIOS II (full sample working with DMA in HAL)?
75063: 04/10/25: Re: Altera NIOS2 flash prgrm port
<nathan_wilson@hotmail.com>:
78084: 05/01/24: 60Hz clock on XC9572
<naude.jaco@gmail.com>:
121590: 07/07/09: Re: XilinxSystemGenerator and Simulink
121591: 07/07/09: Error message in ModelSIM PE
<naughty.zeut@gmail.com>:
125113: 07/10/16: Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2
138245: 09/02/10: Implementing reset / enable in FPGA question
138272: 09/02/11: Re: Implementing reset / enable in FPGA question
138286: 09/02/12: Re: Implementing reset / enable in FPGA question
Nauman Mir:
141881: 09/07/15: HELP required floating point multiplier on FPGA
141882: 09/07/15: HELP required floating point multiplier on FPGA
141952: 09/07/19: Re: HELP required floating point multiplier on FPGA
142314: 09/08/03: Program Memory Space for Microblaze Processor in Spartan-3A
<naumanqau@gmail.com>:
110447: 06/10/15: Low hierarchy not follow in ChipScope Pro
110460: 06/10/16: Re: Low hierarchy not follow in ChipScope Pro
<nav_tiwari@rediffmail.com>:
137271: 09/01/06: Re: Classifying different kinds of FPGA optimizations
<navanee@gmail.com>:
117229: 07/03/26: Re: Solaris 10
Navaneethan Sundaramoorthy:
20213: 00/01/31: Help with xdl -ncd2xdl
21299: 00/03/15: Re: Can we read bits from a file in PCc using Altera or Xilinx ?
naveed:
9464: 98/03/16: Re: Byteblaster
Naveed:
57048: 03/06/22: "Ethernet only" network
57049: 03/06/22: Difference between ASIC and FPGA
57058: 03/06/22: Re: "Ethernet only" network
57059: 03/06/22: Re: Is this is possible???
57060: 03/06/22: Implementing standard DDR module with Cyclone 1C6 (240PQFP)
57343: 03/06/27: Re: why so many problems Xilinx ?
62026: 03/10/16: Re: Altera mySupport
63115: 03/11/15: Altera's EPCS programming algorithm
63127: 03/11/15: Re: Altera's EPCS programming algorithm
63137: 03/11/16: Re: Altera's EPCS programming algorithm
66569: 04/02/23: Re: altera, xilinx susceptible to power transients?
66788: 04/02/26: Re: altera, xilinx susceptible to power transients?
Naveen:
121638: 07/07/10: ISE 9.1i - Process Map Fail without any Error messages
140589: 09/05/19: Prob with verilog memory
naveen:
49928: 02/11/25: Delayed Transactions for PCI Target Core
51377: 03/01/12: CONCEPT OF BALL GRID ARRAY
51481: 03/01/14: Re: CONCEPT OF BALL GRID ARRAY
51484: 03/01/14: software for
51641: 03/01/17: newbie questions
52222: 03/02/04: Re: xilinx tools: How to convert Schematic design to VHDL code
52327: 03/02/06: debounce circuit
52556: 03/02/13: BLACK BOX
52823: 03/02/23: need help
52836: 03/02/24: Re: need help
52837: 03/02/24: HELP WANTED
52861: 03/02/24: Re: HELP WANTED
53006: 03/02/28: error in the design
53561: 03/03/16: on chip components
54485: 03/04/11: fpga fault tolerence.
54575: 03/04/14: Re: fpga fault tolerence.
54576: 03/04/14: configuration file
54802: 03/04/18: LFSR MAXIMUM LENGTH
54836: 03/04/19: Re: LFSR MAXIMUM LENGTH
55164: 03/04/29: DIAGNOSIS AND FAULT TOLERANCE
55381: 03/05/06: ROVING STARS
61340: 03/10/01: Host-PCI Bridge
61394: 03/10/02: Re: Host-PCI Bridge
63399: 03/11/20: How to set 'set up time' in a Quartus Tool for a PCI Device
66798: 04/02/26: Suggestions
Naveen Gupta:
51083: 02/12/30: xilinx virtex "done" pin problem with jtag
Naveen.........:
139711: 09/04/10: NCO'S
<naveen.thohare@gmail.com>:
140563: 09/05/17: Doubts in using memory of verilog
Navneet Rao:
82896: 05/04/19: Re: Strange FPGA problem
Navneet S Yadav:
1584: 95/07/21: Altera Software on DEC Alpha
1718: 95/08/18: Re: Email Address of Xilinx
4007: 96/09/02: Gate Count - Notion of Gate
6938: 97/07/11: VHDL Synthesis in Xilinx Foundation Series
Navya:
72926: 04/09/08: How to use Windpower ICE with Virtex2Pro V2P4 FG456 board from Memec
73055: 04/09/13: Bus Frequecy in virtex2p powerpc
<nayak@cromp.ernet.in>:
10139: 98/04/29: Re: Make a delay in Xilinx FPGAs (Help)?
nba83:
153393: 12/02/15: problem with Global Clock pin and normal IO pin as Clock input
153409: 12/02/17: Re: problem with Global Clock pin and normal IO pin as Clock input
153412: 12/02/18: Re: gigabit ethernet problem
153416: 12/02/20: Re: gigabit ethernet problem
153420: 12/02/21: Re: gigabit ethernet problem
153422: 12/02/22: Re: gigabit ethernet problem
153424: 12/02/22: Re: gigabit ethernet problem
153446: 12/02/27: Re: gigabit ethernet problem
153447: 12/02/27: Re: gigabit ethernet problem
153453: 12/02/28: Re: gigabit ethernet problem
153630: 12/04/07: Watchdog reset for fpga designs
153944: 12/07/02: Generate a pulse with a definite width
154278: 12/09/23: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
154295: 12/09/24: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
154297: 12/09/24: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
154305: 12/09/25: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
154311: 12/09/26: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
154313: 12/09/26: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
154801: 13/01/13: Re: FPGA board with SD card slot (code test)
155210: 13/06/08: A Question about FPGA IO Standard
156764: 14/06/23: problem with xc3s400 place and rout section
156783: 14/06/25: Re: problem with xc3s400 place and rout section
<nbg2006@gmail.com>:
110084: 06/10/10: Xilinx coregen fifo
110231: 06/10/12: Re: Xilinx coregen fifo
114629: 07/01/21: system generator from Xilinx
126479: 07/11/23: vhdl state machine
<nbsfor@home.com>:
16609: 99/05/30: @home & networks 6282
nchandra@gmail.com:
91837: 05/11/14: Using JTAG cable for general comms
<ncunha@gmail.com>:
91305: 05/11/02: Using inout ports in VHDL
ndesi:
45589: 02/07/27: Programming FLASH with Xilinx Parallel Cable III
71181: 04/07/10: Altera configuration Problem?? Help
Ndf:
104518: 06/06/29: Stopping the clock for power management
104579: 06/06/30: Re: Stopping the clock for power management
113679: 06/12/19: PLL minimum input clock frequency
113733: 06/12/20: Re: PLL minimum input clock frequency
141376: 09/06/22: Using SERDES to detect very high-speed pulse.
ndt:
96912: 06/02/13: Rocketio, modelsim xe
<ndznzb@peerweeer.com>:
Neal Becker:
688: 95/02/07: Re: [shin]Anyone ported or have patches for OCTTOOLS to Linux?
1507: 95/07/05: AHDL reference?
2808: 96/02/10: Altera Simulation
4518: 96/11/08: Re: Integer Multiplier
6833: 97/07/01: Altera archiving
Nebojsa:
91017: 05/10/27: Single Event Upset
Ned Konz:
40661: 02/03/12: Re: Mystery two wire interface, or am I being dense?
NeedCleverHandle:
150977: 11/02/25: Re: How to keep iSE from grounding pins
151017: 11/02/28: Re: Nanosecond pulse generator using Spartan-3E
151057: 11/03/02: Re: encryption in FPGA
151151: 11/03/11: Re: pcb&bitstream
151182: 11/03/14: Re: pcb&bitstream
151229: 11/03/16: Re: pcb&bitstream
151261: 11/03/18: Re: DMA (memory to memory)
151433: 11/04/07: Re: Ethernet MAC on Virtex 4
151549: 11/04/18: Re: ethernet core on FX12 mini module
151550: 11/04/18: Re: Simili
151591: 11/04/22: Re: Xilinx ML605 Demo Qusstion
151630: 11/04/27: Re: about slices in xilinx
151675: 11/05/04: Re: Win an Altera DE0-Nano (Cyclone IV Dev Kit)!
151693: 11/05/05: Re: ise 10.1 (Linux) contraints problem
151717: 11/05/09: Re: USB support for XUPV2P
151720: 11/05/09: Re: Win an Altera DE0-Nano (Cyclone IV Dev Kit)!
151724: 11/05/10: Re: Soft Processors and Licensing
151771: 11/05/16: Re: Best syntheses
152032: 11/06/23: Re: P&R based on the post-map simulation model?
needhelp:
51255: 03/01/08: 4-bit excess-3 counter with parallel load
<neer4j.iit.delhi@gmail.com>:
156146: 13/12/19: New Cloud Based VHDL Simulator-Tarang
Neeraj:
40644: 02/03/12: Re: FPGA download fails
46317: 02/08/25: Re: FPGA speed level
46512: 02/09/02: Re: A little question
neeraj:
86290: 05/06/24: Re: Xilinx webshop
Neeraj Varma:
46589: 02/09/04: Re: The Prodigal Son
46604: 02/09/04: PPC blocks in XC2VP50
46658: 02/09/05: Re: PPC blocks in XC2VP50
46699: 02/09/06: Re: Modular Design
49270: 02/11/07: Re: 5.1i and Win-NT
49377: 02/11/11: Re: rs encode
51306: 03/01/10: Re: Small outline FPGA/PLD with differential LVPECL capability
51831: 03/01/23: Re: What's a "D-MIPS"?
52286: 03/02/06: Re: Xilinx Foundation 5.1: reasons to upgrade
52682: 03/02/19: Re: XCV800 Configuration PROM
52878: 03/02/25: Re: Licencing for downloadable FPGA tools
53511: 03/03/14: Re: What is the diff between FPGA and CPLD?
53601: 03/03/18: Re: FPGA dev boards
53628: 03/03/18: Re: usb spartan prototype
53717: 03/03/20: Re: PrimeTime
53742: 03/03/21: Re: programmer adapter for Xilinx XC9572
53756: 03/03/21: Re: programmer adapter for Xilinx XC9572
53796: 03/03/24: Re: Chipscope pro Tools
54284: 03/04/07: Re: price of fpga chips
54423: 03/04/10: Re: $4000 FPGAs
54629: 03/04/15: Re: Buying FPGAs from parts brokers
54686: 03/04/16: Re: spartan 3 pin compatible with 2E?
54707: 03/04/16: Re: spartan 3 pin compatible with 2E?
55540: 03/05/12: Re: Xilinx : Tools
55758: 03/05/19: Re: smallest embedded cpu....and the most pain?
55759: 03/05/19: Re: a (PC) workstation for FPGA development
56266: 03/06/02: Re: SONET/SDH chipset on FPGA
56319: 03/06/03: Re: FPGA design: firmware or hardware?
56591: 03/06/10: Re: System generator and Virtex2Pro Design
57783: 03/07/07: Re: Spartan XL Tool Support
57983: 03/07/11: Re: Spartan XL Prom Selection
58157: 03/07/16: Re: PROM size for spartan
58543: 03/07/25: Re: Pricing question....
58882: 03/08/04: Re: 5 volt tolerant Xilinx parts
59040: 03/08/07: Re: Does Xilinx Webpack 5.2 work on WinNT SP6?
59206: 03/08/12: PalmChip Patent
59247: 03/08/13: Re: News server for posting [was Re: Q: async flip-flop reset by a signal from a different clock domain]
59489: 03/08/21: Re: Legacy 4005 series and current Xilinx ISE offerings?
59643: 03/08/25: Re: Enhancing PAR with FPGA floorplanners
60141: 03/09/05: Re: Original (5V) Xilinx Spartan ?
60402: 03/09/12: Re: Spartan-3 3S50 in Web ISE 5.2i = no block RAM, no multiplier?
60484: 03/09/15: Re: need help with Xilinx ISE 4.2i software
61105: 03/09/28: Re: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
61154: 03/09/29: Re: development-tools under linux for altera excalibur
61413: 03/10/03: Re: OT: spam poll
62870: 03/11/10: Re: Tools Tree
72177: 04/08/10: Re: Spartan Software
72214: 04/08/12: Re: FPGA/CPLD from logic diagram?
72590: 04/08/26: Re: Help, synthesis for Spartan XL; does FPGA Express licenses for ISE 3 or 4 expire?
72840: 04/09/04: Re: Spartan 3 Starter Kit and ISE WebPACK
73378: 04/09/21: Re: FPGA with PCI interface for video processing?
Neeraj Yadav:
156152: 13/12/20: Re: New Cloud Based VHDL Simulator-Tarang
<neeraj_varma@yahoo.com>:
87685: 05/07/28: Re: Conversion of ASIC RTL to FPGA RTL
NEETU GARG:
68602: 04/04/09: Unsupported feature error:access type is not supported
<neha.karanjkar@gmail.com>:
107496: 06/08/29: Undergrad project-8051 specifications??
Neiko:
78168: 05/01/25: Another problem getting ISE 6.3i running on Linux
78187: 05/01/25: Re: Another problem getting ISE 6.3i running on Linux
Neil:
7328: 97/08/27: daisy-chained bitstreams
39787: 02/02/19: Re: FPGA: JTAG CABLE
76977: 04/12/17: Clock Synchronization
77044: 04/12/20: Re: Clock Synchronization
Neil Badenoch:
30400: 01/04/06: x4000 series reset
Neil Carrington:
11126: 98/07/20: Asynchronous FIFO's for XILINX PCI
16756: 99/06/07: Re: XILINX/ALTERA compatibility
Neil Franklin:
26191: 00/10/08: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26192: 00/10/08: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26207: 00/10/08: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26208: 00/10/08: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26287: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26289: 00/10/11: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26353: 00/10/13: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26402: 00/10/15: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26412: 00/10/15: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26417: 00/10/15: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26454: 00/10/16: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26472: 00/10/17: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26473: 00/10/17: VHDL vs Verilog
27363: 00/11/19: Re: Hardware suggestions for evolutionary experiments
27364: 00/11/20: Re: In the news
27394: 00/11/20: Re: In the news
27395: 00/11/20: Re: In the news
27564: 00/11/29: Re: Xess - XS40-005XL question
27609: 00/11/29: Re: Xess - XS40-005XL question
27778: 00/12/07: Re: JBits, Xilinx customer "support" (was Re: Virtex ROM ques.)
27686: 00/12/02: Re: Virtex ROM ques.
28088: 00/12/20: Re: FPGA and Board for Microprocessor Design?
28178: 00/12/24: Re: Question about programming xcv100
28879: 01/01/26: Re: Foundation FPGA Editor hard macros in VHDL
29593: 01/02/27: Re: Partial Reconfig using JBits
29755: 01/03/07: Re: More detailed Spartan II CLB drawings?
29806: 01/03/11: Re: More detailed Spartan II CLB drawings?
29932: 01/03/19: TBUFs in Virtex and later chips, going out of fashion, what instead
29966: 01/03/19: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30043: 01/03/21: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
31136: 01/05/12: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31137: 01/05/12: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31139: 01/05/12: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31155: 01/05/13: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31264: 01/05/16: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31353: 01/05/20: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31357: 01/05/20: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31662: 01/06/02: Re: Xilinx XC4010E Problem
31849: 01/06/07: Re: Xilinx Configuration Bitstream
32996: 01/07/14: Re: Design entry
33102: 01/07/17: Re: Xilinx .bit file format
34574: 01/08/29: Re: download bitstream to FPGA
34641: 01/08/31: Re: Jbits: more info required
34642: 01/09/01: Re: XCV800 : Jbits
36038: 01/10/26: Re: LUT Glitches
36265: 01/11/04: Re: JBITS and modular FPGA configuration
36297: 01/11/05: Re: How dense are FPGA/CPLD's
36366: 01/11/07: Re: Modifying BlockRAM contents in a bitstream?
36437: 01/11/08: Re: Xilinx machine readable package info
36519: 01/11/10: Re: Carry chain in Virtex II
36578: 01/11/12: Re: Carry chain in Virtex II
37016: 01/11/28: Re: Is there a full open-source synthesis path for any FPGA?
37031: 01/11/28: Re: Is there a full open-source synthesis path for any FPGA?
37090: 01/11/30: Re: Is there a full open-source synthesis path for any FPGA?
37130: 01/11/30: Re: Is there a full open-source synthesis path for any FPGA?
37131: 01/11/30: Re: Is there a full open-source synthesis path for any FPGA?
37132: 01/11/30: Re: Is there a full open-source synthesis path for any FPGA?
37147: 01/12/01: Re: Is there a full open-source synthesis path for any FPGA?
37148: 01/12/01: Re: Is there a full open-source synthesis path for any FPGA?
37162: 01/12/02: Re: Is there a full open-source synthesis path for any FPGA?
37171: 01/12/02: Re: Is there a full open-source synthesis path for any FPGA?
37202: 01/12/03: Re: Is there a full open-source synthesis path for any FPGA?
37203: 01/12/03: Re: Is there a full open-source synthesis path for any FPGA?
37204: 01/12/03: Re: Is there a full open-source synthesis path for any FPGA?
37309: 01/12/06: Re: where is designed FPGA for apple II computer...?
40047: 02/02/25: Re: Comparison between two FPGAs- what is decisive factor?
40938: 02/03/18: Re: questions from a newby
42036: 02/04/13: Re: new to fpga's need insight
42038: 02/04/13: Re: new to fpga's need insight
43086: 02/05/13: Re: Architecture for high-level reconfigurable computing
43138: 02/05/14: Re: Architecture for high-level reconfigurable computing
43142: 02/05/14: Re: Architecture for high-level reconfigurable computing
43175: 02/05/15: Re: Architecture for high-level reconfigurable computing
43524: 02/05/22: Re: Routing in a 6200-like sea of gates
44529: 02/06/22: Re: new computer
44557: 02/06/23: Re: new computer
44609: 02/06/24: Re: new computer
44846: 02/07/03: Re: Bitstream Verification (JBITS)
44880: 02/07/03: Re: Bitstream Verification (JBITS)
45781: 02/08/05: Re: Soundchip?
45827: 02/08/07: Re: Qn: Low Level Design
46001: 02/08/14: Re: RBT versus BIT file
46893: 02/09/11: Re: FPGA comes with a DAC?
47032: 02/09/15: Re: Readback size for virtex2
48082: 02/10/11: Re: Why can Xilinx sw be as good as Altera's sw?
48161: 02/10/12: Re: Why can Xilinx sw be as good as Altera's sw?
48163: 02/10/12: Re: Why can Xilinx sw be as good as Altera's sw?
48190: 02/10/13: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
48194: 02/10/14: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
48228: 02/10/14: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
48232: 02/10/14: Re: Why can Xilinx sw be as good as Altera's sw?
48235: 02/10/14: Re: Why can Xilinx sw be as good as Altera's sw?
48243: 02/10/15: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
48245: 02/10/15: Re: Why can Xilinx sw be as good as Altera's sw?
48285: 02/10/15: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
48311: 02/10/16: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
48371: 02/10/16: Re: Why can Xilinx sw be as good as Altera's sw?
48449: 02/10/17: Re: Why can Xilinx sw be as good as Altera's sw?
48535: 02/10/19: Re: Size of configuration bitstream for xcv50 (xilinx)
48597: 02/10/21: Re: Size of configuration bitstream for xcv50 (xilinx)
52589: 03/02/14: Re: JBits
54681: 03/04/16: Re: Selling CPU cores
54726: 03/04/16: Re: Selling CPU cores
57207: 03/06/25: Re: GAL16V8 reverse compilation
57277: 03/06/26: Re: content of a LUT
57279: 03/06/26: Re: Free PAL synth tools (ABEL, PALASM, VHDL, etc.)?
58050: 03/07/13: Re: Virtex Bitstream verification
60254: 03/09/09: Re: CMOS camera w/ USB2 -- crazy?
60374: 03/09/11: Re: CMOS camera w/ USB2 -- crazy?
60710: 03/09/19: Re: Xilinx
60852: 03/09/23: Re: Regarding XC6216
60854: 03/09/23: Re: Regarding XC6216
60856: 03/09/24: Re: FPGA implementation in (V)HDL
60897: 03/09/24: Re: Regarding XC6216
60909: 03/09/25: Re: FPGA implementation in (V)HDL
Neil Glenn Jacobson:
17695: 99/08/24: Re: JTAG 1149 Info
28249: 01/01/03: Re: Jedec to tms/tdi wiggles
37535: 01/12/13: Re: svf files in webpack 4.1
37536: 01/12/13: Re: svf files in webpack 4.2
38293: 02/01/10: Re: Boundary Scn, Bist
38950: 02/01/28: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
42123: 02/04/16: Re: Xilinx JTAG C Source
42126: 02/04/16: Re: Xilinx JTAG C Source (Again)
43385: 02/05/20: Re: Using Impact with XCR5064 coolrunner?
47365: 02/09/24: Re: Spartan II JTAG reconfiguration bug - workaround
49770: 02/11/20: Re: Xilinx programming and PCI printer port
49955: 02/11/26: Re: problems programming/verifying fpga using ISE 5.1
49957: 02/11/26: Re: Xilinx programming and PCI printer port
56038: 03/05/27: Re: Xilinx Spartan download with Parallel III cable
56093: 03/05/28: Re: Xilinx Spartan download with Parallel III cable
57204: 03/06/25: Re: ERROR:iMPACT:583
57349: 03/06/27: Re: ERROR:iMPACT:583
57921: 03/07/09: Re: create JAM-File for Xilinx device
57922: 03/07/09: Re: wired downloading bitstream to spartan2
58186: 03/07/16: Re: JTAG and Xilinx
60511: 03/09/15: Re: Reconfiguration standards
63022: 03/11/12: Re: Impact, SVF, assumed TCK frequency?
63401: 03/11/20: Re: Xilinx legacy situation
63446: 03/11/21: Re: Xilinx legacy situation
64882: 04/01/15: Re: Altera Cyclone Programming device programming
70218: 04/06/09: Re: IR_CAPTURE fail on Virtex2
70219: 04/06/09: Re: ISE 4.2i Impact and Windows XP not working
70309: 04/06/11: Re: Xilinx Parallel Cable IV vs. Linux
70312: 04/06/11: Re: Xilinx Parallel Cable IV vs. Linux
70313: 04/06/11: Re: Xilinx Parallel Cable IV vs. Linux
70360: 04/06/14: Re: Xilinx .bit to .svf...
70365: 04/06/14: Re: Xilinx Parallel Cable IV vs. Linux
70408: 04/06/15: Re: Xilinx Parallel Cable IV vs. Linux
70529: 04/06/18: Re: compressing Xilinx bitstreams
70593: 04/06/21: Re: Xilinx Parallel Cable IV vs. Linux
70596: 04/06/21: Re: Xilinx Parallel Cable IV vs. Linux
71921: 04/08/03: Re: ChipScope Pro Loading Memory
72359: 04/08/16: Re: Usercode in bit/mcs file
72432: 04/08/18: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72433: 04/08/18: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72439: 04/08/18: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72465: 04/08/19: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72467: 04/08/19: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72532: 04/08/23: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72667: 04/08/27: Re: Impact vs. Linux RedHat Linux
73074: 04/09/13: Re: New to FpGa ; At configuring the device error cmes
73139: 04/09/14: Re: New to FpGa ; At configuring the device error cmes
73788: 04/09/29: Re: Read back FPGA configuration
76358: 04/11/30: Re: System ACE programming solution?
76444: 04/12/02: Re: Configuring FPGA & PROM with serial Cable (DB9)
77386: 05/01/05: Re: iMPACT 5.1i w/Parallel Cable
77987: 05/01/21: Re: X-checker Pod : Problem w/ X-checker and Win2000
77988: 05/01/21: Re: SystemACE and Jtag
78149: 05/01/25: Re: Platform Cable USB on WinXP with SP2
78151: 05/01/25: Re: Impact errors programing V4LX25
78219: 05/01/26: Re: Impact errors programing V4LX25
78221: 05/01/26: Re: Impact errors programing V4LX25
79926: 05/02/25: Re: SVF file
82025: 05/04/05: Re: FPGA with 2 JTAG ports
82091: 05/04/06: Re: FPGA with 2 JTAG ports
83084: 05/04/22: Re: Xilinx Impact in Linux 2.6.x
83539: 05/05/02: Re: Performing Readback from Impact
83540: 05/05/02: Re: writing with impact to eeprom
83552: 05/05/02: Re: Performing Readback from Impact
83580: 05/05/03: Re: Performing Readback from Impact
85726: 05/06/14: Re: JTAG programming: JAM files versus ISC (IEEE1532) files
88665: 05/08/24: Re: what is the difference between "configuring" and "programming"?
89324: 05/09/12: Re: Which JTAG cable for Xilinx & Linux?
90947: 05/10/25: Re: System ACE equivalent for CPLDs
91043: 05/10/27: Re: System ACE equivalent for CPLDs
91073: 05/10/28: Re: System ACE equivalent for CPLDs
91154: 05/10/31: Re: System ACE equivalent for CPLDs
93158: 05/12/14: Re: J Tag Protocol
93690: 05/12/28: Re: ERROR:iMPACT:585
94791: 06/01/17: Re: Just want to program Xilinx CPLD device from JEDEC file using
95089: 06/01/20: Re: Just want to program Xilinx CPLD device from JEDEC file using
94792: 06/01/17: Re: Just want to program Xilinx CPLD device from JEDEC file using
95517: 06/01/23: Re: Just want to program Xilinx CPLD device from JEDEC file usingISE8.1
95623: 06/01/24: Re: ISE8.1 Service Packs Schedule
96001: 06/01/27: Re: Impact 8.1 problems with non xilinx device in chain
96010: 06/01/27: Re: Impact 8.1 problems with non xilinx device in chain
96018: 06/01/27: Re: Impact 8.1 problems with non xilinx device in chain
97458: 06/02/22: Re: JTAG problem
97616: 06/02/24: Re: JTAG problem
98829: 06/03/16: Re: Using the IEEE Std 1532
99213: 06/03/21: Re: Xilinx programming cable; Linux notebook w/o parallel port; Am
99302: 06/03/22: Re: this JTAG thing is a joke
108288: 06/09/07: Re: Xilinx Impact Cable Drivers for 64-bit Linux?
111712: 06/11/08: Re: Platform USB Cable and Windows XP Pro x64
126639: 07/11/28: Re: Xilinx XChecker cable supported until which version?
Neil Hamilton:
1012: 95/04/13: Any way to go from routed LCA to logic description?
Neil Judell:
24608: 00/08/15: Re: Non-disclosures in job interviews
Neil Nelson:
24810: 00/08/19: Re: Non-disclosures in job interviews, Round One
24846: 00/08/20: Re: Non-disclosures in job interviews, Round One
24884: 00/08/21: Re: Non-disclosures in job interviews, Round One
24930: 00/08/22: Re: Non-disclosures in job interviews, Round One
24951: 00/08/22: Re: Non-disclosures in job interviews, Round One
24960: 00/08/22: Re: Non-disclosures in job interviews, Round One
24982: 00/08/23: Re: Non-disclosures in job interviews, Round Two
24988: 00/08/23: Re: Non-disclosures in job interviews, Round One
24989: 00/08/23: Re: Non-disclosures in job interviews, Round One
25014: 00/08/23: Re: Non-disclosures in job interviews, Round Two
25027: 00/08/24: Re: Non-disclosures in job interviews, Round Two
25135: 00/08/27: Re: Non-disclosures in job interviews, Round Two
25203: 00/08/30: Re: Non-disclosures in job interviews, Round One
25214: 00/08/30: Re: Non-disclosures in job interviews, Round One
25237: 00/08/31: Re: Non-disclosures in job interviews, Round One
25037: 00/08/24: Re: Non-disclosures in job interviews, Round Two
25040: 00/08/24: Re: Non-disclosures in job interviews, Round Two
25081: 00/08/25: Re: Non-disclosures in job interviews, Round Two
25123: 00/08/26: Re: Non-disclosures in job interviews, Round Two
25247: 00/09/01: Re: Non-disclosures in job interviews, Round One
Neil Stainton:
34680: 01/09/03: How do I configure Altera Apex 20K via JTAG?
45064: 02/07/11: Re: FPGA/CPLD Decision help?
46448: 02/08/30: Re: Handel-C data widths
Neil Steiner:
43598: 02/05/25: Documentation on XDL reports?
95911: 06/01/26: Re: So what happened to JHDLBits?
95981: 06/01/27: Re: So what happened to JHDLBits?
110725: 06/10/20: System ACE and remotely reconfiguring an XUP board?
110738: 06/10/20: Re: System ACE and remotely reconfiguring an XUP board?
110741: 06/10/20: Re: System ACE and remotely reconfiguring an XUP board?
110959: 06/10/25: Semantics or examples for Xilinx xgpio driver under Linux?
111004: 06/10/26: Re: Semantics or examples for Xilinx xgpio driver under Linux?
114493: 07/01/17: Behavior of REV input in Virtex2 flops?
114612: 07/01/20: Correction for hwicap_v1_00_a code
114618: 07/01/20: Re: edif format
114670: 07/01/22: Re: Correction for hwicap_v1_00_a code
114740: 07/01/23: Re: FPGA damage from bad bitstream
114741: 07/01/23: Re: FPGA damage from bad bitstream
114742: 07/01/23: Re: FPGA damage from bad bitstream
114743: 07/01/23: Re: FPGA damage from bad bitstream
115823: 07/02/21: OPB IPIF: write to DIER causing bus timeout
117151: 07/03/23: Re: OPB IPIF: write to DIER causing bus timeout
117535: 07/04/03: Re: Dynamic Reconfig
117644: 07/04/05: Re: suitability of systolic architecture on FPGA
117648: 07/04/05: Re: suitability of systolic architecture on FPGA
119452: 07/05/19: Re: Visio logic symbols
119791: 07/05/25: Re: ML505 : beginners problems
120152: 07/06/01: Re: using ICAP with the ML310
122490: 07/07/28: Restricting XST parameter widths from .mpd files?
122537: 07/07/30: Re: Restricting XST parameter widths from .mpd files?
123566: 07/08/30: Re: Partial reconfiguration using ICAP
125187: 07/10/17: Reason for LUT1_L buffer insertion in Synplify EDIFs?
125206: 07/10/17: Re: Reason for LUT1_L buffer insertion in Synplify EDIFs?
125243: 07/10/18: Re: Dynamic Reconfiguration books
125296: 07/10/19: Re: Dynamic Reconfiguration books
125317: 07/10/20: Protecting slices from GLOBAL_LOGIC0/GLOBAL_LOGIC1 usage?
125337: 07/10/22: Re: Protecting slices from GLOBAL_LOGIC0/GLOBAL_LOGIC1 usage?
127193: 07/12/13: `ifdef XST?
137015: 08/12/18: FPGA partial/catastrophic failure mode question
137025: 08/12/19: Re: FPGA partial/catastrophic failure mode question
137026: 08/12/19: Re: FPGA partial/catastrophic failure mode question
137027: 08/12/19: Re: FPGA partial/catastrophic failure mode question
137030: 08/12/19: Re: FPGA partial/catastrophic failure mode question
140044: 09/04/24: About those TIEOFF primitives ...
140706: 09/05/22: Unable to run 'xdl -ncd2xdl' on RHEL 5.3 in ISE 10.1
140720: 09/05/22: Re: Unable to run 'xdl -ncd2xdl' on RHEL 5.3 in ISE 10.1
140732: 09/05/22: Re: Unable to run 'xdl -ncd2xdl' on RHEL 5.3 in ISE 10.1
140970: 09/06/01: Maximum tilemap size for Virtex6 devices?
140980: 09/06/01: Re: Maximum tilemap size for Virtex6 devices?
145052: 10/01/22: ChipScope scripting for batch data collection?
151918: 11/06/03: Looking for bitgen Virtex7 and Kintex7 support
151924: 11/06/04: Re: Looking for bitgen Virtex7 and Kintex7 support
153365: 12/02/07: Life after XDL
155492: 13/07/01: Problems with Spartan6 CRC calculation
155499: 13/07/03: Re: Problems with Spartan6 CRC calculation
155508: 13/07/09: Re: Problems with Spartan6 CRC calculation
Neil Zanella:
59034: 03/08/06: FPGAs: basic question: two-level AND-OR vs. two-level OR-AND
neil3w@gmail.com:
122870: 07/08/09: what the AC exactly short for here...
Neill A:
84440: 05/05/19: Actel Designer on Linux
85061: 05/06/03: Re: Actel Designer on Linux
86624: 05/07/01: Re: init ProASIC3 Ram from spi
87941: 05/08/04: Re: Porting Actel code
89483: 05/09/16: Version Control Software
90184: 05/10/06: Re: ACTEL ProASIC plus mixed-voltage I/O macro's in Designer 6.2 ....?
90188: 05/10/06: Re: Actel Libero upgrade - problem with clk pin - Synplify
90195: 05/10/06: Re: ACTEL ProASIC plus mixed-voltage I/O macro's in Designer 6.2 ....?
90234: 05/10/07: Re: Actel Libero upgrade - problem with clk pin - Synplify
Neill Arnell:
148627: 10/08/10: Multiple builds with different top-level generic
153353: 12/02/06: Re: Xilinx Artix-7 availability
Neill Clift:
20533: 00/02/13: Using a programable logic device to search a huge number field
<neilla@ewst.co.uk>:
82944: 05/04/20: Re: actel blockram the easy way?
<neilla@pipstechnology.co.uk>:
121219: 07/06/28: USB JTAG Programming
121248: 07/06/29: Re: USB JTAG Programming
121249: 07/06/29: Re: USB JTAG Programming
124203: 07/09/14: Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
124480: 07/09/24: Re: Answer: maximum number of state machines in a current chip: > 500k
125217: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
126730: 07/11/30: Re: Global Reset using Global Buffer
134222: 08/07/31: Re: ISE new file wizard
137646: 09/01/26: Re: dual MIG controller on spartan 3A DSP
137670: 09/01/27: Re: dual MIG controller on spartan 3A DSP
<neli_dimitrova@my-deja.com>:
22854: 00/05/27: Fitting problems with WebPack
Nelson Soria:
1237: 95/05/20: Re: Can the X4010 replace a X4003 ?
1659: 95/08/11: Re: VHDL/FPGAs/PLDs help
1699: 95/08/17: Re: FPGAs with embedded RAM
Nelson Wang:
28909: 01/01/29: compatible issue
Nelson Willhite:
2150: 95/10/20: Re: Chip Express Expreiences Wanted
nemesis:
98795: 06/03/16: Using the IEEE Std 1532
Nemesis:
80838: 05/03/12: Xilinx ISE and IP cores
80984: 05/03/15: Re: Xilinx ISE and IP cores
81092: 05/03/17: Re: Xilinx ISE and IP cores
81218: 05/03/19: FIR choice
81259: 05/03/20: Re: FIR choice
81384: 05/03/22: Importing waveforms from ASCII files
81385: 05/03/22: Re: FIR choice
81386: 05/03/22: Re: FIR choice
81480: 05/03/24: Re: FIR choice
81848: 05/04/02: ModelSim XE and WindowsXP
81870: 05/04/03: Re: ModelSim XE and WindowsXP
81929: 05/04/04: Re: ModelSim XE and WindowsXP
82090: 05/04/06: Re: ModelSim XE and WindowsXP
82439: 05/04/12: Error synthesizing two Xilinx MacFir core
82657: 05/04/15: Re: Importing waveforms from ASCII files
86003: 05/06/20: Xilinx MacFir5.0 - Block Ram requirenments
86042: 05/06/20: Re: Xilinx MacFir5.0 - Block Ram requirenments
86069: 05/06/21: Re: Xilinx MacFir5.0 - Block Ram requirenments
86224: 05/06/23: Re: Xilinx MacFir5.0 - Block Ram requirenments
89446: 05/09/15: ISE 7.1 service packs
90924: 05/10/25: Xilinx FIFO Generator: FIFO Length
90928: 05/10/25: Re: Xilinx FIFO Generator: FIFO Length
90963: 05/10/26: Re: Xilinx FIFO Generator: FIFO Length
90964: 05/10/26: Re: Xilinx FIFO Generator: FIFO Length
90966: 05/10/26: Re: Xilinx FIFO Generator: FIFO Length
90977: 05/10/26: Re: Xilinx FIFO Generator: FIFO Length
131232: 08/04/16: Virtex 4 DCM problem
131235: 08/04/16: Re: Virtex 4 DCM problem
131238: 08/04/16: Re: Virtex 4 DCM problem
131297: 08/04/18: Re: Virtex 4 DCM problem
131788: 08/05/02: Virtex4 Output Pins during Configuration
131801: 08/05/02: Re: Virtex4 Output Pins during Configuration
133648: 08/07/08: What's wrong with this Virtex4 DCM?
133838: 08/07/16: Re: What's wrong with this Virtex4 DCM?
136818: 08/12/07: ISE doesn't work after a crash
136821: 08/12/07: Re: ISE doesn't work after a crash
136834: 08/12/08: Re: ISE doesn't work after a crash
136839: 08/12/08: Re: ISE doesn't work after a crash
136840: 08/12/08: Re: ISE doesn't work after a crash
136853: 08/12/08: Re: ISE doesn't work after a crash
136854: 08/12/09: Re: ISE doesn't work after a crash
137350: 09/01/10: Virtex 4 optimization strategy
137366: 09/01/12: Xilinx Area Group Constraint Usage
137373: 09/01/12: Re: Xilinx Area Group Constraint Usage
137384: 09/01/13: Re: Xilinx Area Group Constraint Usage
137501: 09/01/21: ISE 8.2 Guided PAR ... Does it work?
141794: 09/07/09: Generating a negated clock
141805: 09/07/10: Re: Generating a negated clock
141862: 09/07/14: Re: Generating a negated clock
141907: 09/07/16: Re: Generating a negated clock
141940: 09/07/18: Re: Generating a negated clock
Nemo:
30886: 01/05/02: Re: Shannon Capacity
30920: 01/05/03: Re: Shannon Capacity
30946: 01/05/04: Re: Shannon Capacity
30947: 01/05/04: Re: Shannon Capacity
30949: 01/05/04: Re: Shannon Capacity
30991: 01/05/08: Re: Shannon Capacity
31020: 01/05/09: Shannon Capacity - An Apology
31025: 01/05/09: Re: Shannon Capacity - An Apology
31055: 01/05/10: Re: Shannon Capacity - An Apology
31056: 01/05/10: Re: Shannon Capacity
31057: 01/05/10: Re: Shannon Capacity - An Apology
31070: 01/05/10: Re: Shannon Capacity - An Apology
nemo:
9858: 98/04/09: Re: Xilinx XACT 6.01 crack
138407: 09/02/20: Re: VHDL long elsif state machine
Nenad:
87260: 05/07/20: Re: ChipScope Pro : how to set up trigger
87327: 05/07/21: Re: ChipScope Pro : how to set up trigger
87328: 05/07/21: DDR SDRAM on ML401
87379: 05/07/22: Re: DDR SDRAM on ML401
87700: 05/07/28: Re: ChipScope Pro : how to set up trigger
87734: 05/07/29: Re: ChipScope Pro : how to set up trigger
87782: 05/08/01: Re: ChipScope Pro : how to set up trigger
87912: 05/08/03: Re: ML401 JTAG configuration problem
87962: 05/08/04: Re: ML401 JTAG configuration problem
Nenad Crnko:
12473: 98/10/13: RE: NFX780, where to get?
Neo:
77649: 05/01/13: fpga board with onboard 2 ethernet PHY chips?
79010: 05/02/10: Re: doubt on configuring FPGA
79012: 05/02/11: Re: ISE versus Modelsim inconsistency and attribute definition
79244: 05/02/15: Re: wireload model./custom wl creation
79247: 05/02/15: Re: ISE:ERROR:Xst:829: Constant Value expected for Generic 'U'?
80138: 05/03/01: Re: Help with XST warnings (2)
80272: 05/03/02: Re: Help with XST warnings (2)
80336: 05/03/03: Re: Displays an image in the XS Board RAM on a VGA monitor
80558: 05/03/08: Re: Hierarchical Synchronous Design
80560: 05/03/08: Re: Good, affordable verilog simulator
80683: 05/03/09: Re: Good, affordable verilog simulator
80684: 05/03/09: Re: ethernet core on a xc3s200
80687: 05/03/09: Re: Xilinx vs Altera high-end solutions
80751: 05/03/10: Re: low speed FIR filter in FPGA
80753: 05/03/10: Re: New in C to RTL
80754: 05/03/10: Re: conditional port generation in Verilog 2001
80895: 05/03/14: Re: I need systemc.h
81757: 05/03/31: WTB NIOS-II kit
81759: 05/03/31: Re: WTB NIOS-II kit
81762: 05/03/31: Re: WTB NIOS-II kit
81765: 05/03/31: Re: WTB NIOS-II kit
81948: 05/04/05: Re: Reverse engineering ASIC into FPGA
81956: 05/04/05: Re: Need Help
82121: 05/04/06: Re: Reverse engineering ASIC into FPGA
83208: 05/04/25: Re: VHDL Analysis Tool (vhdlarch 0.1.0)
83514: 05/05/01: Re: one hot decoder
83523: 05/05/02: Re: Reasonable Entry Level Dev. Board....
83743: 05/05/06: Spartan-3 boards comparison
83928: 05/05/09: Re: IP core supply
84001: 05/05/11: An FPGA eval board at $49!!
84009: 05/05/11: Re: An FPGA eval board at $49!!
84245: 05/05/16: Re: floorplanning
84312: 05/05/17: Re: Tristate-Master-Slave testbench description
84449: 05/05/19: Re: Why do VHDL gate level models simulate slower than verilog
84520: 05/05/20: Re: FFT with FPGA
84528: 05/05/20: Re: Bullshit Achieves Literary Status
84529: 05/05/20: Re: A Short Pulse Catcher
84611: 05/05/23: Re: FSM stops working
84652: 05/05/24: Re: Simulation of rocket IO in virtex 2 pro
85784: 05/06/15: Deisgn partitioning issues
85791: 05/06/16: Re: LUT, how to?
85845: 05/06/16: Re: Deisgn partitioning issues
88394: 05/08/17: Re: Evolutionary VHDL code example
88434: 05/08/18: Re: Synthesis : HowTo Preserve FSM encodings
88524: 05/08/21: Re: Quartus performance penalty of {a,b} <= {c,d} vs. a<=c; b<=d;
88525: 05/08/21: Re: real constants in XST
88526: 05/08/21: Re: Verilog translation
88565: 05/08/22: Re: Good SystemC tutorials or books?
88685: 05/08/25: Re: Library of eBooks on FPGA's and other programming stuff
113306: 06/12/10: Re: @(posedge clk)
115050: 07/01/29: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
Neo Wei Thiam:
25886: 00/09/24: FPGA for PCM coded DTMF transmission?
28904: 01/01/29: Is it a timing constraint problem?
29537: 01/02/25: Re: Soldering and Unsoldering PQFP by hand ...
Neo WT:
29426: 01/02/20: Virtex E:Sample price
neoh:
85398: 05/06/08: Re: Boot problem Stratix Kit EP1S25
Neon John:
159883: 17/04/14: Re: fan speed controller
159887: 17/04/15: Re: fan speed controller
159888: 17/04/15: Re: fan speed controller
neoo:
157256: 14/11/08: Re: USB PHY recommendations
157257: 14/11/08: Re: USB PHY recommendations
neosis:
149349: 10/10/18: Xilinx ISE 12.3 : library simprim problem
149367: 10/10/19: Re: Xilinx ISE 12.3 : library simprim problem
Nesrine:
44001: 02/06/08: RC 1000 board and Handel-c
44508: 02/06/21: Baugh-Wooley multiplier using Handel-C
Nestor:
20715: 00/02/18: Generating a Higher Frequency Clock from a Lower One in FPGA
20716: 00/02/18: Predictable Delays of Altera's Fast Interconnect for DLL/PLL
21002: 00/03/02: DLL Details of Xilinx Virtex FPGAs
21024: 00/03/03: Re: DLL Details of Xilinx Virtex FPGAs
21840: 00/04/03: Re: Pipelined ALTERA LPMs - where are the registers introduced?
22066: 00/04/17: Errors when synthesizing using generics but not during synthessi
22153: 00/04/27: Instantiating and Compiling Altera LPM Macros with Synplify
22209: 00/05/01: Re: Instantiating and Compiling Altera LPM Macros with Synplify
22889: 00/05/30: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22890: 00/05/30: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22892: 00/05/30: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22893: 00/05/30: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22894: 00/05/30: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22895: 00/05/30: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22896: 00/05/30: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
23176: 00/06/16: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
24742: 00/08/17: Accessing internal signals and ports for writing to a file using testbench
25075: 00/08/25: Problems Fitting Design When Inserting More Than One Internal Global Buffer...
25076: 00/08/25: Re: Accessing internal signals and ports for writing to a file using testbench
25374: 00/09/08: Numerically-Controlled Crystal Oscillator (NCXO) or Digitally-Controlled Crystal Oscillator (DCXO) Designs
25488: 00/09/12: Re: Accessing internal signals and ports for writing to a file using testbench
25489: 00/09/12: Re: Numerically-Controlled Crystal Oscillator (NCXO) or Digitally-Controlled Crystal Oscillator (DCXO) Designs
25490: 00/09/12: Re: Numerically-Controlled Crystal Oscillator (NCXO) or Digitally-Controlled Crystal Oscillator (DCXO) Designs
Nestor C.:
7745: 97/10/10: Re: XILINX and ALTERA development boards
16554: 99/05/27: Pipeline/Delay Stages in a Feedback Loop
23152: 00/06/16: Designing a narrowband bandpass filter to pass a tone (analog domain)
Nestor Caouras:
7679: 97/10/02: XILINX and ALTERA development boards
7680: 97/10/02: XILINX and ALTERA development boards
7681: 97/10/02: XILINX and ALTERA development boards
7932: 97/10/31: Division & Multiplication (unsigned/signed) - Need HELP
8561: 98/01/08: Simulation errors when using Synopsys Design Ware/GTECH components
10178: 98/05/01: Creating a clock with a clock enable
10297: 98/05/10: Re: Creating a clock with a clock enable
11977: 98/09/22: How to reduce ringing/ground bounce from FPGA output pin?
12029: 98/09/24: Re: How to reduce ringing/ground bounce from FPGA output pin?
12238: 98/10/06: USAGE of XILINX "FROM:TO" for VHDL and IMPLEMENTATION
12241: 98/10/06: Re: USAGE of XILINX "FROM:TO" for VHDL and IMPLEMENTATION
12275: 98/10/07: Degradation of results from Xilinx F1.3 -> F1.4 -> F1.5
12276: 98/10/07: Degradation of results from Xilinx F1.3 -> F1.4 -> F1.5 (MORE INFO)
12288: 98/10/07: Re: Degradation of results from Xilinx F1.3 -> F1.4 -> F1.5
12314: 98/10/08: Re: Degradation of results from Xilinx F1.3 -> F1.4 -> F1.5
12315: 98/10/08: Re: Degradation of results from Xilinx F1.3 -> F1.4 -> F1.5
12564: 98/10/16: Re: Degradation of results from Xilinx F1.3 -> F1.4 -> F1.5
21740: 00/03/30: Pipelined ALTERA LPMs - where are the registers introduced?
<nestor@ece.concordia.ca>:
20745: 00/02/20: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
22866: 00/05/28: Design of Phase-Locked Loop (PLL) - 2 alternatives
<nestor@stansync.com>:
20723: 00/02/19: Re: Predictable Delays of Altera's Fast Interconnect for DLL/PLL
20724: 00/02/19: Re: Predictable Delays of Altera's Fast Interconnect for DLL/PLL
nestorj@lafayette.edu:
97386: 06/02/21: Relative placement constraints in Xilinx ISE w/ Verilog
<net9147@yahoo.com>:
28862: 01/01/26: 6845
Netoko Young:
113521: 06/12/15: Re: Spartan-3A launched
113556: 06/12/16: Re: Spartan-3A launched
120726: 07/06/14: What is LatticeSC implementation of Virtex-4 ISERDES and OSERDES
121452: 07/07/04: LVDS via Emulation
121453: 07/07/04: Re: LVDS via Emulation
netpit:
80553: 05/03/08: malloc doesn't work when I use OCM (with Virtex II Pro and PPC405)
80616: 05/03/09: Re: malloc doesn't work when I use OCM (with Virtex II Pro and PPC405)
81283: 05/03/21: Re: malloc doesn't work when I use OCM (with Virtex II Pro and PPC405)
<netpit@gmail.com>:
85639: 05/06/13: Re: PowerPC crash down
Netscape User:
25937: 00/09/26: Re: CORDIC COS/SIN with FPGA implementation
25958: 00/09/27: Synplicity vs Xilinx FPGA Express
26030: 00/09/30: Re: Altera FPGA experts needed
26031: 00/09/30: Xilinx Student Edition 2.1i first impressions
26046: 00/10/01: Re: Xilinx Student Edition 2.1i first impressions
26047: 00/10/01: GPIO on AVNET Xilinx FPGA board? any cables?!?
26094: 00/10/03: Re: Xilinx Student Edition 2.1i first impressions
26095: 00/10/03: Re: GPIO on AVNET Xilinx FPGA board? any cables?!?
26325: 00/10/11: Re: Xilinx, Altera stocks take dumps!
26601: 00/10/21: Re: Virtex-E and ADC
26749: 00/10/26: Xilinx Spartan2 and VirtexE availability
NetWalker:
13476: 98/12/04: VHDL/AHDL algorithm for 28f010 or compable
network lines:
67997: 04/03/24: cheapest & best FPGA???
<networkfabulous@gmail.com>:
119028: 07/05/09: ISE 9.1 Hierarchy Problem
119097: 07/05/11: Re: ISE 9.1 Hierarchy Problem
neu:
85692: 05/06/14: Re: Gated clock question
Neurotech GmbH:
9142: 98/02/24: PLL design with Xilinx 4kseries
Neven Colak:
67917: 04/03/22: Altera and PCI-X
68075: 04/03/25: ASYNC SRAM selection
<neverthelessless@gmail.com>:
160591: 18/05/08: Re: verilog reg usage
Neville Miles:
3540: 96/06/18: JTAG Boundary Scan
Nevin:
79341: 05/02/17: FPGA Hardware/Cell Diagnostics
Nevo:
105507: 06/07/24: Connecting two buses in Xilinx ISE
105589: 06/07/26: Re: Combining Schematic and VHDL code in Webpack 8.1 ??
105693: 06/07/28: "This design element is inferred rather than instantiated" (newbie)
105694: 06/07/28: Re: "This design element is inferred rather than instantiated" (newbie)
105707: 06/07/28: Can I get 840HZ from a Xilinx Spartan-3's DCM? Phase locked?
105724: 06/07/30: Re: Can I get 840HZ from a Xilinx Spartan-3's DCM? Phase locked?
105725: 06/07/30: Re: "This design element is inferred rather than instantiated" (newbie)
106255: 06/08/10: Re: Simple code to check out Spartan3 starter kit?
106412: 06/08/13: Maximum Current Draw of FPGA
106415: 06/08/13: Re: Maximum Current Draw of FPGA
107365: 06/08/27: Quartus software and dual-purpose pins
107379: 06/08/28: Spartan 3 and 5V input
107382: 06/08/28: Re: Spartan 3 and 5V input
107384: 06/08/28: Re: Spartan 3 and 5V input
107671: 06/08/31: Re: Undergrad project-8051 specifications??
109217: 06/09/22: Configuration of Cyclone devices
112480: 06/11/23: Altera configuration with microcontroller
112588: 06/11/25: Re: Altera configuration with microcontroller
113257: 06/12/09: JTAG programming of Altera Cyclone and CONF_DONE
113258: 06/12/09: Current programming hardware does not support Active Serial programming mode
113345: 06/12/11: Re: JTAG programming of Altera Cyclone and CONF_DONE
125461: 07/10/26: Power supply filter capacitors
125478: 07/10/26: Re: Power supply filter capacitors
125530: 07/10/27: Re: Power supply filter capacitors
125531: 07/10/27: Re: Power supply filter capacitors
125533: 07/10/27: Re: Power supply filter capacitors
125542: 07/10/28: Re: Power supply filter capacitors
125558: 07/10/29: Re: Power supply filter capacitors
125559: 07/10/29: Re: Power supply filter capacitors
125561: 07/10/29: Re: Power supply filter capacitors
125562: 07/10/29: Re: Power supply filter capacitors
125765: 07/11/04: Re: Power supply filter capacitors
126426: 07/11/22: Unable to scan device chain
126443: 07/11/22: Re: Unable to scan device chain
126444: 07/11/22: Re: Unable to scan device chain
126497: 07/11/25: Re: Unable to scan device chain
126498: 07/11/25: Re: Unable to scan device chain
126499: 07/11/25: Converting a ByteBlasterMV into a ByteBlaster II?
New User:
15140: 99/03/09: Startup issues with 24c04 eeprom and I2C interface
new.online.de:
85006: 05/06/02: Re: need a book: Hilbert transform
newb:
47295: 02/09/22: fpga eval kits
47405: 02/09/24: Re: fpga eval kits
49167: 02/11/03: pc to fpga cpu commands
53694: 03/03/20: Re: Using FPGAs as coprocessors in a PC
newbab22:
147306: 10/04/22: OFFSET and OFFSET out
newbie:
55774: 03/05/20: about simulation
55793: 03/05/20: Re: about simulation
62835: 03/11/10: ASIC vs FPGA
newdevkit:
53625: 03/03/18: usb spartan dev board
53626: 03/03/18: usb spartan prototype
newgroups:
72938: 04/09/08: Re: PCI Noise
Newhand:
64292: 03/12/25: How to get first bit '0' position in certain register?
64302: 03/12/26: Re: Anyone has the AMD flash AM29LV800B verilog model?
newman:
36252: 01/11/03: Re: spartan synthesis with synopsis
36282: 01/11/05: Re: spartan synthesis with synopsis
37925: 01/12/25: Re: Look for FPGA Starterkit
37946: 01/12/26: Re: Look for FPGA Starterkit
37947: 01/12/26: Re: Innoveda Speedwave vs. Modelsim?
37979: 01/12/28: Re: Innoveda Speedwave vs. Modelsim?
38150: 02/01/07: Re: WARNING
38167: 02/01/07: Re: I2C/SPI implementation on FPGA
38560: 02/01/17: Re: Leonardo + Xilinx tools help
38582: 02/01/18: Re: Coregen Half-Band FIR filter implemenation does not work
38653: 02/01/20: Re: help me!
38691: 02/01/22: Re: help me!
38692: 02/01/22: Re: Q: can ROM content affect logic syn result
38799: 02/01/25: Re: XC2V10000 still on the Xilinx roadmap?
38809: 02/01/25: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38870: 02/01/26: Re: Coregen Half-Band FIR filter implemenation does not work
38889: 02/01/27: Re: Simple shift register not working (update)
38965: 02/01/28: Re: Simple shift register not working (update)
39029: 02/01/30: RLOCS with combinatorial logic
39142: 02/02/01: Re: www.easics.com
39202: 02/02/04: Re: MUX seelction question
39272: 02/02/05: Re: DCM relationship question
39556: 02/02/13: Re: Making Altera development quicker
39621: 02/02/14: Re: Modelsim questions
39791: 02/02/19: Re: Coregen Half-Band FIR filter implemenation does not work
39793: 02/02/19: Re: Faster designs
40007: 02/02/24: Re: init RAM in VirtexII
40482: 02/03/07: Re: How can I install Xilinx ISE 4.1i under Linux?
41705: 02/04/05: Re: Schematic Stuff
42885: 02/05/06: Re: State Machine output assignment
43692: 02/05/29: Re: place and route simulation time
43746: 02/05/31: Re: LFSR with 2^n instead of (2^n)-1
43894: 02/06/05: Re: OFFSET timing contraints
43994: 02/06/07: Re: Xilinx ISE BaseX... What is it?
44067: 02/06/11: Re: programming xc3030 using atmel's ATDH2225 programmer cable
44293: 02/06/16: Re: core generator / where is it?
44346: 02/06/18: Re: impacts batch mode....
44349: 02/06/18: Re: lfsr and implementation and alpha
44352: 02/06/18: Re: what's the use of BlockRAM
44456: 02/06/20: Re: How to get Unisims netlist?
44474: 02/06/20: Re: How to get Unisims netlist?
44559: 02/06/23: Re: Clock enable & Synplify 7.1
44562: 02/06/23: Re: Clock enable & Synplify 7.1
44597: 02/06/24: Re: Clock enable & Synplify 7.1
44607: 02/06/24: Re: Clock enable & Synplify 7.1
44608: 02/06/24: Re: Will this clock divider be good on hardware?
44612: 02/06/24: Re: Will this clock divider be good on hardware?
44685: 02/06/26: Re: Clock enable & Synplify 7.1
44719: 02/06/27: Re: Clock enable & Synplify 7.1
44720: 02/06/27: Re: clock skew in quartus, not in maxplus
45080: 02/07/11: Re: ModelSim License problem
56282: 03/06/02: Re: Need help with Xilinx ISE
75214: 04/10/29: Re: xilinx edk 6.3
75216: 04/10/29: Re: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps.
75267: 04/10/31: Re: XST: suppressing incorrect optimizations in VHDL code
75292: 04/11/01: Re: XST: suppressing incorrect optimizations in VHDL code
75337: 04/11/02: Re: XST: suppressing incorrect optimizations in VHDL code
74542: 04/10/13: Re: simprim errors
74543: 04/10/13: Re: Flex10K10A, I2C, MultiVolt IO, pull-ups
74544: 04/10/13: Re: question about types in VHDL
74547: 04/10/13: Re: question about types in VHDL
74588: 04/10/14: Re: Tristate
74594: 04/10/14: Re: Tristate
74723: 04/10/17: Re: question about types in VHDL
75467: 04/11/06: Re: Jtag problem for Virtex II pro (XC2VP20-6FF896C).
75470: 04/11/06: Re: how to force DC to use a specific cell ?
75562: 04/11/09: Re: Jtag problem for Virtex II pro (XC2VP20-6FF896C).
75570: 04/11/09: Re: xilinx webpack simulation problem (latch in place of logic)
75655: 04/11/11: Re: digital analog conversion
75692: 04/11/12: Re: DDR Mux - how does it work?
79812: 05/02/24: Re: edk, chipscope_icon and chipscope_ila
79862: 05/02/25: Re: NiosII Vs MicroBlaze
80034: 05/02/28: Re: modelling Bi-directional address/data multiplexed bus
80060: 05/03/01: Re: FPGA interface to an asynchronous microcontroller memory bus
80222: 05/03/02: Re: sysACE load vs bootloader load of vxWorks on ML310
80285: 05/03/03: Re: sysACE load vs bootloader load of vxWorks on ML310
80857: 05/03/12: ISE build dependencies
80859: 05/03/12: Re: ISE build dependencies
Newman:
77998: 05/01/21: Re: Poblem with Xilinx ISE
78276: 05/01/27: Problem with XSysAce_SectorRead
79613: 05/02/21: Re: WYSIWYG option in xilinx webpack 6.3
79793: 05/02/24: Re: Spartan-3 Starter Kit supplier in the UK?
80054: 05/02/28: Re: FPGA interface to an asynchronous microcontroller memory bus
89125: 05/09/06: Partial vector range in instance warning
89135: 05/09/06: Re: Partial vector range in instance warning
89221: 05/09/08: Re: to use flash on the fpga board
89826: 05/09/27: Re: Sythesis software for Virtex-4
89877: 05/09/28: Re: Using 3rd Party FPGA flows and Xilinx
89948: 05/09/30: Re: Testbench using Modelsim/VHDL - simple signal generation problem
90010: 05/10/01: Re: I, Wish: I had an Spartan-3e NOW!
90013: 05/10/02: Re: ISE does not initialize the bitstream of a EDK project
90161: 05/10/05: Re: evaluation edk in Spartan-3 starter kit
90204: 05/10/06: Re: evaluation edk in Spartan-3 starter kit
90250: 05/10/07: Re: Xilinx WebPack and command line
90258: 05/10/07: Re: Xilinx IMPACT Problem... detects 101 unknown devices
90379: 05/10/11: Re: question: timing constraint for clock enable
90433: 05/10/12: Re: VHDL : Use concatenation on port mapping
91029: 05/10/27: Re: Optimizing a State Machine
91103: 05/10/29: Xilinx ML403 Virtex 4 IIC uses bitbang test?
91198: 05/11/01: Re: Xilinx ML403 Error 1 LED
91290: 05/11/02: Re: Xilinx trouble opening ml40x_emb_ref_xx
91815: 05/11/14: Re: downloading with XMD ?
91890: 05/11/15: Re: downloading with XMD ?
91952: 05/11/17: Re: ISE 6.2i strange behavior
92895: 05/12/08: Re: Simulating Post-Synthesis Model on Xilinx FPGA
93299: 05/12/19: Re: ERROR:Pack:1564: ML403 & Xilinx Platform Studio 7.1.02i
93346: 05/12/20: Re: real-time compression algorithms on fpga
94217: 06/01/08: Re: Virtex2 I/O state in configure phase
94232: 06/01/08: Re: Virtex2 I/O state in configure phase
94732: 06/01/17: Re: BRAM/XMD strangeness?
101625: 06/05/03: Re: Interfacing Spartan 3 board to PC parallel port??
101627: 06/05/03: Re: Interfacing Spartan 3 board to PC parallel port??
115441: 07/02/11: Re: EDK tri-state control
117814: 07/04/10: Re: System Generator pcore I/O performance results
117815: 07/04/10: Re: System Generator pcore I/O performance results
117902: 07/04/12: Re: System Generator pcore I/O performance results
117903: 07/04/12: Re: SETUP & HOLD time confusion
117911: 07/04/13: Re: SETUP & HOLD time confusion
117924: 07/04/13: Re: SETUP & HOLD time confusion
118105: 07/04/17: Re: XPS behavioral simulation fails: the design is not loaded
118116: 07/04/17: Re: SETUP & HOLD time confusion
118125: 07/04/17: Re: Block RAM strange behavior, address off by one
118161: 07/04/18: Re: Block RAM strange behavior, address off by one
118164: 07/04/18: Re: Block RAM strange behavior, address off by one
118313: 07/04/23: Re: Ouputs during startup and Programming
118416: 07/04/26: Re: Problem with writing values to SRAM from XMD
118418: 07/04/26: Re: EDK Simulation library compilation wizard can't find modelsim
118420: 07/04/26: Re: How to drop a Ethernet Packet in Xilinx EMAC
118625: 07/05/01: Re: About ModelSim
118630: 07/05/01: Re: switched to xcf32p prom and now doesn't run
118648: 07/05/01: Re: About ModelSim
119248: 07/05/15: Re: coregen -> simulation error in modelsim
119375: 07/05/17: Re: clock wide pulse transfer b/w clock domains
119420: 07/05/18: Re: Xilinx Timing Constraint Questions
119599: 07/05/23: Re: How the synthesizer acutally works.
119607: 07/05/23: Re: Project Navigator / Verilog / +define
119623: 07/05/24: Re: How the synthesizer acutally works.
119795: 07/05/25: Re: low speed communication
119796: 07/05/25: Re: low speed communication
119849: 07/05/28: Re: Spartan3 LVCMOS33 Slew rate
119853: 07/05/28: Re: Spartan3 LVCMOS33 Slew rate
119909: 07/05/29: Re: Linux device driver for FPGA Xilinx Virtex-4
119914: 07/05/29: Re: Linux device driver for FPGA Xilinx Virtex-4
119917: 07/05/29: Re: Spartan3 LVCMOS33 Slew rate
119998: 07/05/30: Re: Inverse of a matrix
120405: 07/06/06: Re: asynchronous circuit design
133688: 08/07/09: Re: Xilinx ISE impact outputs bad idcode when in batch mode but works
133691: 08/07/09: Re: Configure registers of CMOS Sensor by Spartan3
133878: 08/07/18: Re: Need help regarding xupv2p board....
133884: 08/07/18: Re: a question about linker map file
134001: 08/07/21: Re: Strange behaviour with Xilkernel
134018: 08/07/22: Re: help me improve this simple function
134023: 08/07/22: Re: Help to SImulate Uart TX
134032: 08/07/22: Re: Help to SImulate Uart TX
134033: 08/07/22: Re: Help to SImulate Uart TX
134043: 08/07/22: Re: Help to SImulate Uart TX
149577: 10/11/06: Re: combinatorial process not simulating correctly
149644: 10/11/12: Re: Design chaos
149719: 10/11/20: Re: test peripheral example in xilinx XPS
149725: 10/11/20: Re: Debugging with a single LED
149732: 10/11/21: Re: test peripheral example in xilinx XPS
149868: 10/11/29: Re: Hi-Z Output Bug in Lattice ispLever
149890: 10/11/30: Re: Hi-Z Output Bug in Lattice ispLever
149891: 10/12/01: Re: Hi-Z Output Bug in Lattice ispLever
149977: 10/12/04: Re: FSM single process...BIG question
150004: 10/12/06: Re: Concurrent Logic Timing
150005: 10/12/06: Re: Concurrent Logic Timing
Newman5382:
35471: 01/10/06: Re: Xilinx XST synthesis signal naming
75698: 04/11/12: Re: DDR Mux - how does it work?
newman5382:
76122: 04/11/25: Re: how to evaluate the needed number of gate?
76265: 04/11/29: Re: Which programmable clock for Spartan3 starter board and A/D-converter
76276: 04/11/29: Re: Which programmable clock for Spartan3 starter board and A/D-converter
76330: 04/11/30: Re: 99% Utilisation !
76339: 04/11/30: Re: block ram and bmm files
76340: 04/11/30: Re: block ram and bmm files
76342: 04/11/30: Re: block ram and bmm files
76363: 04/12/01: Re: Which programmable clock for Spartan3 starter board and A/D-converter
76379: 04/12/01: Re: 99% Utilisation !
76394: 04/12/01: Re: block ram and bmm files
76507: 04/12/05: Experiences with Memec V2Pro Board
76517: 04/12/05: Re: Experiences with Memec V2Pro Board
76568: 04/12/06: Re: Xilinx 6.2 to 6.3 upgrade brakes soc
76585: 04/12/06: Re: Xilinx 6.2 to 6.3 upgrade brakes soc
76657: 04/12/08: Re: Xilinx Read First Write First
77298: 05/01/04: Re: problem with edk
77352: 05/01/05: Re: Latches
77574: 05/01/11: Re: Asynchronous signals and simulation
77863: 05/01/19: Re: Passing OPB signals through submodule
77869: 05/01/19: Re: Passing OPB signals through submodule
78281: 05/01/28: EDK 6.3 Eval with Spartan 3 Starter Kit
78343: 05/01/30: Re: Trouble with Post-Place Simulation
78352: 05/01/30: Re: Trouble with Post-Place Simulation
78484: 05/02/01: Re: reading from CF card
78757: 05/02/07: Re: xilinx parallel cable IV
78816: 05/02/08: Re: V4LX25-ES and systemACE
78817: 05/02/08: Re: BFM Basics
78822: 05/02/08: Re: V4LX25-ES and systemACE
78824: 05/02/08: Re: V4LX25-ES and systemACE
78851: 05/02/09: Re: V4LX25-ES and systemACE
78859: 05/02/09: Re: V4LX25-ES and systemACE
78927: 05/02/10: Re: V4LX25-ES and systemACE
78959: 05/02/10: Re: Spartan-3 Starter Kit supplier in the UK?
78964: 05/02/10: Re: XMD/GBD problems
78967: 05/02/10: Re: Spartan-3 Starter Kit supplier in the UK?
78973: 05/02/10: Re: XMD/GBD problems
78976: 05/02/10: Re: Spartan-3 Starter Kit supplier in the UK?
78991: 05/02/10: Re: Flash problem
79068: 05/02/13: Re: Fast counting in Spartan 3
79085: 05/02/14: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
79178: 05/02/15: Re: Xilinx Spartan 3 kit - VHDL design question
79185: 05/02/15: Re: Xilinx Post Place and Route FIFO problems
79198: 05/02/15: Re: Xilinx Post Place and Route FIFO problems
79219: 05/02/15: Re: Xilinx Post Place and Route FIFO problems
79256: 05/02/16: Re: Weird Mircroblaze programm execution
79329: 05/02/17: Re: VGA core
79376: 05/02/18: Re: ModelSim Timing Strategy
79464: 05/02/19: Re: Antti Lukats: all my past live projects to be published...
79473: 05/02/19: Re: EMC and Shared SRAM/FLASH Bus
79475: 05/02/19: Re: ModelSim Timing Strategy
79503: 05/02/20: Re: Antti Lukats: all my past live projects to be published...
79507: 05/02/20: Re: Antti Lukats: all my past live projects to be published...
79513: 05/02/20: Re: Antti Lukats: all my past live projects to be published...
79543: 05/02/20: Re: Antti Lukats: all my past live projects to be published...
79586: 05/02/21: Re: Antti Lukats: all my past live projects to be published...
79591: 05/02/21: Re: PPC405 sleep?
79617: 05/02/22: Re: BACK to FPGA
79626: 05/02/22: Re: Exporting Modelsim Values?????
79702: 05/02/23: Re: Frustrated with Altera
<newman5382@yahoo.com>:
137133: 08/12/24: Re: PCI newbie problems
138278: 09/02/11: Re: Strange EDK 10.1.i error message
138291: 09/02/12: Re: MicroBlaze Programming
138681: 09/03/04: Re: 32x32 -> 64 multiplier in virtex-5
138686: 09/03/04: Re: 32x32 -> 64 multiplier in virtex-5
138688: 09/03/04: Re: 32x32 -> 64 multiplier in virtex-5
138789: 09/03/10: Re: Finding aligned clock transitions with state machine
138819: 09/03/11: Re: Finding aligned clock transitions with state machine
138898: 09/03/13: Re: XST: Unconnected output pins
138899: 09/03/13: Re: XST: Unconnected output pins
138987: 09/03/17: Re: How to load an image onto system ace compact flash embedded on
News:
20932: 00/02/29: Foundation2.1i installation problem in Win98se
79114: 05/02/14: Strange clock problem with Synthesized netlist in Quartus
134427: 08/08/10: Spartan 3e, LVDS LCD.
news:
26849: 00/11/01: Re: help on a simple ALU
47857: 02/10/06: Re: SoC Testing , need links
79340: 05/02/17: IOBs in virtex4?
news reader:
116400: 07/03/08: How best do I implement routing boxes in RTL?
116463: 07/03/10: Re: How best do I implement routing boxes in RTL?
117319: 07/03/28: How is it possible to design a convolutional interleaver with sequential memory writes?
117367: 07/03/29: Re: How is it possible to design a convolutional interleaver with sequential memory writes?
117368: 07/03/29: Re: How is it possible to design a convolutional interleaver with sequential memory writes?
117465: 07/04/01: How much time margin should I give to a SDRAM interface via FPGA?
117487: 07/04/02: Re: How much time margin should I give to a SDRAM interface via FPGA?
117917: 07/04/13: How do I constrain Xilinx to implement multi-cycle paths?
119438: 07/05/19: How do I constraint multiple clock cycle in Altera?
119859: 07/05/28: Is this the correct way to design FPGA to DRAM interface?
News sender:
64507: 04/01/06: Installation of Xlinx
news tin:
26299: 00/10/11: palasm
26354: 00/10/13: Re: palasm
news-server.houston.rr.com:
52539: 03/02/12: FPGA for audio record and playback???
<news-support@sbcglobal.net>:
141149: 09/06/08: AT&T Usenet Netnews Service Shutting Down
news.bellatlantic.net:
42744: 02/05/02: Re: static logic vs LUT
43108: 02/05/14: Re: Architecture for high-level reconfigurable computing
news.dlr.de:
40979: 02/03/19: 1,5V power supply?
news.gate.net:
26024: 00/09/30: Xilinx XC2018 Design tools
news.green.ch:
89162: 05/09/07: Signed addition
<news.guardiani@gmail.com>:
94162: 06/01/06: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
news.hinet.net:
24599: 00/08/15: Re: 8251 USART
30264: 01/03/30: Re: 8279 keyboard controller in Verilog or VHDL ?
30333: 01/04/03: Re: some info. on FPGA
90337: 05/10/10: Re: evaluation edk in Spartan-3 starter kit
news.la.sbcglobal.net:
117234: 07/03/27: Open-source CPU-core for standard-cell ASIC?
news.optimum-online.com:
70754: 04/06/26: Xilinx ML310 Experience?
news.pavilion.net:
29766: 01/03/08: GSM Baseband Chipset??
news.pcnet.com:
16667: 99/06/01: FPGA Introduction is needed, right?
16750: 99/06/06: Re: FPGA Introduction is needed, right?
news.skynet.be:
81208: 05/03/19: Re: Is an XC3S1500 enough to implement a MP@ML MPEG-2 decoder?
news.t-online.de:
116346: 07/03/07: Spartan3AN - Roadmap
news.terra.es:
47593: 02/09/30: SOC interconexion
news.utanet.at:
69393: 04/05/10: Re: Error while simulation with XILINX DCM
news.verizon.net:
81190: 05/03/19: rocketio
96316: 06/02/02: Re: BPSK modulation on Xilinx FPGA
100686: 06/04/16: Re: Counting bits
News123:
139301: 09/03/25: Re: Looking for a low-cost development kit
139507: 09/04/01: Switching an AC power socket from an FPGA
139517: 09/04/02: Re: Switching an AC power socket from an FPGA
139518: 09/04/02: Re: Switching an AC power socket from an FPGA
139583: 09/04/05: Re: Modulo-10 counter
139691: 09/04/09: Re: Two stage synchroniser,how does it work?
139776: 09/04/13: Re: Processor returns-Explanation
139959: 09/04/21: Re: Help me I am a new techie on FPGA
<news@fkchong.freeuk.com>:
20706: 00/02/18: Re: launching a FPGA cores start-up
<news@logici.com>:
2915: 96/02/28: Re: PCI models synthesized to FPGAs?
3104: 96/04/02: Re: PCI Support...
<news@prodigy.net>:
40138: 02/02/28: Pacbell users - this group has been changed!
<news@rblack01.plus.com>:
135444: 08/10/02: Standalone Altera production programmer
138099: 09/02/06: Precedence of signal assignment in a clocked process
138333: 09/02/16: Re: Precedence of signal assignment in a clocked process
138350: 09/02/17: Re: Precedence of signal assignment in a clocked process
153058: 11/11/24: Re: Production Programming of Flash for FPGAs and MCUs
<news@rtrussell.co.uk>:
25273: 00/09/04: Slow routing of PWR/GND (Virtex)
25285: 00/09/05: Re: Slow routing of PWR/GND (Virtex)
25526: 00/09/13: Virtex 'shutdown' phenomenon
25565: 00/09/14: Re: Virtex 'shutdown' phenomenon
26139: 00/10/05: Re: DLL unlocking
26760: 00/10/27: Using previous version as floorplan (2.1i vs 3.1i)
26822: 00/10/31: Re: Using previous version as floorplan (2.1i vs 3.1i)
39085: 02/01/31: Re: Coregen Half-Band FIR filter implemenation does not work
42760: 02/05/02: Re: Virtex Evolution ( Deltas )
52362: 03/02/07: Re: low pass FIR filter in FPGA
58773: 03/08/01: Design fits XC9536 but not XC9536XL
58957: 03/08/05: Re: Design fits XC9536 but not XC9536XL
59012: 03/08/06: Re: Design fits XC9536 but not XC9536XL
59172: 03/08/11: Re: Design fits XC9536 but not XC9536XL
67404: 04/03/11: Re: Answering Machine RAM
69504: 04/05/12: Disabling bus-hold on XC9500XL
83952: 05/05/10: Re: dividing the clcok by 2.5
91978: 05/11/18: Re: RoHS
93456: 05/12/22: Re: real-time compression algorithms on fpga
95574: 06/01/24: Very OT: Americanized family names
<news@tumlis.lis.e-technik.tu-muenchen.de>:
2124: 95/10/18: Xilinx Configuration Memory Hacking
news_alias:
31864: 01/06/07: Re: Pentium 4 or AMD ?
32856: 01/07/10: Re: Handel-C
news_check.py:
7439: 97/09/10: Re: hdtv interpolation and decimation
7440: 97/09/10: Re: fpga configuration over PCI
News_food:
19212: 99/12/06: Re: Simple programmator for EP910
Newsbrowser:
25212: 00/08/30: Re: Xilinx and CD databooks (rant)
25614: 00/09/15: Re: PCI-Tip? (for Xilinx Virtex/-E)
26501: 00/10/18: Re: Virtex-E and ADC
27089: 00/11/10: Re: Xilinx PCI Core
27590: 00/11/29: Re: Clock Skew : Does Xilinx know what they're doing?
27936: 00/12/15: Re: Dual-ported RAM instantiation in Virtex-E ?
28444: 01/01/12: Re: Problem with Simulation of VirtexE Block SelectRAM
28581: 01/01/17: Re: Virtex-II officially launched
28830: 01/01/25: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
28871: 01/01/26: Re: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
28917: 01/01/29: Re: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
29165: 01/02/08: Re: Mentor Advice
31258: 01/05/16: Re: Bizarre PAR phenomenon
newsgroup:
86277: 05/06/24: Re: How do I convert a polynomial into a parallel scrambler formula?
86281: 05/06/24: Re: How do I convert a polynomial into a parallel scrambler formula?
86291: 05/06/24: Re: How do I convert a polynomial into a parallel scrambler formula?
86293: 05/06/24: Re: FPGA :FFT Core in Xilinx
Newsgroup:
55814: 03/05/20: Thermal problems with large FPGA BGA's
<newsgroup@johnhandwork.com>:
138844: 09/03/12: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
138845: 09/03/12: Re: How to initialize the Xilinx FIFO with predetermined value on
newsleecher@spam.com:
123967: 07/09/08: Re: Nios II -- Why does this error occur ?
<newsmailcomp5@gustad.com>:
77479: 05/01/07: Re: San Jose job offer - need advice
78349: 05/01/30: Re: Altera Quartus 4.2 Service Pack 1 fails to install
94447: 06/01/11: Re: Altera MAX-II: User logic access to USERCODE_REGISTER?
94838: 06/01/18: Re: Altera MAX-II: User logic access to USERCODE_REGISTER?
<newsmaster@bellsouth.net>:
141315: 09/06/17: AT&T Usenet Netnews Service Shutting Down
<newtech@my-dejanews.com>:
11098: 98/07/18: Jobs for FPGA Designers/Engineers
11099: 98/07/18: Jobs for FPGA Hardware Designers/Engineers
NewToFPGA:
119499: 07/05/21: Does FPGA need CPU for processing a packet/frame
119500: 07/05/21: Does FPGA need CPU for processing a packet/frame
119501: 07/05/21: Does FPGA need CPU for processing a packet/frame
119542: 07/05/22: Re: Does FPGA need CPU for processing a packet/frame
119572: 07/05/22: Re: Does FPGA need CPU for processing a packet/frame
newzhnd:
148010: 10/06/13: Altera Quartus - how to create small roms & rams for Cyclone 3
148012: 10/06/13: Re: Altera Quartus - how to create small roms & rams for Cyclone 3
next:
37603: 01/12/17: Re: division 64
37623: 01/12/17: Re: division 64
nezhate:
91448: 05/11/07: Adder synthesis
92077: 05/11/21: architecture
92084: 05/11/22: Re: architecture
92091: 05/11/22: Re: architecture
97892: 06/03/01: problem with ISE versions
98530: 06/03/12: Re: Shift Register synthesis??
103488: 06/06/04: Multi place and route
103489: 06/06/04: Re: Multi place and route
103559: 06/06/05: Re: Multi place and route
117820: 07/04/10: FIFO newbie question
117835: 07/04/11: Re: FIFO newbie question
118132: 07/04/18: Printing problem with Ise 9.1.03i
118171: 07/04/18: Re: Printing problem with Ise 9.1.03i
118174: 07/04/18: Re: Printing problem with Ise 9.1.03i
118228: 07/04/20: Re: Printing problem with Ise 9.1.03i
119079: 07/05/10: NgdBuild:604 error
119094: 07/05/11: Re: NgdBuild:604 error
122728: 07/08/05: Re: Area report
122753: 07/08/06: Re: new to the group
128966: 08/02/11: Reed solomon IP core
128967: 08/02/11: Re: ModelSim versus Active-HDL....redux
128974: 08/02/12: Re: Reed solomon IP core
129768: 08/03/05: Bit Error Rate Test
129813: 08/03/05: Re: Bit Error Rate Test
135338: 08/09/27: Open source IP core development with configuration GUI
nfeske:
134727: 08/08/28: Re: Genode FPGA graphics project launched
134733: 08/08/28: Re: Genode FPGA graphics project launched
135880: 08/10/20: Major update of the Genode FPGA graphics project
137306: 09/01/08: Re: Which revision control do fpga designers use (2009)
nfirtaps:
112135: 06/11/16: Validity of data on rising edge of clock
116422: 07/03/08: Driving PLL from general I/O in Altera Cyclone
116438: 07/03/08: Re: Driving PLL from general I/O in Altera Cyclone
116462: 07/03/09: Re: Driving PLL from general I/O in Altera Cyclone
116464: 07/03/09: Re: Driving PLL from general I/O in Altera Cyclone
116466: 07/03/09: Re: Driving PLL from general I/O in Altera Cyclone
Ng Choon Yam:
11483: 98/08/19: Problem in using Mentor Graphic to generate VHDL code
11486: 98/08/19: Problem in using Mentor Graphic to generate VHDL code
11484: 98/08/19: Problem in using Mentor Graphic to generate VHDL code
11485: 98/08/19: Problem in using Mentor Graphic to generate VHDL code
11487: 98/08/19: Problem in using Mentor Graphic to generate VHDL code
ngill:
153223: 12/01/12: Re: Can't get the Xilinx cable drivers installed on SL6.1 (RHEL 6.1)
NgKH:
22917: 00/06/02: university graduate seeking IT position
ngsayjoe@gmail.com:
99683: 06/03/28: Re: Verilog, PSL or SystemVerilog of OVL?
Nguyentule:
27807: 00/12/09: Consultant needed. Xilinx Spartan 2.
27808: 00/12/09: WTB 500-1000 Xilinx Spartan1 XSC30 or XCS40 chips
NHartl:
13709: 98/12/19: Re: Why doesn't Xilinx's simulator work?
13708: 98/12/19: Re: Two questions
13710: 98/12/19: Re: xilink Parallel cable III
<nhddlo@thehaunting.com>:
18440: 99/10/24: I Like The Way I DO
<nhduong@my-deja.com>:
27787: 00/12/08: PLCC adapter
Nhoxford:
30602: 01/04/18: Re: CONTRACTORS
nhurley:
96243: 06/02/01: Die Area
97877: 06/03/01: Microblaze on Spartan3
ni:
130445: 08/03/24: BYTE shifter
130487: 08/03/25: Re: BYTE shifter
130800: 08/04/01: coregenerator bram in synplify pro error
130818: 08/04/02: Re: coregenerator bram in synplify pro error
130824: 08/04/02: Re: coregenerator bram in synplify pro error
130867: 08/04/03: synplify pro generates negative slack
130896: 08/04/04: Re: synplify pro generates negative slack
130913: 08/04/04: Re: synplify pro generates negative slack
131242: 08/04/16: chipscope pro , lower level signals not visible
132961: 08/06/11: DISABLING POWERPC IN VIRTEXII PRO
132990: 08/06/12: chipscope analyzer error
132991: 08/06/12: Re: DISABLING POWERPC IN VIRTEXII PRO
133012: 08/06/13: export to project naigator
133017: 08/06/13: Re: chipscope analyzer error
133018: 08/06/13: Re: export to project naigator
133782: 08/07/14: pci bridge fpga card
144416: 09/12/04: BRAM usage in synplify pro
144420: 09/12/05: Re: BRAM usage in synplify pro
144423: 09/12/05: Re: BRAM usage in synplify pro
<ni.neofpga@gmail.com>:
89291: 05/09/11: Block RAM problem (spartan 3)
Nial Stewart:
22760: 00/05/23: Re: Xilinx tools
22839: 00/05/26: Re: Xilinx tools
23729: 00/07/06: Altera's promises unfulfilled???
23758: 00/07/07: Re: Altera's promises unfulfilled???
23864: 00/07/13: Re: Altera's promises unfulfilled???
24013: 00/07/21: Downloadable versions available
24127: 00/07/27: Re: Variable shifting
25223: 00/08/31: Re: Using a FPGA as I/O expansion on embedded PC ??
25610: 00/09/15: Re: Clock skew in XILINX CPLD
25705: 00/09/18: Re: Clock skew in XILINX CPLD
25712: 00/09/18: Re: Clock skew in XILINX CPLD
25888: 00/09/25: Dual monitor display possible with modelsim on a PC?
27290: 00/11/17: Spartan 3.3V Driving 5v input tristate + pull up problem...
27417: 00/11/21: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
27520: 00/11/27: Re: Survey on design methodologies
27583: 00/11/29: Re: hard or soft core for FPGA?
27691: 00/12/03: Re: Issues with Spartan II
27698: 00/12/04: Re: Issues with Spartan II
27712: 00/12/04: Re: Issues with Spartan II
27796: 00/12/08: Re: Altera free development tools
27844: 00/12/12: Re: Linear Regulator troubles
27847: 00/12/12: Re: Synplify PRO 6.1 + Foundation 3.1i
27851: 00/12/12: Re: Synplify PRO 6.1 + Foundation 3.1i
27881: 00/12/13: Re: Synplify PRO 6.1 + Foundation 3.1i
27969: 00/12/18: Re: Altera free development tools
27999: 00/12/19: 3V -> 5V clock signal level conversion
28007: 00/12/19: Re: 3V -> 5V clock signal level conversion
28028: 00/12/19: Re: 3V -> 5V clock signal level conversion
28030: 00/12/19: Re: 3V -> 5V clock signal level conversion
28039: 00/12/19: Re: 3V -> 5V clock signal level conversion
28052: 00/12/20: Re: 3V -> 5V clock signal level conversion
28103: 00/12/21: Re: 3V -> 5V clock signal level conversion
28333: 01/01/08: Re: Spartan-II DLL Usage
28609: 01/01/18: Re: About programming cables
28750: 01/01/23: Re: grey code counters
28822: 01/01/25: Re: UK parts
28913: 01/01/29: Re: grey code counters
28941: 01/01/30: Re: Can Virtex-II be programmed with MultiLINX?
29327: 01/02/14: Re: Mentor Advice
29433: 01/02/21: Re: Altera process change....
29869: 01/03/14: Re: NIOS 16-Bit
29882: 01/03/15: Re: NIOS 16-Bit
30590: 01/04/18: Re: Getting license for Modelsim in Xilinx webpack?
30610: 01/04/19: Re: Wanted: ISA bus implementation for Xilinx
30693: 01/04/24: Re: Altera Mercury comments
30816: 01/04/30: Re: Multiple state machines in altera AHDL
30835: 01/05/01: Re: Multiple state machines in altera AHDL
30852: 01/05/01: Re: Multiple state machines in altera AHDL
32178: 01/06/18: Re: Pin locking in Maxplus2
32198: 01/06/19: Re: Verilog or VHDL?
32223: 01/06/20: Re: Pin locking in Maxplus2
32242: 01/06/21: Re: Pin locking in Maxplus2
32245: 01/06/21: Re: FPGA Boards
32256: 01/06/21: Re: Pin locking in Maxplus2
32310: 01/06/22: Re: ALTERA CHIPS - ANYBODY WANT TO BUY A "FEW" ONLY (UK based thread)
32457: 01/06/27: Re: LOOKING FOR VHDL DEBUGGER
32458: 01/06/27: Re: LOOKING FOR VHDL DEBUGGER
32706: 01/07/05: Re: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (0/1)
32707: 01/07/05: Re: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (0/1)
32730: 01/07/06: Re: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (0/1)
33151: 01/07/18: Re: Working Design - Anyone
33155: 01/07/18: Re: Working Design - Anyone
33428: 01/07/26: Re: FPGA Express or Spectrum?
33675: 01/08/02: Re: May I connect two pins to the same net?
34516: 01/08/28: Re: System Requirements
34550: 01/08/29: Re: System Requirements
34601: 01/08/30: Re: Principles of Verifiable RTL Design (2nd ed)
34974: 01/09/17: Re: Altera survey
35231: 01/09/26: Re: Pentium 3 vs Pentium 4 benchmarks
36557: 01/11/12: Re: Funny voltage levels
36569: 01/11/12: Re: Funny voltage levels
36603: 01/11/13: Re: Funny voltage levels
36618: 01/11/13: Re: Incrementing counter from state-machine
38754: 02/01/24: Re: NIOS ver 1.1.1 type boards for sale: Money making opportunity.
40378: 02/03/06: Re: Quartus II 2.0 fast fit option
40442: 02/03/07: Re: exceeding 2GB limits in xilinx
40509: 02/03/08: Re: Quartus II 2.0 fast fit option
41649: 02/04/04: Re: Marquis of Queensbury Rules
41851: 02/04/09: Re: How sensitive is the EPM7064?
42443: 02/04/24: Re: Reasonably Priced Development Software ??
46554: 02/09/03: Re: IT consultant vs Engineer
48267: 02/10/15: Re: Sync Reset without clocks
51191: 03/01/06: Re: Contracting in the UK
51202: 03/01/06: Re: Contracting in the UK
51203: 03/01/06: Re: asynchronous inputs
51245: 03/01/08: Re: Newbie question
51689: 03/01/19: Re: Xilinx PCI core PCI-X compatible ?
51760: 03/01/21: Re: FLEXlm
52092: 03/01/31: Re: Quartus
52177: 03/02/03: Targeting the VirtexII version of Picoblaze at a SpartanII....
52280: 03/02/05: Re: Targeting the VirtexII version of Picoblaze at a SpartanII....
52358: 03/02/07: Re: NIOS and ACEX1K
52474: 03/02/11: Re: Fast BlockRAM updates
52475: 03/02/11: Re: Quartus / ModelSim
52480: 03/02/11: Re: Fast BlockRAM updates
52486: 03/02/11: Re: Quartus / ModelSim
52579: 03/02/14: Re: Silly Quartus Question
53184: 03/03/05: Re: Issues in Outsourcing?
53308: 03/03/10: Re: comp.arch.fpga : VCC shorted to GND within FPGA???
54107: 03/04/02: Re: uP interface question
55752: 03/05/18: Re: smallest embedded cpu.
56353: 03/06/03: Re: SONET/SDH chipset on FPGA
56534: 03/06/08: Re: using USB
56536: 03/06/08: Re: outsourcing hardware verification
56983: 03/06/20: Perl Testbench generator
57411: 03/06/30: Re: Xilinx Webpack bugs bugs bugs
57471: 03/07/01: Re: Asynchronous RESET?
58665: 03/07/30: Re: Simple circuit / good design?
58709: 03/07/31: Re: Handel C
58768: 03/08/01: Re: Handel C
58875: 03/08/03: Re: Handel C
59337: 03/08/15: Re: Free VHDL Simulator
59439: 03/08/19: Re: Parallel interface to an FPGA
59482: 03/08/20: Re: serial communication between pc and altera fpga
59842: 03/08/29: Re: HDL Designer from Mentor
60123: 03/09/05: Re: use verilog-modules in an vhdl-design-flow
60318: 03/09/10: Re: simulating memory models in sopc builder
60417: 03/09/12: Re: Webpack Vs. ISE
60486: 03/09/15: Re: Webpack Vs. ISE
60498: 03/09/15: Re: USB transceiver for FPGA
60603: 03/09/17: Re: FPGA congress on Asia
60635: 03/09/18: Re: Webpack Vs. ISE
61419: 03/10/03: Re: Quartus II tutorial vs the real world
61473: 03/10/05: Re: Quartus II tutorial vs the real world
61664: 03/10/08: Re: Problem with PCI cards
61676: 03/10/08: Re: Problem with PCI cards
61769: 03/10/10: Re: Problems with PCI-CardbusCard (interface is an FPGA) on Windows
61879: 03/10/14: Re: Electronic Dice ( 3 die ) In VHDL
62001: 03/10/16: Re: Electronic Dice ( 3 die ) In VHDL
62059: 03/10/17: Re: 3rd party pci dma engine
62222: 03/10/22: Re: VHDL Souce Code Beautifiers
62223: 03/10/22: Re: Cool test bench generator for testing some devices which describe by Verilog or VHDL
62293: 03/10/24: Re: Pass transistor logic and multi-valued logic in a FPGA
62460: 03/10/30: Re: Some FPGA questions
62505: 03/10/31: Re: How to protect fpga based design against cloning?
62608: 03/11/03: Re: How to protect fpga based design against cloning?
62609: 03/11/03: Re: How to protect fpga based design against cloning?
62666: 03/11/04: Re: Xilinx - Multi Volt Interfacing
62789: 03/11/07: Re: Programmer's unpaid overtime.
62927: 03/11/11: Re: Multiple clock domains in a FPGA (using DLL's)
62992: 03/11/12: Re: Layout examples
63001: 03/11/12: Re: 0.13u device with 5V I/O
63385: 03/11/20: Re: State Machines....
63501: 03/11/24: Re: PCI interface with attached PLD
63542: 03/11/25: Re: How to set 'set up time' in a Quartus Tool for a PCI Device
63792: 03/12/04: Re: Ideal Development Machine Specifications
63816: 03/12/04: Re: Ideal Development Machine Specifications
63835: 03/12/05: Re: Ideal Development Machine Specifications
63896: 03/12/08: Re: NIOS: Running code from flash
63899: 03/12/08: Re: NIOS: Running code from flash
63993: 03/12/11: Re: Soldering of FPGAs
64058: 03/12/15: Re: Manufacturing Tests
64118: 03/12/17: Re: Multi-FPGA PCI board recommendations???
64184: 03/12/19: Re: Spartan3 availability
64214: 03/12/20: Re: Spartan3 availability
64229: 03/12/21: Re: Spartan3 availability
64460: 04/01/05: Re: Something additional: Adding internal signals in MODELSIM
64710: 04/01/12: Re: Altera Cyclone data is incomplete or messy
64722: 04/01/12: Re: Programming and debugging the Altera Cyclone family
64920: 04/01/16: Re: Hardware to test (FPGA-based) prototype?
64985: 04/01/18: Re: What does nios-run do?
64987: 04/01/18: Re: Programming and debugging the Altera Cyclone family
65182: 04/01/21: Re: Altera/Xilinx Distributor in Europe?
65340: 04/01/25: Re: Cascading of many stages of DCM...
65358: 04/01/26: Re: Cascading of many stages of DCM...
65452: 04/01/29: Re: Altera Active Serial
65453: 04/01/29: Re: Altera Active Serial
65567: 04/02/02: Re: Altera Active Serial
65863: 04/02/09: Re: Do Xilinx Fix Their Prices?
65942: 04/02/10: Re: Synchronization of signals
65950: 04/02/10: Re: Synchronization of signals
65961: 04/02/10: Re: Synchronization of signals
66041: 04/02/11: Re: Spartan-3 shipping, or perhaps not!
66294: 04/02/16: GSR in Spartan3 ?
66324: 04/02/17: Re: GSR in Spartan3 ?
66328: 04/02/17: Re: GSR in Spartan3 ?
66342: 04/02/17: Re: GSR in Spartan3 ?
66362: 04/02/18: Re: GSR in Spartan3 ?
66364: 04/02/18: Re: GSR in Spartan3 ?
66370: 04/02/18: Re: GSR in Spartan3 ?
66376: 04/02/18: Re: GSR in Spartan3 ?
66378: 04/02/18: Re: GSR in Spartan3 ?
66379: 04/02/18: Re: FFT on Virtex-II (Desperation Imminent)
66380: 04/02/18: Re: Using 3.3V compliant FPGA for 5V PCI
66385: 04/02/18: Re: GSR in Spartan3 ?
66387: 04/02/18: Re: GSR in Spartan3 ?
67078: 04/03/05: Re: Different Finite Field Multipliers!!!
67469: 04/03/12: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67768: 04/03/19: Re: Spartan III availability
67952: 04/03/23: Quartus with AMD64 processors?
67993: 04/03/24: Re: Quartus with AMD64 processors?
68042: 04/03/25: Re: Quartus with AMD64 processors?
68319: 04/04/01: Re: Quartus removes Tristate Buffer
68393: 04/04/02: Re: AHDL, VERILOG or VHDL??
68539: 04/04/07: Re: Cyclone and ByteBlasterMV?
68699: 04/04/14: Re: Cyclone and ByteBlasterMV?
68971: 04/04/23: OT - Generating a 20MHz clock that can be adjusted by +- 2%
68972: 04/04/23: Re: Best Xilinx toolchains for under $2,000 ?
69040: 04/04/26: Re: OT - Generating a 20MHz clock that can be adjusted by +- 2%
69044: 04/04/26: Re: Altera ByteBlaster II schematic
69950: 04/05/25: Re: Never right, always room for improvement
70456: 04/06/17: Re: Several Problems with Spartan2 Configuration
70907: 04/07/01: Re: Cyclone 5V Tolerance
70945: 04/07/02: Re: Compile 30% of my multipliers with LUT?
70946: 04/07/02: Re: Xilinx $99 Spartan-3 kit
71407: 04/07/17: Re: programmable voltage control of a VCCIO Bank
71528: 04/07/21: Re: 32-channel PC-based logic analyzers
71589: 04/07/23: Re: Converting High Rise Time clock to Low Rise time clock - Chellenge!
71702: 04/07/28: Re: vhdl code : altera vs xilinx
72758: 04/08/31: Re: From good-old ISA bus cards to PCI bus
73363: 04/09/20: Re: Verilog vs VHDL for Loops
75256: 04/10/31: Re: FPGA board checking
74869: 04/10/20: Re: unstable fpga design
75908: 04/11/18: NIOSII problems?
76068: 04/11/23: Favourite Design Entry Optomisation Method?
76069: 04/11/23: Re: Favourite Design Entry Optomisation Method?
76091: 04/11/24: Re: Favourite Design Entry Optomisation Method?
78878: 05/02/09: Re: SimmStick FPGA module
78886: 05/02/09: Re: ASIC vs DSP vs FPGA
78892: 05/02/09: Re: Cyclone configuration device
81070: 05/03/17: Re: Altera free web FPGA software license question
81158: 05/03/18: Re: Altera free web FPGA software license question
81364: 05/03/22: Re: Free simulator
82353: 05/04/11: Re: LVDS PCI card is needed
87882: 05/08/03: Re: Xilinx Best Source for Reset
87945: 05/08/04: Re: Xilinx Best Source for Reset
87963: 05/08/04: Re: Xilinx Best Source for Reset
88364: 05/08/16: Re: Altera NIOSII IDE problem???
89267: 05/09/09: Re: Cyclone conf flash - 25p10 !
89596: 05/09/20: Re: Reprogramming FPGA over PCI???
90302: 05/10/10: Re: FPGA behaviour when its used resource is >90% ?
90304: 05/10/10: Re: Power on reset generation in FPGA
90920: 05/10/25: Re: FPGA Design Docs
91250: 05/11/02: Re: FPGA : PCI-CORE
91725: 05/11/11: Re: fastest possible USB
93838: 06/01/01: Re: Easy and fun: Worlds smallest FPGA module.
94584: 06/01/13: Re: Don't even get me started on lead,
94668: 06/01/16: Re: Don't even get me started on lead,
94914: 06/01/19: Re: Raggedstone specifications ...
94913: 06/01/19: Re: How much do you trust your CAD Program?
95207: 06/01/21: Re: need for a group FAQ?
96090: 06/01/30: Re: Remotely updating Altera FPGA configuration
96995: 06/02/14: Re: Altera RoHS Irony
97493: 06/02/23: Re: Is FPGA code called gateware?
97587: 06/02/24: Re: Is FPGA code called gateware?
97754: 06/02/27: Re: Is FPGA code called gateware?
97818: 06/02/28: Re: System crashes when configuring altera stratix pci board
97952: 06/03/02: Re: Is FPGA code called gateware?
98015: 06/03/03: Re: Is FPGA code called gateware?
98677: 06/03/14: Re: Soldering SMT/BGA
99385: 06/03/23: Timing Diagram software recommendations?
99590: 06/03/27: Altera IP address?
99600: 06/03/27: Re: Altera IP address?
100012: 06/04/01: Re: KEEP_HIERARCHY
100047: 06/04/02: Re: KEEP_HIERARCHY
100367: 06/04/07: Re: Configuration pins on Spartan-3
100559: 06/04/12: Re: Distributed Arithmetic
100561: 06/04/12: Re: Altera Nios II & PCI Compiler 4.1.0 Question
100563: 06/04/12: Re: PCI speed.
101577: 06/05/03: Re: How to open an ISE 8.1 project in ISE 7.1?
102433: 06/05/16: Re: getting good deals on small qty?
102825: 06/05/21: Re: How simple can FPGA design be? (Mission Possible 2006)
102826: 06/05/21: Forgot to say....
103005: 06/05/24: Re: fpga debug
103006: 06/05/24: Stopping Quartus using multipliers?
103018: 06/05/24: Re: Stopping Quartus using multipliers?
103019: 06/05/24: Re: Stopping Quartus using multipliers?
103024: 06/05/24: Re: Stopping Quartus using multipliers?
103058: 06/05/25: Re: problem programming Altera Cyclone device
103066: 06/05/25: Re: problem programming Altera Cyclone device
103153: 06/05/26: Re: problem programming Altera Cyclone device
103332: 06/05/31: Re: Cardbus Power On Reset !!!!!!!!
103391: 06/06/01: Re: PCI Design
103718: 06/06/09: Re: Good free or paid merge software that edits two similar files?
103842: 06/06/13: Re: How to get lowest price for a ModelSim license?
103854: 06/06/13: Re: How to get lowest price for a ModelSim license?
104433: 06/06/27: Re: VHDL model for Micron SDRAM simulation ?
104750: 06/07/05: Re: "Large" memory array in VHDL
105136: 06/07/14: Re: Need for reset in FPGAs
106123: 06/08/08: Re: Who is your favourite FPGA guru?
106547: 06/08/15: Re: Compiler can't detect std_logic_1164 package
106970: 06/08/23: Re: Modelsim
107491: 06/08/29: Re: Quartus software and dual-purpose pins
107629: 06/08/30: Re: Performance Appraisals
107812: 06/09/01: Higher voltages input, quick check....
107816: 06/09/01: Re: Higher voltages input, quick check....
107817: 06/09/01: Re: Higher voltages input, quick check....
107826: 06/09/01: Re: Higher voltages input, quick check....
107832: 06/09/01: Re: Higher voltages input, quick check....
119748: 07/05/25: Re: Dual Core or Quad Core when running Quartus 7.1
120587: 07/06/11: Unused clock pins tied inactive?
120671: 07/06/13: Re: Unused clock pins tied inactive?
121598: 07/07/09: Re: LiveDesign, Altium [opinion]
122368: 07/07/26: Re: Altera or Xilinx
122436: 07/07/27: Re: Best CPU platform(s) for FPGA synthesis
124050: 07/09/11: Re: Uses of Gray code in digital design
124173: 07/09/13: Re: Uses of Gray code in digital design
124195: 07/09/14: Re: Uses of Gray code in digital design
124751: 07/10/03: Re: FPGA NTSC signal with 2 resistors and PWM
125372: 07/10/24: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
125425: 07/10/25: Re: Nios II, ThreadX, NetX
126001: 07/11/12: Re: Programming connection
126038: 07/11/13: Structured way of changing eg time constants for real world build / simulation?
126040: 07/11/13: Re: Structured way of changing eg time constants for real world build / simulation?
126051: 07/11/13: Re: Structured way of changing eg time constants for real world build / simulation?
126460: 07/11/23: Re: FPGA for hobby use
126593: 07/11/28: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126653: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126654: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126655: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126656: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126657: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126658: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126659: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126660: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126661: 07/11/29: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126721: 07/11/30: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126723: 07/11/30: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
128226: 08/01/18: Re: How is FIFO implemented in FPGA and ASIC?
128875: 08/02/08: Strange "Style guide" requirements...
129216: 08/02/19: Efficient division algorithm?
129217: 08/02/19: Re: Strange "Style guide" requirements...
129219: 08/02/19: Re: Strange "Style guide" requirements...
129231: 08/02/19: Re: Efficient division algorithm?
129232: 08/02/19: Re: Efficient division algorithm?
129333: 08/02/21: Re: Efficient division algorithm?
129337: 08/02/21: Further Thoughts...
129452: 08/02/25: Re: Further Thoughts...
130716: 08/03/31: Re: Places to visit in Amsterdam and Brussells
130769: 08/04/01: Antii, can you give us an update?
130833: 08/04/03: Re: async clk input, clock glitches
131470: 08/04/22: Re: synchronous reset problems on FPGA
131475: 08/04/22: Re: Newbie: Testbench question
133070: 08/06/17: Re: Virtex5 FPGA Board and USB interface
133449: 08/06/30: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
134349: 08/08/07: Re: Downsizing Verilog synthesization.
134574: 08/08/19: Re: altera cyclone3 vertical migration
135547: 08/10/07: Actel constraints?
135554: 08/10/08: Another problem....
135570: 08/10/08: Re: Another problem....
135589: 08/10/09: Re: Actel constraints?
135600: 08/10/09: More Actel 'Funnies'
135621: 08/10/10: Re: More Actel 'Funnies'
135702: 08/10/13: Re: More Actel 'Funnies'
135714: 08/10/13: Re: More Actel 'Funnies'
136525: 08/11/20: Announce: HSMC General Purpose Interface Board for Altera Dev kits
137285: 09/01/07: UPDATE: HSMC General Purpose Interface Board, example FPGA design and Excel interface
137401: 09/01/14: Re: Counter: natural VS std_logic_vector
137419: 09/01/15: Re: Counter: natural VS std_logic_vector
137433: 09/01/16: Re: Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?
137434: 09/01/16: Re: Counter: natural VS std_logic_vector
138294: 09/02/13: Re: EPC16 does not configure CycloneII at high temperature
138797: 09/03/11: Re: Checking HDL syntax on command line with xilinx tools
140268: 09/05/07: Environmental variables to point at libraries with Modelsim?
140275: 09/05/07: Re: Environmental variables to point at libraries with Modelsim?
140658: 09/05/21: Re: Sigasi Public Beta: future of VHDL design
141312: 09/06/17: Re: 5.0V and 3.3V PCI interfacing with Altera Cyclone III
141327: 09/06/18: Re: 5.0V and 3.3V PCI interfacing with Altera Cyclone III
141472: 09/06/25: Re: True dual-port RAM in VHDL: XST question
141473: 09/06/25: Re: SRAM vs Flash based FPGA one more time
142329: 09/08/05: Re: AES encryption of bitstream - is my design secure?
142413: 09/08/10: Re: Spartan-6 Boards - Your Wish List
142414: 09/08/10: Re: Quartus fitter put a user pin on an already assigned pin
142966: 09/09/10: Re: An email from Altera
143518: 09/10/14: Re: Handwritten recognition using FPGA
143938: 09/11/04: Re: Cyclone IV announced
144292: 09/11/25: Re: Going mad trying to solve PLL setup/hold timing violation issues in Quartus
144322: 09/11/26: Re: Going mad trying to solve PLL setup/hold timing violation issues in Quartus
144334: 09/11/27: Re: Going mad trying to solve PLL setup/hold timing violation issues in Quartus
144352: 09/11/30: Re: Going mad trying to solve PLL setup/hold timing violation issues in Quartus
144405: 09/12/04: Re: A new approach to FPGA and PCB System Development Platform, Santa Clara, CA, USA (By Altium)
144462: 09/12/09: Re: Multiport BRAM for custom CPUs
144801: 10/01/05: Re: EPCS vs SPI Flash
144904: 10/01/14: Re: black box module integration
144906: 10/01/14: Re: black box module integration
144927: 10/01/15: Re: SystemVerilog Verification Example using Quartus and ModelSim
145279: 10/02/04: Re: Board layout for FPGA
145301: 10/02/05: Re: Board layout for FPGA
145302: 10/02/05: Re: Board layout for FPGA
145309: 10/02/05: Re: Board layout for FPGA
145472: 10/02/11: 10 layer stack for 1152 pin BGA routing (and decoupling)?
145497: 10/02/12: Test Post
145500: 10/02/12: Re: Test Post
145590: 10/02/15: Repost on 10 layer stack for 1152 pin BGA.
145746: 10/02/22: Re: System design in FPGA
145869: 10/02/26: Re: Frustration with Vendors!
145876: 10/02/26: Re: Frustration with Vendors!
145901: 10/02/27: Re: Frustration with Vendors!
145926: 10/02/28: Re: Frustration with Vendors!
145948: 10/03/01: Re: Frustration with Vendors!
145965: 10/03/02: Re: Frustration with Vendors!
145975: 10/03/02: Antti....
146023: 10/03/04: Announce: 1 Pin Interface - FPGA and HW debug tool
146024: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
146033: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
146053: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
146055: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
146080: 10/03/05: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
146221: 10/03/09: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146254: 10/03/10: Re: Some Active-HDL questions
146256: 10/03/10: Re: Spartan3AN DDR2 - bad writing zeros
146257: 10/03/10: Re: Some Active-HDL questions
146300: 10/03/11: Re: Spartan3AN DDR2 - bad writing zeros
146301: 10/03/11: Re: Some Active-HDL questions
146306: 10/03/11: Re: Compiling a design in Quartus that doesn't fit
146438: 10/03/18: Re: FPGA's with on-chip PROM?
146579: 10/03/23: Re: Why hardware designers should switch to Eclipse
146847: 10/03/30: Re: PCB routing issues for sync SRAM
147046: 10/04/12: Re: Debug multiple FPGAs using ChipScope via single JTAG chain
147256: 10/04/21: Re: I'd rather switch than fight!
147298: 10/04/22: Re: I'd rather switch than fight!
147605: 10/05/06: Re: FPGA Compilation Time Windows vs Linux
147639: 10/05/11: Re: Expecting sequential output, but RTL shows concurrent implementation.
147650: 10/05/12: Re: what is the fmax of the simple dual port ram in the altera fpga
147655: 10/05/13: New 'standard' compact programming header needed!
147675: 10/05/14: Re: New 'standard' compact programming header needed!
147676: 10/05/14: Re: New 'standard' compact programming header needed!
147677: 10/05/14: Re: New 'standard' compact programming header needed!
147691: 10/05/17: Re: New 'standard' compact programming header needed!
147696: 10/05/17: Re: Expecting sequential output, but RTL shows concurrent implementation.
147699: 10/05/17: Re: New 'standard' compact programming header needed!
147720: 10/05/19: Re: New 'standard' compact programming header needed!
147828: 10/05/26: Re: Advice on Xilinx Spelunking
147840: 10/05/26: Re: Advice on Xilinx Spelunking
147856: 10/05/27: Re: Software bloat (Larkin was right)
147997: 10/06/11: Re: Alternative to Chipscope
147998: 10/06/11: Re: Is it possible to get consistent implementation results?
148014: 10/06/14: Re: Altera Quartus - how to create small roms & rams for Cyclone 3
148017: 10/06/14: Re: Altera Quartus - how to create small roms & rams for Cyclone 3
148019: 10/06/14: Re: how fast is ... fast.
148043: 10/06/16: Re: how fast is ... fast.
148480: 10/07/27: Re: Embedded Multipliers in Altera Cyclone
148701: 10/08/18: Re: Getting started with FPGA
148702: 10/08/18: Re: Getting started with FPGA
148705: 10/08/18: Re: Getting started with FPGA
148707: 10/08/18: Re: Getting started with FPGA
148745: 10/08/19: Re: Getting started with FPGA
148796: 10/08/26: Re: New Application Note: Multiple configurations for Altera FPGAs
148797: 10/08/26: Re: New Application Note: Multiple configurations for Altera FPGAs
148798: 10/08/26: Re: New Application Note: Multiple configurations for Altera FPGAs
148922: 10/09/10: Re: Question about OC PCI Cores
148935: 10/09/13: Re: Question about OC PCI Cores
148937: 10/09/13: Re: Question about OC PCI Cores
148941: 10/09/14: Re: Question about OC PCI Cores
148943: 10/09/14: Re: Question about OC PCI Cores
148967: 10/09/16: Re: Question about OC PCI Cores
148969: 10/09/16: Re: Question about OC PCI Cores
149182: 10/10/06: Driving a design via TCP/IP
149185: 10/10/06: Re: Driving a design via TCP/IP
149186: 10/10/06: Re: Driving a design via TCP/IP
149189: 10/10/06: Re: Driving a design via TCP/IP
149199: 10/10/07: Re: Driving a design via TCP/IP
149208: 10/10/07: Re: Driving a design via TCP/IP
149239: 10/10/11: Re: Driving a design via TCP/IP
149241: 10/10/11: Re: i don't have any idea to select write mode at ASMI_PARALLEL
149287: 10/10/14: Re: FPGAOptim0208r available
149291: 10/10/14: Re: store data into fpga
149524: 10/11/02: Re: Nios 2 Cyclone II board problem with simple logic
149528: 10/11/02: Re: Nios 2 Cyclone II board problem with simple logic
149538: 10/11/03: Re: Nios 2 Cyclone II board problem with simple logic
149657: 10/11/15: Re: cool BGA pattern
149662: 10/11/15: Cypres PSoC devices - hdl entry for digital sections?
149664: 10/11/15: Re: Cypres PSoC devices - hdl entry for digital sections?
149758: 10/11/23: Re: Debugging with a single LED
149781: 10/11/24: Re: Brain Cramps...
149786: 10/11/24: Re: Debugging with a single LED
149789: 10/11/24: Re: Altera EP2C8A -- dead PLL
149860: 10/11/29: Re: Brain Cramps...
149878: 10/11/30: Re: PCI Architecture Question for Data Acquisition Board
149896: 10/12/01: Re: PCI Architecture Question for Data Acquisition Board
149901: 10/12/01: Re: PCI Architecture Question for Data Acquisition Board
150044: 10/12/07: Re: Opinions on Lattice ECP3
150508: 11/01/25: Re: FPGA changes behaviour when the resource's usage percentage changes
150543: 11/01/26: Re: FPGA changes behaviour when the resource's usage percentage changes
150648: 11/01/31: Re: FPGA changes behaviour when the resource's usage percentage changes
150759: 11/02/09: Re: Designing in Altium
150959: 11/02/24: Re: Simulating mutiplication of 'X' with '0'
150969: 11/02/25: Re: Simulating mutiplication of 'X' with '0'
150970: 11/02/25: Re: Simulating mutiplication of 'X' with '0'
151114: 11/03/08: Re: IP Core Delivery Format Info
151120: 11/03/08: Re: IP Core Delivery Format Info
151139: 11/03/10: Re: pcb&bitstream
151180: 11/03/14: Re: pcb&bitstream
151183: 11/03/14: Re: pcb&bitstream
151237: 11/03/17: Re: pcb&bitstream
151416: 11/04/05: Re: Ideal FPGA Development Kit
151458: 11/04/11: Re: Altium Limited closing up shop - Altium Designer discontinued
151624: 11/04/27: Re: Excess Stratix IV and SIII parts inventory
151712: 11/05/09: Re: Soft Processors and Licensing
151769: 11/05/16: Re: Counter clocks on both edges sometimes, but not when different IO pin is used
151782: 11/05/18: Re: Scoping a glitch
151787: 11/05/18: Re: Scoping a glitch
152023: 11/06/23: Re: Sporadic simulation result with modelsim
152031: 11/06/23: Re: Sporadic simulation result with modelsim
152306: 11/08/05: QuartusII Ver11.0 programmer problems?
152308: 11/08/05: Re: Regarding process time calculation
152332: 11/08/10: Re: QuartusII Ver11.0 programmer problems?
152778: 11/10/21: Re: Peter Alfke has passed away
152779: 11/10/21: Re: Doulos training courses at Xilinx
<nial@nialstewartdevelopments.co.uk>:
136539: 08/11/21: Re: Announce: HSMC General Purpose Interface Board for Altera Dev
Niall Battson:
38707: 02/01/22: Re: Image Processing on FPGAs. Dose System Generator help??
45400: 02/07/22: Re: Do you know a parallel algorithym for 2D convolution
Niall Murphy:
27231: 00/11/16: Re: ANNOUNCE: Checksum and CRC Code/Article
NialS:
146060: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
146064: 10/03/04: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
Nic:
7025: 97/07/24: Re: free FPGA software from actel
7053: 97/07/27: Re: Why fast message delete in this group? - date format "flame"
8608: 98/01/13: Re: Parallel port interface
9134: 98/02/24: Re: Correlation implementation...
nic_o_mat@msn.com:
143137: 09/09/23: Re: Xilinx XST and counter synthesis problem
143174: 09/09/24: Re: Xilinx XST and counter synthesis problem
143192: 09/09/25: Re: Xilinx XST and counter synthesis problem
Nicholas Brown:
17304: 99/07/19: Xilinx/Synopsys License Problem
17309: 99/07/20: Re: Xilinx/Synopsys License Problem
17339: 99/07/21: Xilinx Foundation Beginner Question
17361: 99/07/22: Re: Question Resolved, Thanks
17430: 99/07/27: Xilinx Fountation 1.5 Question
17511: 99/08/03: Re: Xilinx/Synopsys License Problem
Nicholas C. Weaver:
5273: 97/02/03: Back annotation under Workview Office/Xilinx...
5374: 97/02/11: Re: DES Challenge
5843: 97/03/20: Re: Is this really possible?
6721: 97/06/19: Building Homebrew Tools for Xilinx 4K
7685: 97/10/02: Re: bidirectional bus problem
14199: 99/01/19: Experience with Xilinx PCI
15774: 99/04/13: Using the temperature diode on the virtex...
15819: 99/04/15: Re: Obsolete Xilinx series - how to use them?
15873: 99/04/17: Re: XC4000 LUT on the fly programming
16026: 99/04/28: Re: Need HELP!!! Hurry
16196: 99/05/08: Re: BGA Prototyping ?
19564: 99/12/31: Re: Design security
19737: 00/01/10: Re: XC4000 Configuration Bitstream structure
19765: 00/01/11: Re: XC4000 Configuration Bitstream structure
19884: 00/01/16: Re: Partly reprogrammable FPGAs
20087: 00/01/26: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20116: 00/01/27: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20685: 00/02/17: Re: Looking for a small, fast CPU core for FPGA
20841: 00/02/23: Re: Looking for a small, fast CPU core for FPGA
21487: 00/03/23: Re: FPGA openness
21504: 00/03/23: Re: FPGA openness
21545: 00/03/24: Re: FPGA openness
21547: 00/03/24: Re: Clock disabling
21593: 00/03/26: Re: FPGA openness
22188: 00/04/30: Re: How to Prevent theft of FPGA design
22189: 00/04/30: Re: How to Prevent theft of FPGA design
22259: 00/05/03: Re: Why are there no "cheap" FPGAs?
22278: 00/05/04: Re: How to Prevent theft of FPGA design
22299: 00/05/04: Re: How to Prevent theft of FPGA design
22301: 00/05/04: Re: How to Prevent theft of FPGA design
22306: 00/05/04: Re: How to Prevent theft of FPGA design
22309: 00/05/04: Re: How to Prevent theft of FPGA design
22313: 00/05/04: Re: How to Prevent theft of FPGA design
22320: 00/05/04: Re: How to Prevent theft of FPGA design
22333: 00/05/05: Re: How to Prevent theft of FPGA design
22337: 00/05/05: Re: How to Prevent theft of FPGA design
22355: 00/05/05: Re: How to Prevent theft of FPGA design
22578: 00/05/12: Re: Future of FPGAs?
22713: 00/05/19: Re: FPGA emultaion of a microprocessor
22770: 00/05/23: Re: Xilinx Logic Cell counts and carry chains
22912: 00/06/01: Re: Microprocessors in FPGA
22988: 00/06/07: Re: XCV vs. XCV-E ?
23111: 00/06/14: Re: Mutating Virtex FPGA
23235: 00/06/18: Re: Problem copying text from the Spartan II data sheet
23326: 00/06/22: Re: Looking for 'FREE' FPGA software
23338: 00/06/22: Re: FPGAs for Bioinformatics accelerators
23354: 00/06/23: Re: Looking for 'FREE' FPGA software
23372: 00/06/23: Re: Looking for 'FREE' FPGA software
23847: 00/07/12: Re: C++/Java generators vs. synthesizers
24093: 00/07/26: Re: Power PC with Xilinx - what do you think?
24289: 00/08/02: Re: 32-input AND and 100-input OR - can I do it fast?
24355: 00/08/04: Re: 5v -> 1.8v switcher supply for FPGA ??
24736: 00/08/17: Re: When will SpartanII be in ditribution
25046: 00/08/24: Re: largest fpga in the industry
25047: 00/08/24: Re: largest fpga in the industry
25053: 00/08/24: Re: create a RAM in a Virtex
25121: 00/08/26: Re: Why Aren't Anti-Fuse FPGAs The Biggest FPGAs In The World?
25165: 00/08/29: Re: largest fpga in the industry
25170: 00/08/29: Re: Spartan II vs. Virtex
25268: 00/09/03: Re: Balls!
25387: 00/09/09: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25599: 00/09/15: Re: hardware compatibility and patent infringement
25688: 00/09/17: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
25702: 00/09/18: Re: virtex shape
45616: 02/07/29: Re: secure FPGA
45620: 02/07/29: Re: secure FPGA
45629: 02/07/30: Re: logic elements v/s logic cells
45698: 02/08/01: Pricing on Virtex 2 pro XC2VP4?
45777: 02/08/05: Re: AES (rijndael) Ip core
45845: 02/08/07: Re: Programming bits reverse engineering
45856: 02/08/07: Re: AES (rijndael) algorithm coding time
45919: 02/08/11: Re: I seek a FPFA developer
45953: 02/08/12: Symplify Hacking/munging question...
45959: 02/08/12: Re: Symplify Hacking/munging question...
45960: 02/08/12: Re: Symplify Hacking/munging question...
46026: 02/08/15: Re: Xilinx tools: which one? Esp. schematic
46061: 02/08/15: Re: Xilinx tools: which one? Esp. schematic
46066: 02/08/16: Re: Xilinx tools: which one? Esp. schematic
46081: 02/08/16: Re: Fun FPGA system
46085: 02/08/16: Re: Xilinx tools: which one? Esp. schematic
46359: 02/08/27: Re: FPGA speed level
46407: 02/08/28: Re: My SpartanII thinks it's a Virtex??
46465: 02/08/30: Re: XNF vs. EDIF
46469: 02/08/30: Re: gate the main FPGA clk
46489: 02/09/01: Re: Virtex/E/2/2P area efficient addmux, reiterating PAR timing modeler enhancement request
46496: 02/09/01: Re: gate the main FPGA clk
46500: 02/09/01: Logic on Virtex CLB, what's the YB and XB used for?
46529: 02/09/02: Re: Hardware Code Morphing?
46530: 02/09/02: Re: Hardware Code Morphing?
46532: 02/09/02: Re: Hardware Code Morphing?
46534: 02/09/02: Re: Hardware Code Morphing?
46565: 02/09/03: Re: Logic on Virtex CLB, what's the YB and XB used for?
46638: 02/09/04: Re: why the need for HIGH speed design?
46723: 02/09/06: Re: Performance degradation when put on an FPGA ?
46777: 02/09/09: Re: minimalist FPGA system
46828: 02/09/09: Re: minimalist FPGA system
46983: 02/09/13: Re: exploiting metastability
47013: 02/09/14: Re: Xilinx TBUFs
47087: 02/09/17: Re: 1.8V regulator needed for Spartan IIE
47105: 02/09/17: Any Virtex 2 pro development boards yet?
47133: 02/09/18: Re: Any Virtex 2 pro development boards yet?
47230: 02/09/20: Re: Multiple divide by 10
47315: 02/09/23: Re: Fast serial interconnect bus using spartan-II
47393: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
47436: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
47534: 02/09/27: Re: Dual Port RAM
47550: 02/09/28: Re: Block Ram maximum speed
47554: 02/09/28: Re: Block Ram maximum speed
47704: 02/10/02: Re: C\C++ to VHDL Converter
47710: 02/10/02: Re: ANN: Embedded processor for Tcl language
47760: 02/10/03: Re: A MAC design question
47772: 02/10/03: Re: ANN: Embedded processor for Tcl language
47851: 02/10/05: Re: TCP/IP in FPGA
47864: 02/10/06: Re: ANN: Embedded processor for Tcl language
47909: 02/10/07: Re: Low power design
47911: 02/10/07: Re: C\C++ to VHDL Converter
47917: 02/10/07: Re: String Matching Developments on FPGA's
47952: 02/10/08: Re: Academic FPGA Cad Tools
47988: 02/10/09: Re: Simple Counters in Xilinx Spartan II
48040: 02/10/10: Re: Intel ARM 'XScale' cores as IP blocks that can be synthesized into an FPGA/ASIC?
48124: 02/10/11: Re: Why can Xilinx sw be as good as Altera's sw?
48164: 02/10/12: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
48168: 02/10/12: Re: FPGA breadboard with a SmartMedia Card to store the bit file.
48192: 02/10/13: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
48221: 02/10/14: Re: Why can Xilinx sw be as good as Altera's sw?
48234: 02/10/14: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
48236: 02/10/14: Re: Why can Xilinx sw be as good as Altera's sw?
48246: 02/10/15: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
48287: 02/10/15: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
48291: 02/10/15: Re: Xilinx microblaze vs. picoblaze
48297: 02/10/15: Re: Xilinx microblaze vs. picoblaze
48304: 02/10/15: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48313: 02/10/15: Re: Open Source and other issues.... (was Re: Why can Xilinx sw be as good as Altera's sw?)
48342: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48348: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48361: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48365: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48366: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48383: 02/10/16: Re: Xilinx microblaze vs. picoblaze
48385: 02/10/16: Re: Why can Xilinx sw be as good as Altera's sw?
48396: 02/10/17: Re: Xilinx microblaze vs. picoblaze
48397: 02/10/17: Re: Xilinx microblaze vs. picoblaze
48405: 02/10/17: Re: Xilinx microblaze vs. picoblaze
48444: 02/10/17: Re: Hobbyist FPGA
48445: 02/10/17: Re: Hobbyist FPGA
48505: 02/10/18: Re: Cyclic Redundancy Check generator
48668: 02/10/22: Silly Virtex 2 Pro question...
48690: 02/10/22: Re: low power embedded FPGA
48741: 02/10/23: Re: How full is too full?
48742: 02/10/23: Re: More Newbie Questions - What teaching resources
48795: 02/10/24: Re: Silly Virtex 2 Pro question...
48946: 02/10/28: Re: High Performance FPGA's - Xilinx and ??????
49088: 02/10/31: Re: V2Pro board with gigabit Ethernet?
49391: 02/11/11: Silly FPGA Arch question...
49394: 02/11/11: Re: Silly FPGA Arch question...
49443: 02/11/12: Re: new to fpga, what language is better to start with
49457: 02/11/12: Re: HDL vs RTL
49466: 02/11/12: Re: Feedback from a 200 MHz Virtex2 design
49467: 02/11/12: Re: HDL vs RTL
49584: 02/11/16: Re: DLL again :-)
49615: 02/11/18: Re: Virtex is the 4th Xilinx Fpga generation
49664: 02/11/19: Re: Metastability in FPGAs
49808: 02/11/21: Re: Metastability in FPGAs
49832: 02/11/22: Re: Metastability in FPGAs
49840: 02/11/22: Re: Metastability in FPGAs
49962: 02/11/26: Re: Initialising Spartan's Block RAM
50290: 02/12/07: Re: Virtex archtecture question
50301: 02/12/08: Re: Virtex archtecture question
50313: 02/12/08: Re: Virtex archtecture question
50557: 02/12/12: Re: what makes an implementation a patent?
50613: 02/12/14: Re: AN: FPGA-based Personal Logic Analyzer, 500MHz, $166
50693: 02/12/17: Re: MPEG FPGA
50851: 02/12/20: Re: Hi xilinx
50859: 02/12/20: Re: thermal issues on FPGA
50861: 02/12/20: Re: FPGA Supercomputing opportunity
50863: 02/12/21: Re: FPGA Supercomputing opportunity
50989: 02/12/25: Re: FPGA accelerated FPGA/ASIC tools
51051: 02/12/28: Re: FPGA accelerated FPGA/ASIC tools
51054: 02/12/28: Re: Virtex architecture newbie question
51102: 03/01/01: Re: Any Xilinx Design Language(.xdl) document?
51119: 03/01/02: Re: Any Xilinx Design Language(.xdl) document?
51287: 03/01/10: Re: Virtex-II Pro misfire?
51291: 03/01/10: Re: Virtex-II Pro misfire?
51341: 03/01/11: Re: Virtex-II Pro misfire?
51366: 03/01/12: Re: Virtex-II Pro misfire?
51388: 03/01/12: Re: Open FPGA please!
51437: 03/01/13: Re: Virtex-II Pro misfire?
51438: 03/01/13: Re: Open FPGA please!
51471: 03/01/14: Re: SChematic design approach compared to VHDL entry approach
51478: 03/01/14: Re: SChematic design approach compared to VHDL entry approach
51480: 03/01/14: Re: Open FPGA please!
51489: 03/01/14: Re: Off Topic: Single Board Computers?
51496: 03/01/15: Re: Open FPGA please!
51508: 03/01/15: Re: Spartan II found on Ebay
51571: 03/01/16: Re: Schematic design approach compared to VHDL entry approach
51574: 03/01/16: Re: SChematic design approach compared to VHDL entry approach
51589: 03/01/16: Re: Support for older Virtex
51830: 03/01/23: Re: What's a "D-MIPS"?
51861: 03/01/23: Re: free x86 core ip
51880: 03/01/24: Re: AES(Rijindal) CTR with CBC MAC
51893: 03/01/24: Re: AES(Rijindal) CTR with CBC MAC
51913: 03/01/25: Re: Why so many pins?
51916: 03/01/26: Re: Why so many pins?
51918: 03/01/26: Re: Why so many pins?
51928: 03/01/26: Re: Why so many pins?
52052: 03/01/29: Re: Reconfigure only some elements
52158: 03/02/03: Re: which microprocessor core?
52241: 03/02/05: Re: difference between pci2.1 and pci2.2
52242: 03/02/05: Re: difference between pci2.1 and pci2.2
52313: 03/02/06: Re: Clock Enables
52332: 03/02/07: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
52338: 03/02/07: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
52414: 03/02/08: Re: Multicontext FPGA
52458: 03/02/10: Re: Multicontext FPGA
52465: 03/02/10: Re: Multicontext FPGA
52471: 03/02/11: Re: Multicontext FPGA
52491: 03/02/11: Re: Multicontext FPGA
52558: 03/02/13: Re: Multicontext FPGA
52574: 03/02/14: Re: Multicontext FPGA
52666: 03/02/18: Re: About automatically programming my FPGA
52691: 03/02/19: Re: Should I choose Xilink or Altera for a small project
52701: 03/02/19: Re: PCB Design for a Xilinx Spartan-II FPGA
52779: 03/02/21: Re: Should I choose Xilink or Altera for a small project
52799: 03/02/22: Re: spartan III what is it?
52944: 03/02/26: Re: FPGA arch.
53015: 03/02/28: Re: How to maintain pipeline delays
53017: 03/02/28: PCB board design software vs outsourcing?
53019: 03/02/28: Re: PCB board design software vs outsourcing?
53087: 03/03/03: Re: FPGA demo board schematic
53273: 03/03/09: Xilinx/Altera product timeline?
53324: 03/03/11: Re: Are there any FPGA magazines/journals?
53565: 03/03/16: Re: What is the diff between FPGA and CPLD?
53732: 03/03/20: Re: Altera ACEX 1K
53816: 03/03/24: Re: Does Xilinx have self-boot option like Cypress?
53819: 03/03/24: Re: Does Xilinx have self-boot option like Cypress?
53824: 03/03/24: Re: Does Xilinx have self-boot option like Cypress?
53827: 03/03/24: Re: Does Xilinx have self-boot option like Cypress?
53829: 03/03/24: Re: triple des
53892: 03/03/26: Re: Virtex II pro board design question
53900: 03/03/26: Re: triple des
54020: 03/03/31: Re: Xilinx announces 90nm sampling today!
54028: 03/03/31: Re: Xilinx announces 90nm sampling today!
54155: 03/04/03: Re: What is DA and SLR16?
54160: 03/04/03: Re: What is DA and SLR16?
54171: 03/04/04: Re: Spartan vs. Cyclone for arithmetic functions
54194: 03/04/04: Re: Xilinx V2.1i Licensing
54199: 03/04/04: Re: Xilinx V2.1i Licensing
54202: 03/04/04: Re: Xilinx V2.1i Licensing
54206: 03/04/04: Re: Xilinx V2.1i Licensing
54208: 03/04/04: Re: Xilinx V2.1i Licensing
54241: 03/04/05: Re: Xilinx announces 90nm sampling today!
54258: 03/04/06: Re: Should I bother with Xilinx Foundation 1.5 vs 2.1?
54298: 03/04/07: Re: Spartan-3 in docsan Webpack release notes... a joke???
54491: 03/04/11: Re: fpga fault tolerence.
54728: 03/04/16: Xilinx Virtex switchbox details...
54877: 03/04/21: Spartan 3 Interconnect structure...
54884: 03/04/21: Re: Boycott All Xilinx products untill they correct all ISE softwareerrors
55448: 03/05/08: Re: Design Protection Spartan2
55503: 03/05/10: Re: Encrypted bitstream - battery lifetime problem
55564: 03/05/12: Re: How do I know of Xilinx connectivity restrictions?
55601: 03/05/13: Re: Spartan3 DLL?
55607: 03/05/14: Re: Spartan3 DLL?
55653: 03/05/15: Re: how to calculate the gate count required for a FPGA design
55688: 03/05/15: Re: Low power, high temperature CPLD
55690: 03/05/15: Re: Low power, high temperature CPLD
55771: 03/05/19: Re: a (PC) workstation for FPGA development
55794: 03/05/20: Re: a (PC) workstation for FPGA development
55807: 03/05/20: Re: a (PC) workstation for FPGA development
56533: 03/06/08: More details on V2Pro-X?
56556: 03/06/09: Re: Masters Project Topic
56636: 03/06/10: Re: Pseudo random shift register - > DAC
56728: 03/06/12: Re: RISC CPU plus FPGA in small package
56833: 03/06/17: Re: BGA Xray inspection costs?
56954: 03/06/19: Re: Dr. Leaky responds
57022: 03/06/20: Re: No longer talking about power consumption....
57126: 03/06/24: Re: MIPS instruction set?
57262: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
57326: 03/06/27: Re: why so many problems Xilinx ?
57331: 03/06/27: Re: MIPS instruction set?
57344: 03/06/27: Re: MIPS instruction set?
57345: 03/06/27: Re: why so many problems Xilinx ?
57420: 03/06/30: Re: SPARTAN-3 vs. VIRTEX-II
57434: 03/06/30: Re: Cyclone vs Spartan-3
57454: 03/07/01: Re: SPARTAN-3 vs. VIRTEX-II
57554: 03/07/02: Re: Cyclone vs Spartan-3
57674: 03/07/03: Re: Cyclone vs Spartan-3
57682: 03/07/03: Re: Why not DDR in FPGAs?
57850: 03/07/08: Re: Rant mode ON
57881: 03/07/09: Re: Rant mode ON
58024: 03/07/12: Re: Cyclone vs Spartan-3
58089: 03/07/14: Re: Booth Multipliers
58136: 03/07/15: Re: PROM size for spartan
58142: 03/07/15: Re: PROM size for spartan
58314: 03/07/20: Re: Is a Virtex-II Pro family a hands-down winner for DSP ?
58789: 03/08/01: Re: Multi Cycle path and False paths
58790: 03/08/01: Re: Size does matter
58806: 03/08/01: Re: Size does matter
58839: 03/08/02: Re: Multi Cycle path and False paths
58847: 03/08/02: Re: beginner
58860: 03/08/03: Re: Size does matter
59150: 03/08/10: Re: a quick searching problem
59214: 03/08/12: Re: PalmChip Patent
59234: 03/08/13: Re: PalmChip Patent
59238: 03/08/13: Re: PalmChip Patent
59601: 03/08/23: Re: Thinking out loud about metastability
59642: 03/08/25: Re: Thinking out loud about metastability
59645: 03/08/25: Re: Thinking out loud about metastability
59657: 03/08/25: Re: Thinking out loud about metastability
59682: 03/08/26: Re: Enhancing PAR with FPGA floorplanners
59705: 03/08/26: Re: Free FPGA samples anywhere?
59766: 03/08/28: Re: Thinking out loud about metastability
59791: 03/08/28: Re: Moving Sum
59796: 03/08/28: Re: Thinking out loud about metastability
59813: 03/08/28: Re: Thinking out loud about metastability
60000: 03/09/03: Re: Thinking out loud about metastability
60009: 03/09/03: Re: Thinking out loud about metastability
60024: 03/09/03: Re: Thinking out loud about metastability
60279: 03/09/09: Re: opinions are OK
60365: 03/09/11: Re: The real history of computer architecture: the short form
61222: 03/09/30: Re: doubling clock rate does what to power consumption?
61292: 03/10/01: Any word on the V2Pro-X?
61369: 03/10/02: Re: High-performance workstation
61666: 03/10/08: Re: Xilinx dedicated multiers vs multipliers in slice fabric
61777: 03/10/10: Re: pci-x133 to parallel pci-66
61911: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
61953: 03/10/15: Ph.inisheD.
61964: 03/10/15: Coredump on partial reconfig...
61977: 03/10/15: Re: Virtex-II Pro ML-300 Evaluation Platform
62023: 03/10/16: Re: Ph.inisheD.
62031: 03/10/17: Re: Spartan-3 non-ES availability, and misleading pricing info
62101: 03/10/19: Re: CPU vs. FPGA vs. RAM
62149: 03/10/20: Re: CPU vs. FPGA vs. RAM
62172: 03/10/21: Re: CPU vs. FPGA vs. RAM
62233: 03/10/22: The Luddite Needs Reference Books...
62420: 03/10/29: Re: How to protect fpga based design against cloning?
62492: 03/10/30: Re: How to protect fpga based design against cloning?
62526: 03/10/31: Re: How to protect fpga based design against cloning?
62559: 03/11/01: Re: How to protect fpga based design against cloning?
62599: 03/11/03: Re: How to protect fpga based design against cloning?
62672: 03/11/04: Silly ML300 question...
62752: 03/11/06: Re: Tools Tree
62833: 03/11/09: Re: FPGAs and DRAM bandwidth
62863: 03/11/10: Re: Home grown CPU core legal?
62866: 03/11/10: Re: FPGAs and DRAM bandwidth
62884: 03/11/10: Re: Home grown CPU core legal?
62897: 03/11/10: Re: FPGAs and DRAM bandwidth
63013: 03/11/12: Re: Home grown CPU core legal?
63014: 03/11/12: Re: Home grown CPU core legal?
63109: 03/11/15: Re: XILINX Foundation Series 3_1i Problem with installation...
63332: 03/11/19: Re: State Machines....
63564: 03/11/25: Re: 5V I/O with 1.8V Core
63582: 03/11/26: Re: 5V I/O with 1.8V Core
63656: 03/11/27: Re: 5V I/O with 1.8V Core
63660: 03/11/27: Re: 5V I/O with 1.8V Core
63680: 03/11/28: Re: 5V I/O with 1.8V Core
63768: 03/12/03: Re: Command line in Windows?
63808: 03/12/04: Re: Ideal Development Machine Specifications
64075: 03/12/15: Re: datasheet needed!
64258: 03/12/22: Re: Hyperthreading vs. Dual proc
64467: 04/01/05: Re: Hyperthreading vs. Dual proc
65287: 04/01/23: Re: Spirit on Mars
66125: 04/02/12: 10 GigE demoboards...
66233: 04/02/15: Re: RFC: ARM+FPGA tiny board
66246: 04/02/16: Re: Xilinx DB-01 info?
66773: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
66845: 04/02/27: Re: Stratix 2 ALUT architecture patented ?
66846: 04/02/27: Re: Stratix 2 ALUT architecture patented ?
66857: 04/02/27: Re: Stratix 2 ALUT architecture patented ?
67069: 04/03/04: Re: Global reset question?
67072: 04/03/04: Re: Spec VPR Results for various processors...
67112: 04/03/05: Re: Global reset question?
67207: 04/03/08: Re: NEWS: Xilinx announces acquisition of Triscend
67283: 04/03/09: Re: copy protection on FPGA using embedded serial number
67357: 04/03/10: Re: copy protection on FPGA using embedded serial number
67415: 04/03/11: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67451: 04/03/12: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67470: 04/03/12: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67472: 04/03/12: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67570: 04/03/15: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67596: 04/03/15: Re: Xilinx Vertex-II Pro Logic Cells compared to Slices
67613: 04/03/16: Re: copy protection on FPGA using embedded serial number
69193: 04/04/29: Re: best machine setup for ISE ??
69204: 04/04/30: Re: best machine setup for ISE ??
69751: 04/05/19: Re: Nios II Going Live...
69756: 04/05/19: Re: Nios II Going Live...
69778: 04/05/19: Re: Nios II Going Live...
69834: 04/05/21: Re: Never right, always room for improvement
69996: 04/05/26: Re: Nios II = Microblaze
Nicholas Collin Paul de Gloucester:
158554: 15/12/23: Re: FPGA for a beginner
158572: 16/01/04: Re: Programming waveshare core3s250e with Impact and ISE 14.1
158577: 16/01/05: Re: Programming waveshare core3s250e with Impact and ISE 14.1
Nicholas Doyle:
3200: 96/04/24: Atmel vs Xilinx
Nicholas Girde:
52273: 03/02/05: Switching synthesis tools
52384: 03/02/07: Re: Switching synthesis tools
52562: 03/02/13: Re: Switching synthesis tools
52643: 03/02/17: Re: Synopsys FC2 version 3.7.2 best so far
Nicholas Kinar:
142206: 09/07/28: Re: cool chart
142234: 09/07/29: Re: cool chart
142679: 09/08/25: Reading from ADC and writing to DAC at same time
142682: 09/08/25: Re: Reading from ADC and writing to DAC at same time
142683: 09/08/25: Re: Reading from ADC and writing to DAC at same time
142686: 09/08/26: Re: Reading from ADC and writing to DAC at same time
142687: 09/08/26: Re: Reading from ADC and writing to DAC at same time
142690: 09/08/26: Re: Reading from ADC and writing to DAC at same time
142694: 09/08/26: Re: Reading from ADC and writing to DAC at same time
142695: 09/08/26: Re: Reading from ADC and writing to DAC at same time
142696: 09/08/26: Re: Reading from ADC and writing to DAC at same time
142697: 09/08/26: Re: Reading from ADC and writing to DAC at same time
142700: 09/08/26: Re: Reading from ADC and writing to DAC at same time
142701: 09/08/26: Re: Reading from ADC and writing to DAC at same time
142703: 09/08/26: Re: Reading from ADC and writing to DAC at same time
142705: 09/08/27: Re: Reading from ADC and writing to DAC at same time
142708: 09/08/27: Re: Reading from ADC and writing to DAC at same time
142709: 09/08/27: Re: Reading from ADC and writing to DAC at same time
142711: 09/08/27: Is free-to-use IP included with downloadable FPGA tools?
142714: 09/08/27: Re: Is free-to-use IP included with downloadable FPGA tools?
142715: 09/08/27: Re: Is free-to-use IP included with downloadable FPGA tools?
142722: 09/08/28: Re: Reading from ADC and writing to DAC at same time
142723: 09/08/28: Re: Is free-to-use IP included with downloadable FPGA tools?
142725: 09/08/28: Re: Is free-to-use IP included with downloadable FPGA tools?
142727: 09/08/28: Re: Is free-to-use IP included with downloadable FPGA tools?
142728: 09/08/28: Re: Is free-to-use IP included with downloadable FPGA tools?
142729: 09/08/28: Re: Is free-to-use IP included with downloadable FPGA tools?
142730: 09/08/28: Re: Is free-to-use IP included with downloadable FPGA tools?
142731: 09/08/28: Re: Is free-to-use IP included with downloadable FPGA tools?
142732: 09/08/28: Re: Is free-to-use IP included with downloadable FPGA tools?
142734: 09/08/28: Re: Is free-to-use IP included with downloadable FPGA tools?
142760: 09/08/30: Selection of external clocks for FPGA system and bus interfacing
142770: 09/08/31: Re: Selection of external clocks for FPGA system and bus interfacing
142771: 09/08/31: Re: Selection of external clocks for FPGA system and bus interfacing
144678: 09/12/22: Strange behavior with serial ADC chip select and MISO pin
144690: 09/12/23: Re: Strange behavior with serial ADC chip select and MISO pin
144691: 09/12/23: Re: H.264 on Spartan3A DSP
144692: 09/12/23: Re: Strange behavior with serial ADC chip select and MISO pin
144715: 09/12/27: Re: Strange behavior with serial ADC chip select and MISO pin
144815: 10/01/06: Databus crossing clock domains with data freeze
144819: 10/01/06: Re: Databus crossing clock domains with data freeze
144820: 10/01/06: Re: Databus crossing clock domains with data freeze
144821: 10/01/06: Re: Databus crossing clock domains with data freeze
144822: 10/01/06: Re: Databus crossing clock domains with data freeze
144823: 10/01/06: Re: Databus crossing clock domains with data freeze
144824: 10/01/06: Re: Databus crossing clock domains with data freeze
144825: 10/01/06: Re: Databus crossing clock domains with data freeze
144826: 10/01/06: Re: Databus crossing clock domains with data freeze
144836: 10/01/07: Re: Databus crossing clock domains with data freeze
144837: 10/01/07: Re: Databus crossing clock domains with data freeze
144843: 10/01/07: Re: Difference among Virtex Families, FPGA Books
144850: 10/01/07: Re: Difference among Virtex Families, FPGA Books
Nicholas Kubiak:
120155: 07/06/01: Tristate ipcore problem with XPS
Nicholas Pappas:
24438: 00/08/08: HELP! Strange Xilinx Software Error
Nicholas Paul Collin Gloster:
119419: 07/05/18: Re: seeking insights for potential reconfigurable computing application platforms
Nicholas Paul Collin Gloucester:
138664: 09/03/03: Re: XILINX sysgen cordic divider
Nicholas Velastegui:
23619: 00/07/03: Re: First time chip design. Is my roadmap correct ?
Nicholas Weaver:
26503: 00/10/18: Stupid Virtex Trick...
26535: 00/10/19: Re: How safe is the algorithm implemented with FPGA?
26542: 00/10/19: Re: How safe is the algorithm implemented with FPGA?
26572: 00/10/20: Re: How safe is the algorithm implemented with FPGA?
26663: 00/10/24: Re: How safe is the algorithm implemented with FPGA?
26696: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
26699: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
26702: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
26703: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
26711: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
26712: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
26751: 00/10/27: Re: How safe is the algorithm implemented with FPGA?
26695: 00/10/25: Re: Design theft story in EDN. New security ?
26857: 00/11/01: Re: JBits
26886: 00/11/02: Re: cryptography/Block ciphers
33174: 01/07/18: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
33848: 01/08/06: Re: Slightly off topic - PCs for running FPGA tools
36224: 01/11/02: Re: Open configuration bitstreams
36427: 01/11/08: Re: FPGA Wish list
36432: 01/11/08: Re: FPGA Wish list
36433: 01/11/08: Re: FPGA Wish list
36810: 01/11/20: Re: Elliptic Curves
37082: 01/11/29: Re: 128-bit scrambling and CRC computations
37149: 01/12/01: Re: 128-bit scrambling and CRC computations
37326: 01/12/07: Re: where is designed FPGA for apple II computer...?
37965: 01/12/28: Re: Choice of Processor Cores in FPGAs - Both Embedded & Soft
38011: 01/12/31: Stupid Foundation Question (Hey Peter, some Kindergarden stuff for you)
38043: 02/01/02: Thanks all....Re: Stupid Foundation Question
38102: 02/01/05: Re: ASIC faster than VirtexII FPGA?
38171: 02/01/08: Re: 128 bit compare delay kill me!
38172: 02/01/08: Re: 128 bit compare delay kill me!
39546: 02/02/13: Suggestions on distributing a module...
39783: 02/02/19: Re: Faster designs
40071: 02/02/26: Anyone have a delidded Spartan II?
40157: 02/03/01: Re: Altera FPGAs
40194: 02/03/01: Xilinx Virtex Family die photos...
40217: 02/03/02: Re: Xilinx Virtex Family die photos...
40365: 02/03/06: Re: exceeding 2GB limits in xilinx
40367: 02/03/06: Re: Xilinx announces Virtex-II Pro is shipping
40410: 02/03/06: Re: exceeding 2GB limits in xilinx
40423: 02/03/07: Announcement: Freely Available Rijndael Core for Virtex FPGAs.
40429: 02/03/07: Re: exceeding 2GB limits in xilinx
40674: 02/03/12: Re: Article in March Embedded Systems - "The Death of Hardware Engineering"...
40678: 02/03/12: Re: cyphers
40930: 02/03/18: Re: questions from a newby
41283: 02/03/25: Re: question on LFSR
41658: 02/04/04: Re: powerpc in virtex2pro
41659: 02/04/04: Re: powerpc in virtex2pro
41660: 02/04/04: Re: hand placement
41661: 02/04/04: Re: powerpc in virtex2pro
41668: 02/04/04: Re: powerpc in virtex2pro
41670: 02/04/04: Re: powerpc in virtex2pro
41688: 02/04/05: Re: hand placement
41694: 02/04/05: Re: hand placement
41700: 02/04/05: Re: hand placement
41735: 02/04/06: Re: hand placement
42017: 02/04/12: Stupid .ngd file questions....
42233: 02/04/18: Re: 1000 I/O Pins -- What is cheapest FPGA?
42237: 02/04/18: Re: 1000 I/O Pins -- What is cheapest FPGA?
42258: 02/04/19: Re: 1000 I/O Pins -- What is cheapest FPGA?
42301: 02/04/19: Re: 1000 I/O Pins -- What is cheapest FPGA?
42303: 02/04/19: Re: 1000 I/O Pins -- What is cheapest FPGA?
42436: 02/04/24: Re: Xilinx Easypath- Selling parts with known defects
42501: 02/04/25: Re: Newbie Advice Please
42571: 02/04/28: Re: SpartanII design considerations...
42591: 02/04/28: Re: Xilinx
42598: 02/04/29: Re: FlexLM
42626: 02/04/29: Re: Partial reconfiguration
42638: 02/04/30: Re: Does Vertex II PRO Really work?
42673: 02/04/30: Re: SpartanIIE hold timing
42683: 02/04/30: Placement, Retiming and Performance
42684: 02/04/30: Re: Xilinx Easypath- Selling parts with known defects
42972: 02/05/08: Xilinx Design Language (xdl) documentation?
43054: 02/05/10: Re: Opinions on FPGA cores - best for a commercial project?
43094: 02/05/13: Re: Architecture for high-level reconfigurable computing
43096: 02/05/13: Re: Architecture for high-level reconfigurable computing
43104: 02/05/14: Re: Architecture for high-level reconfigurable computing
43137: 02/05/14: Re: Architecture for high-level reconfigurable computing
43139: 02/05/14: Re: Architecture for high-level reconfigurable computing
43301: 02/05/18: Re: HardPath
43403: 02/05/21: Re: Addressable shift register
43512: 02/05/22: Re: 50Mhz driven - Overheat by Program?
43513: 02/05/22: Re: Time for a new computer. Suggestions?
43521: 02/05/22: Re: Routing in a 6200-like sea of gates
43555: 02/05/23: Re: Time for a new computer. Suggestions?
43558: 02/05/24: Re: Time for a new computer. Suggestions?
43585: 02/05/24: Re: Time for a new computer. Suggestions?
43685: 02/05/29: Re: Xilinx proprietary format?
43712: 02/05/30: Re: Time for a new computer. Suggestions?
43750: 02/06/01: Re: Engineering Samples for free?
43766: 02/06/01: Re: place and route simulation time
43811: 02/06/03: Re: FPGA destruction possible?
43829: 02/06/04: Re: FPGAs used to crack Xbox security
44198: 02/06/13: Re: 20,000 gates?
44211: 02/06/13: Re: must signals to ram come from a register?
44243: 02/06/14: Re: MAP problem with RLOC'ed macros
44415: 02/06/19: Re: uart code using vhdl
44420: 02/06/19: Re: new computer
44550: 02/06/23: Re: new computer
44565: 02/06/24: Re: new computer
44586: 02/06/24: Re: new computer
44684: 02/06/27: Re: why not pipeline by default?
44873: 02/07/03: Re: Bitstream Verification (JBITS)
44881: 02/07/03: Re: Bitstream Verification (JBITS)
44935: 02/07/06: Virtex manhattan distance delay model...
45088: 02/07/12: Re: Deterministic Output?
45106: 02/07/12: Re: FPGA CPU?
45109: 02/07/12: Re: FPGA CPU?
45147: 02/07/13: Re: What proportion of an FPGA's configuration data is used for routing?
45336: 02/07/19: Re: Theft protection of FPGA configuration data
45375: 02/07/20: Re: spiral / waterfall /watersluice : Which are your methods?
45380: 02/07/21: Re: spiral / waterfall /watersluice : Which are your methods?
70913: 04/07/01: Re: FPGA with fully asynchronous RAM
71688: 04/07/27: Re: ramdon noise generation
73699: 04/09/28: Re: has anyone tried implementing Serpent?
73707: 04/09/28: Re: NV on-chip memory?
73800: 04/09/29: Pricing info for Synplify Pro Xilinx...
73804: 04/09/29: Re: Pricing info for Synplify Pro Xilinx...
73823: 04/09/30: Re: DISCLOSURE : NV on-chip memory?
73829: 04/09/30: Re: ELABORATED DISCLOSURE and continued discussion : NV on-chip memory?
73837: 04/09/30: Re: ELABORATED DISCLOSURE and continued discussion : NV on-chip memory?
73859: 04/09/30: Re: ELABORATED DISCLOSURE and continued discussion : NV on-chip memory?
73955: 04/10/01: Re: NV on-chip memory?
73993: 04/10/02: Re: FPGA vs ASIC area
74003: 04/10/02: Re: NV on-chip memory?
74016: 04/10/02: Re: How to generate a signal on Xilinx Spartan II
73069: 04/09/13: ML300 Ethernet question.
73086: 04/09/14: Re: Would flash/antifuse-based vendors be more likely to disclose
73256: 04/09/16: Re: Virtex 4 released Monday, and we are still learning about it......
73402: 04/09/21: Re: Stratix II vs. Virtex 4 - features and performance
73403: 04/09/21: Re: Stratix II vs. Virtex 4 - features and performance
73444: 04/09/22: Re: Mr. Greenfield, spare us the propaganda !
73520: 04/09/22: Re: Stratix II vs. Virtex 4 - features and performance
73543: 04/09/23: Re: Stratix II vs. Virtex 4 - features and performance
73577: 04/09/24: Re: Stratix II vs. Virtex 4 - features and performance
73582: 04/09/24: Re: Stratix II vs. Virtex 4 - features and performance
74174: 04/10/05: Re: FPGA vs ASIC area -- the crucial issue is power consumption
74242: 04/10/06: Re: I need help for Xilinx Demo Board (XC40xx-PC84
74694: 04/10/16: Re: How many Altera LE's to Xilinx Slices????
75446: 04/11/05: Silly Xilinx Foundation question...
75809: 04/11/15: Re: Soft Processor Core
76171: 04/11/27: Re: Choice of FPGA device -- my view on benchmarks
76327: 04/11/30: Re: 99% Utilisation !
76333: 04/11/30: Re: 99% Utilisation !
76341: 04/11/30: Stupid tools question...
76499: 04/12/04: Re: Stupid tools question...
77445: 05/01/06: Re: San Jose job offer - need advice
77466: 05/01/07: Re: San Jose job offer - need advice
77542: 05/01/10: Re: Editing bitstream
77550: 05/01/10: Re: Editing bitstream
77580: 05/01/11: Re: Editing bitstream
77628: 05/01/12: Re: Programming and copyright
77702: 05/01/14: Re: Programming and copyright
77705: 05/01/14: Re: Programming and copyright
77732: 05/01/15: Re: Programming and copyright
77791: 05/01/17: Re: Programming and copyright
77890: 05/01/19: Very Stupid XST verilog synthesis question...
77892: 05/01/19: Re: Very Stupid XST verilog synthesis question...
78212: 05/01/26: ML310 personality modules...
78395: 05/01/31: Re: Design security
78398: 05/01/31: Re: Design security
78650: 05/02/04: Re: Benchmarks or not.
79279: 05/02/16: Re: What do future FPGA's need? (was: Updated S2 Power specs)
80108: 05/03/01: Examples with GEMAC and ML300 board?
81378: 05/03/22: ML300 Gigabit Ethernet Issues...
81401: 05/03/22: Re: ML300 Gigabit Ethernet Issues...
82218: 05/04/08: Re: Hey Xilinx
84164: 05/05/13: Stupid Question on the Urination Contest... Re: V4 vs. Stratix-II...
85573: 05/06/11: Re: computer upgrade time.
85574: 05/06/11: Re: computer upgrade time.
85575: 05/06/11: Re: computer upgrade time.
86477: 05/06/28: Re: Good FPGA for an encryptor
86548: 05/06/29: Re: Good FPGA for an encryptor
86603: 05/06/30: Re: Good FPGA for an encryptor
86604: 05/06/30: Re: Good FPGA for an encryptor
86609: 05/06/30: Re: Good FPGA for an encryptor
86777: 05/07/06: Re: fastest FPGA speed grade?
86788: 05/07/06: Re: fastest FPGA speed grade?
88598: 05/08/23: 10 Gigabit Ethernet FPGA boards...
88653: 05/08/24: Re: Send IP packets at the Ethernet level with VIRTEX4
nick:
72184: 04/08/10: Re: Newbie Xilinx Question: How to keep past designs?
Nick:
14727: 99/02/12: Re: AHDL VS. VHDL
14726: 99/02/12: Re: AHDL & VHDL
14728: 99/02/12: Re: can I trust Altera Simulator?
14779: 99/02/16: Re: Opinions requested : Minc/Synario alternatives
14781: 99/02/16: Re: Xilinx de-compiler
14780: 99/02/16: Re: Xilinx de-compiler
14880: 99/02/22: Re: virtex vs apex ?
15172: 99/03/11: Re: Current State of FPGA-based PCI Interfaces?
18083: 99/09/28: Verilog or VHSIC HDL ?
21349: 00/03/17: Xilinx Foundation 1.5 Question
21350: 00/03/18: Re: Xilinx Problem Found
21364: 00/03/20: Re: Beginner's Guide
21365: 00/03/20: Re: Beginner's Guide
22412: 00/05/08: How do I lock down Macro Routing
27142: 00/11/12: OT but important
27836: 00/12/12: ActelDeskTop Macro fanout problem
37228: 01/12/04: quartus post simulation setup problem
37287: 01/12/06: Re: quartus post simulation setup problem
37292: 01/12/06: Re: quartus post simulation setup problem
37340: 01/12/07: Re: quartus post simulation setup problem
62619: 03/11/03: Defect and Fault Tolerance Material
63221: 03/11/18: %age occupation of interconnect resources
63955: 03/12/10: Manufacturing Tests
64594: 04/01/08: Readbackn on Virtex II Pro devices
65965: 04/02/10: Lattice XPGA
72328: 04/08/15: SDRAM Controller on a cyclone dev kit
72450: 04/08/19: Re: SDRAM Controller on a cyclone dev kit
75320: 04/11/02: FPGA configuration download - How is it done?
76153: 04/11/26: Re: Choice of FPGA device -- my view on benchmarks
76703: 04/12/09: Re: Open source FPGA EDA Tools
77218: 04/12/30: Quartus and Cyclone programming problem
77227: 04/12/31: Re: Quartus and Cyclone programming problem
77256: 05/01/02: Re: Quartus and Cyclone programming problem
77257: 05/01/02: Re: Quartus and Cyclone programming problem
77484: 05/01/07: Re: Quartus and Cyclone programming problem
77624: 05/01/12: Programming and copyright
77638: 05/01/13: Re: Programming and copyright
77677: 05/01/13: Re: Programming and copyright
77678: 05/01/13: Re: Programming and copyright
77718: 05/01/15: Re: Programming and copyright
82150: 05/04/07: Re: Sdram controller on the Altera Cyclone board!
82297: 05/04/10: Re: Neural Networks in FPGA
83686: 05/05/05: Altera SDRam ip core
87268: 05/07/20: FPGA + DIMM SDRAM
88515: 05/08/21: Using very large number in VHDL
88527: 05/08/22: Re: Using very large number in VHDL
88593: 05/08/23: Re: Using very large number in VHDL
92116: 05/11/22: Stupid reset question
92137: 05/11/23: Re: Stupid reset question
92217: 05/11/24: Re: Stupid reset question
111375: 06/11/02: Tsamp for Spartan 3?
128026: 08/01/14: Read/Write SRAM on Spartan3 Starter kit
128123: 08/01/16: Re: Read/Write SRAM on Spartan3 Starter kit
128567: 08/01/31: About 10-bit pixel datum from CMOS image sensor
128572: 08/01/31: Re: About 10-bit pixel datum from CMOS image sensor
128981: 08/02/13: '1' or '0' when I/O pin is pulled up
129021: 08/02/13: Re: '1' or '0' when I/O pin is pulled up
144073: 09/11/10: Analog power supplies to FPGAs
146034: 10/03/04: Re: Modelsim PE vs. Aldec Active-HDL (PE)
Nick Bailey:
9552: 98/03/23: Re: The case for Linux and EDA
Nick Barton:
7349: 97/08/29: Re: LogiBLOX components in VHDL?
7548: 97/09/21: Re: Atmel 17256 serial config EEPROMs
Nick Bruty:
27558: 00/11/28: Re: Spartan II ?
27554: 00/11/28: Re: ACEX1K vs FLEX10K
27555: 00/11/28: Re: Xess - XS40-005XL question
27556: 00/11/28: Re: hard or soft core for FPGA?
27557: 00/11/28: Re: PLL vs DLL
27559: 00/11/28: Xilinx Coolrunner going on last time buy?
Nick Camilleri:
98069: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
Nick Campregher:
56442: 03/06/05: Multipliers - Ram ratio
56454: 03/06/05: Re: Multipliers - Ram ratio
Nick Elliott:
117458: 07/03/31: Altera ASMI_PARALLEL megafunction (EPCS4/CycloneII)
Nick Gent:
1678: 95/08/15: Re: Timespecs in XNF format
1680: 95/08/15: Re: Timespecs in XNF format
1686: 95/08/16: Re: Timespecs in XNF format
4237: 96/10/03: VHDL for Xilinx designs?
7493: 97/09/17: Can 3.3v Xilinx drive CMOS?
7638: 97/09/30: Xilinx 5200 I/O Performance
9631: 98/03/27: Re: "CORE Competency" ???
12610: 98/10/20: GUI GRINDERs vs SLICK SCRIPTOs
Nick Hartl:
9112: 98/02/21: Re: System Gates and Logic Cells...
9113: 98/02/21: Re: XACT6 & ORCAD IV
9111: 98/02/21: Re: Xilinx download cable ??????
9109: 98/02/21: Re: Free FPGA tools???
9110: 98/02/21: Re: Free FPGA tools???
9120: 98/02/21: Re: XACT6 & ORCAD IV
9359: 98/03/07: Re: Leonardo/Xilinx BUFGLS question
9451: 98/03/14: Re: Strange Xilinx question?
9767: 98/04/03: Re: Xilinx routing optimization?
9768: 98/04/03: Re: One time programmables
9779: 98/04/04: Re: VHDL in synopsys -> M1
9843: 98/04/08: Re: Xilinx Foundation Express
9842: 98/04/08: Re: Effects of IC production
9846: 98/04/08: Re: fmap and timespec
9890: 98/04/10: Re: VHDL compiler differences ?
10285: 98/05/09: Re: Xilinx Foundation and Linux
10284: 98/05/09: Re: Help: 25Mhz XC4025E-2 FPGA having hold time errors during simulation
10286: 98/05/09: Re: Xilinx Foundation and Linux
10287: 98/05/09: Re: How to use LogiBlox Components in FPGA Express?
10289: 98/05/09: Re: Low power FPGA design
10288: 98/05/09: Re: Low power FPGA design
10650: 98/06/09: Re: Xilinx Foundation
10652: 98/06/09: Re: Multipliers on FPGA's
10651: 98/06/09: Re: Q: FPGA Place and Route Software
10661: 98/06/09: Re: HELP: Bidirectional I/O's in state machine
10662: 98/06/09: Re: Xilinx XL Pin supply current
10851: 98/06/25: Re: transfert a BINARY file from a PC to a XC3030 (Xilinx)
11005: 98/07/09: Re: Xilinx Foundation Frustartions
11307: 98/08/03: Re: Delay Element for async design.
11308: 98/08/03: Re: Caluclation of gates in FPGA
11641: 98/08/27: Re: CPLD/FPGA software
11663: 98/08/29: Re: [Fwd: FGPA-express : is there a way to use scripts ?]
11742: 98/09/06: Re: lookup table for mult/div
11827: 98/09/11: Re: Xilinx Spartan vs. 4K series (Spartan pins)
11935: 98/09/20: Re: Xilinx ncd files
12375: 98/10/10: Re: Xilinx F1.5/FPGA Express wackiness
12377: 98/10/10: Re: Xilinx may not support schematics for Virtex?????
12383: 98/10/10: Re: Verilog Vs VHDL
12385: 98/10/10: Re: Verilog Vs VHDL
12548: 98/10/15: Re: Schematic entry?
12549: 98/10/15: Re: Xilinx may not support schematics for Virtex?????
12835: 98/10/31: Re: Musical Chairs (Disti troubles)
14963: 99/02/27: Re: Your view on this article?
17408: 99/07/24: Re: How to get Foundation synthesis result(gate level layout)?
Nick Macias:
20250: 00/02/02: Re: Count 1's algorithm...
36897: 01/11/23: Re: Viewing generated VHDL
37126: 01/11/30: WebPack Experience
37619: 01/12/17: Re: Configuring Xilinx FPGA through parallel port
Nick Maclaren:
29284: 01/02/12: Re: double precision floating point arithmetic
46531: 02/09/02: Re: Hardware Code Morphing?
65605: 04/02/03: Re: 4 bit divisor with flip-flop ?
67885: 04/03/22: Re: Dual-stack (Forth) processors
82052: 05/04/06: Re: ISA vs. patent/trademark
82130: 05/04/07: Re: ISA vs. patent/trademark
82163: 05/04/07: Re: ISA vs. patent/trademark
117525: 07/04/03: Re: Implementing a communication protocol for data transfer over TCP on an FPGA
Nick Mckay:
36280: 01/11/05: Re : Xilinx multiplier core - problem
Nick Pomponio:
208: 94/09/21: Re: Software costs (was Re: Lattice ISP software)
340: 94/10/24: Suggestions for low power FPGAs/CPLDs needed
Nick Sawyer:
73464: 04/09/22: Re: Spartan-3 DDR Speed
Nick Schmitz:
856: 95/03/14: <--> Proposed Newsgroup for Programmable Logic Users <--->
1013: 95/04/13: Re: Need "fusemap" information from vendor, likely?
7141: 97/08/05: Synopsys Newbie Q: What happens if Replace_FPGA doesn't work
Nick Steffen:
17829: 99/09/08: Re: QuickLogic FPGAs
Nick Suttora:
43933: 02/06/06: Re: Xilinx JTAG verification failed
64979: 04/01/17: Simulation Speed when using Xilinx DCM
65032: 04/01/19: Re: Simulation Speed when using Xilinx DCM
65330: 04/01/24: Xilinx DDR Register FDDRRSE
nick toop:
5101: 97/01/23: Re: Able to reverse a .JED back to logic?
7177: 97/08/11: Re: Problems with Lattice pDS+
10610: 98/06/05: Re: LATTICE 2032 problems
10672: 98/06/10: Re: How about Lattice ispLSI?
10677: 98/06/10: Re: How about Lattice ispLSI?
13754: 98/12/22: exporting synario schematics?
Nick Tredennick:
891: 95/03/22: Re: FPGA accelerated engines for volume rendering
Nick Weavers:
5731: 97/03/11: Re: Introducing Renoir
Nick Young:
23895: 00/07/14: FPGA Intro
56630: 03/06/10: Learning FPGAs
nick291:
157711: 15/02/10: Re: Dynamic partial reconfiguration on Spartan 3 chips
NickC:
98764: 06/03/16: Re: for all those who believe in ASICs....
98786: 06/03/16: Re: for all those who believe in ASICs....
Nickel:
74316: 04/10/07: Virtex : Routing Prohibit
nickel:
43999: 02/06/07: F3.1i:Timing warning
61796: 03/10/11: FPGA Editor: Macro(Xilinx)
77625: 05/01/12: General Question - Which FPGAs can support partial run-tim reconfiguration?
81371: 05/03/22: Lattic ECP/EC -- Partial Run-time Reconfiguration??
<NickHolby@googlemail.com>:
114373: 07/01/13: Will FPGAs suit my need?
114389: 07/01/14: Re: Will FPGAs suit my need?
114392: 07/01/14: Re: Will FPGAs suit my need?
NickNitro:
120615: 07/06/12: UK shop - FPGA boards + chips.
120654: 07/06/12: Re: UK shop - FPGA boards + chips.
123769: 07/09/04: Multiple CPLDs on a PCB.
123784: 07/09/04: Re: Multiple CPLDs on a PCB.
123790: 07/09/04: Re: Multiple CPLDs on a PCB.
123799: 07/09/04: Re: Multiple CPLDs on a PCB.
123813: 07/09/05: Re: Multiple CPLDs on a PCB.
124534: 07/09/26: Very basic clock questions.
124537: 07/09/26: Re: Very basic clock questions.
124577: 07/09/27: Basic questions about the Nios II.
124579: 07/09/27: Re: Basic questions about the Nios II.
124580: 07/09/27: Re: Basic questions about the Nios II.
124584: 07/09/27: Re: Basic questions about the Nios II.
124586: 07/09/27: Re: Basic questions about the Nios II.
Nicko van Someren:
13035: 98/11/12: Re: DES in VHDL?
Nicky:
66361: 04/02/18: Using 3.3V compliant FPGA for 5V PCI
66398: 04/02/18: Re: Using 3.3V compliant FPGA for 5V PCI
71794: 04/07/30: Active modular implementation of modules created with the generate statement
103621: 06/06/06: Re: how to readback a frame
103884: 06/06/14: Re: how to readback a frame
107377: 06/08/27: ask for help about routing/unrouting problems in jbits2.8,thanks
<nicmo92@yahoo.com>:
136622: 08/11/26: Re: FMC/VITA 57
Nico:
71253: 04/07/13: KCPSM3+vhdl+verilog
71259: 04/07/13: Re: KCPSM3+vhdl+verilog
nico:
81802: 05/04/01: Re: modelsim: Types do not match
Nico Coesel:
1952: 95/09/23: cheap (free) fpga design software
2224: 95/11/05: Wanted motorola fpga mpa1036
7067: 97/07/28: Re: free FPGA software from actel
64975: 04/01/17: Re: Hardware to test (FPGA-based) prototype?
70535: 04/06/19: Re: compressing Xilinx bitstreams
70537: 04/06/19: Re: compressing Xilinx bitstreams
70542: 04/06/19: Re: compressing Xilinx bitstreams
70557: 04/06/20: Re: compressing Xilinx bitstreams
99951: 06/03/31: Re: deglitching a clock
99971: 06/03/31: Re: deglitching a clock
99975: 06/03/31: Re: deglitching a clock
100105: 06/04/03: Re: deglitching a clock
103767: 06/06/10: Re: Xilinx ISE S/W Install kernel version "mismatch"
104810: 06/07/06: Re: DDR Controller problems
104811: 06/07/06: Re: "Large" memory array in VHDL
104889: 06/07/08: Re: Fastest platform to run ISE?
104909: 06/07/09: Re: Weird JTAG lockup issue, where is the BUG?
105094: 06/07/13: Re: Development Boards -Your chance to suggest features
105170: 06/07/16: Re: An idea for a product (FPGA/ASIC based)
105243: 06/07/18: Re: Opencore ddr_controller
105407: 06/07/21: Re: Last Chance for Tarfessock1 Features
105422: 06/07/22: Re: HW Debug tools
105432: 06/07/22: Re: Why 8 clock trees in Xilinx Spartan-3 device?
105582: 06/07/26: Re: Spartan 3 clock to output tristate timing
106023: 06/08/05: Re: verilog versus vhdl
106035: 06/08/06: Re: verilog versus vhdl
106086: 06/08/07: Re: FPGA : PCI-Xilinx Core, PC not booting
106245: 06/08/09: Re: Unpicking Logical Synthesis
106430: 06/08/13: Re: Maximum Current Draw of FPGA
106438: 06/08/13: Re: Maximum Current Draw of FPGA
106443: 06/08/13: Re: Maximum Current Draw of FPGA
106565: 06/08/15: Re: Maximum Current Draw of FPGA
106570: 06/08/15: Re: IIR filter example ?
106605: 06/08/16: Re: Maximum Current Draw of FPGA
106648: 06/08/16: Re: Open-source JTAG software?
106761: 06/08/18: Re: FFT on an FPGA
106762: 06/08/18: Re: Problems about the synthesis(XST)
106787: 06/08/19: Re: FFT on an FPGA
106789: 06/08/19: Re: FFT on an FPGA
106832: 06/08/20: Re: CPU design
107098: 06/08/24: Re: DDR controller on Spartan-3e 500
107292: 06/08/26: Re: FPGA -> SATA?
107455: 06/08/28: Re: FPGA -> SATA?
107521: 06/08/29: Re: Undergrad project-8051 specifications??
107720: 06/08/31: Re: Bypass Caps : XAPP623 vs Spartan-3 Starter Kit Board
107875: 06/09/01: Re: Interface of 8051 microcontroller with FPGA Block RAM
108033: 06/09/04: Re: Clock Domain Crossing in Virtex4
108127: 06/09/05: Re: FPGA multiplier
108208: 06/09/06: Re: NON-CLK pins failed to route using a CLK template
108292: 06/09/07: Re: Xilinx LogiCORE PCI32
108310: 06/09/07: Re: ddr with multiple users
108311: 06/09/07: Re: Synchronous Clocks
108368: 06/09/09: Re: Virtex4FX12 and Spartan3 lead time
108658: 06/09/14: Spartan3: Multiplier Madness
108661: 06/09/14: Re: Spartan3: Multiplier Madness
108787: 06/09/16: Re: Spartan3: Multiplier Madness
108819: 06/09/17: Re: What resources do the Xilinx tools require on a PC?`
108857: 06/09/18: Re: Spartan3: Multiplier Madness
108869: 06/09/18: Re: Spartan3: Multiplier Madness
108956: 06/09/19: Re: Using a global clock as a flip-flop enable?
108958: 06/09/19: Re: Spartan3: Multiplier Madness
108972: 06/09/19: Re: ddr clock issues
109077: 06/09/20: Re: ddr clock issues
109079: 06/09/20: Re: ddr clock issues
109160: 06/09/21: Re: ddr clock issues
109169: 06/09/21: Re: Are you ready for Virtex-5? We are...
109263: 06/09/22: Re: Dell Laptop for Embedded Work
109418: 06/09/26: Re: Migration from Spartan-2E to Spartan-3E
109498: 06/09/27: Re: Help required regarding PCI Master core
109606: 06/09/30: Re: DDR RAM
109798: 06/10/05: Re: nicer code => slower code??
109924: 06/10/08: Re: Spartan3A - internal flash configuration or not?
110686: 06/10/19: Re: Meeting Timing Constraint
110865: 06/10/24: Re: Survey on Quartus SOPC/Nios-II
110902: 06/10/25: Re: Simple multiply in Xilinx?
111267: 06/10/31: Re: Question about bandwidth of scope?
111477: 06/11/03: Re: Scientific Computing on FPGA
111496: 06/11/03: Re: Scientific Computing on FPGA
112807: 06/11/29: Re: Bus structures question (Spartan 3)
113000: 06/12/04: Re: Picoblaze C compiler 1.8.4
113254: 06/12/09: Re: RTL Hardware design issue: Count Leading Zeros CLZ
113266: 06/12/09: Re: 50 MSPS ADC with Spartan 3 FPGA - clock issues
113753: 06/12/20: Re: ANN: PicoBlaze C: compile to bitstream!
113768: 06/12/20: Re: ANN: PicoBlaze C: compile to bitstream!
113858: 06/12/26: Re: better ways for debugging?
113918: 06/12/29: Re: ChipScope - impact on design or not?
113925: 06/12/29: Re: ChipScope - impact on design or not?
113939: 06/12/29: Re: ChipScope - impact on design or not?
113971: 06/12/31: Re: Memory controller design
114120: 07/01/04: Re: DC timing violation, what to do first?
114146: 07/01/05: Re: Spartan3E minimum clock-to-output (hold time)
114171: 07/01/06: Re: Spartan3E minimum clock-to-output (hold time)
114391: 07/01/14: Re: Will FPGAs suit my need?
114398: 07/01/14: Re: Will FPGAs suit my need?
114663: 07/01/22: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114730: 07/01/23: Re: FPGA damage from bad bitstream
114970: 07/01/28: Re: Minimal design for xilinx?
115010: 07/01/29: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
115123: 07/01/31: Re: DDR FPGA Design
115136: 07/01/31: Re: DDR FPGA Design
115137: 07/01/31: Re: DDR FPGA Design
115301: 07/02/06: Re: DDR FPGA Design
115486: 07/02/12: Re: Picobalze in the FPGA
115600: 07/02/14: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115731: 07/02/18: Re: Do you like Virtex-5 ?
115964: 07/02/26: Re: Spartan-3AN
116003: 07/02/27: Re: XC3S400 and XC3S500E in PQ208
116005: 07/02/27: Re: Spartan-3AN
116430: 07/03/08: Xilinx Spartan DCM jitter spectrum
116757: 07/03/16: Re: Xilinx Synthesis Attribute usage
116769: 07/03/17: Re: Xilinx Synthesis Attribute usage
116993: 07/03/21: Re: Why is Xilinx's WebPACK so inferior?
117588: 07/04/04: Re: Looking for Memory Recommendation for Spartan 3E 1200
117602: 07/04/04: Re: Interfacing the DAC0808 to FPGA
117636: 07/04/05: Re: Looking for Memory Recommendation for Spartan 3E 1200
117637: 07/04/05: Re: Implement IIR Filter on FPGA
117679: 07/04/06: Re: PCI FPGA Dev Board Suggestions
117694: 07/04/07: Re: PCI FPGA Dev Board Suggestions
117698: 07/04/07: Re: Transition from ASIC to FPGA
117717: 07/04/08: Re: A new way to define systems of systems?
117955: 07/04/14: Re: picoblaze C compiler download wanted
118446: 07/04/26: Re: Sscanf replacement for xilinx EDK
118480: 07/04/27: Re: Problem cascading 2 DCMs
118515: 07/04/28: Re: Placement error for adjacent pins
118560: 07/04/30: Re: driving Spartan-3 input from 74LS TTL
119462: 07/05/20: Re: Single Chip MSX computer full schematic and VHDL sources
119570: 07/05/22: Re: System-synchronous interface clocking between FPGA's
119987: 07/05/30: Re: FIR Filter ON FPGA
119988: 07/05/30: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
120048: 07/05/31: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
120137: 07/06/01: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
120566: 07/06/10: Re: Affordable pcie card ?
120645: 07/06/12: Re: XIlinx tools question - how to quickly identify unconstrained paths
120751: 07/06/15: Re: help on clock fowarding between 2 FPGAs
121089: 07/06/25: Re: How to choose FPGA for a huge computation?
121526: 07/07/06: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121601: 07/07/09: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121683: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121741: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121881: 07/07/14: Re: Which embedded O/S for a 32-bit RISC microcontroller?
121911: 07/07/15: Re: ESR Meter - design contest
121912: 07/07/15: Re: ESR Meter - design contest
122068: 07/07/18: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122116: 07/07/19: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122280: 07/07/25: Re: Altera or Xilinx
122863: 07/08/08: Re: New Xilinx forum.
122952: 07/08/12: Re: DDR/DDR2 controller - core
122960: 07/08/12: Re: DDR/DDR2 controller - core
123068: 07/08/15: Re: Xilinx DDR2 SDRAM controller performance
123181: 07/08/18: Re: DDR controller - best device to perform
123184: 07/08/19: Re: DDR controller - best device to perform
123196: 07/08/19: Re: DDR controller - best device to perform
123288: 07/08/22: Re: Power Reduction Strategy
123522: 07/08/29: Re: memory in spartan 3 fpga
124066: 07/09/11: Good VHDL reference?
124231: 07/09/15: Re: Beginner Advice (Languages, tools etc.)
124524: 07/09/25: Re: Never buy Altera!!!!
124556: 07/09/26: Re: Never buy Altera!!!!
124655: 07/09/29: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124656: 07/09/29: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124675: 07/09/29: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124961: 07/10/12: Re: Graphical VHDL Viewer ?
125760: 07/11/03: Re: How do I meet this memory IO with least resources on FPGA?
125990: 07/11/11: Re: newbie to 16v8
126211: 07/11/16: Re: FPGA for hobby use
126473: 07/11/23: Re: VHDL language is out of date! Why? I will explain.
126504: 07/11/25: Re: VHDL language is out of date! Why? I will explain.
126621: 07/11/28: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126744: 07/11/30: Re: Hand solder that FPGA on your prototype
126855: 07/12/04: Re: calculation of clock cycle /instructions...
127009: 07/12/08: Re: Which FPGA and memory to use? The eternal X vs. A question.
127016: 07/12/08: Re: Which FPGA and memory to use? The eternal X vs. A question.
127017: 07/12/08: Re: Which FPGA and memory to use? The eternal X vs. A question.
127032: 07/12/09: Re: Which FPGA and memory to use? The eternal X vs. A question.
127149: 07/12/12: Re: Debugging designs that are running on FPGA
127167: 07/12/13: Re: spartan 3e VQ100 serious question
127430: 07/12/24: Re: DQS contention with ddr_sdr from Opencores
127437: 07/12/25: Re: FPGA Project Support
127454: 07/12/26: Re: Spartan 3 FPGA verification via readback
127489: 07/12/28: Re: TechXclusives from Xilinx
127551: 08/01/02: Re: Split Plane
127552: 08/01/02: Re: Where are the LCD or OLED bitmapped displays?
127553: 08/01/02: Re: Where are the LCD or OLED bitmapped displays?
127622: 08/01/04: Re: Ethernet on recent FPGAs
127659: 08/01/04: Re: Ethernet on recent FPGAs
127660: 08/01/04: Re: Where are the LCD or OLED bitmapped displays?
127671: 08/01/05: Re: Ethernet on recent FPGAs
127692: 08/01/05: Re: Ethernet on recent FPGAs
127731: 08/01/06: Re: Spartan 3E Sarter Kit Ethernet
127737: 08/01/07: Re: Ethernet on recent FPGAs
127870: 08/01/09: Re: Spartan3 vs cyclone
127922: 08/01/10: Re: Multiple UCF support in Xilinx ISE
128227: 08/01/18: Re: Where has Xilnet gone?
128618: 08/01/31: Re: FPGA in Telecommunications
129317: 08/02/20: Re: MIG and Spartan3 for a 112 bit DQ bus (7chips x16)
129401: 08/02/22: Re: Interview questions
129423: 08/02/23: Re: Interview questions
129555: 08/02/27: Re: Picoblaze enhencement and assembler
129599: 08/02/28: Re: Picoblaze enhencement and assembler
129655: 08/03/02: Re: Software for FPGA-based PC scope
129665: 08/03/02: Re: Software for FPGA-based PC scope
129718: 08/03/03: Re: my Spartan-4 wishlist
129784: 08/03/05: Re: my Spartan-4 wishlist
129806: 08/03/05: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129957: 08/03/11: Re: BRAM synthesis question
130078: 08/03/14: Re: DDR3 speed, Altera vs Xilinx
130115: 08/03/15: Re: DDR3 speed, Altera vs Xilinx
130116: 08/03/15: Re: DDR3 speed, Altera vs Xilinx
130337: 08/03/20: Re: DDR SDRAM interface for Virtex II Pro and Spartan3a
130502: 08/03/25: Re: dual clock fifo
130580: 08/03/27: Re: VHDL document generation utilities
130617: 08/03/28: Re: VHDL document generation utilities
130618: 08/03/28: Re: Places to visit in Amsterdam and Brussells
130794: 08/04/01: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
130908: 08/04/04: Re: Xilinx FPGA + SMPS
130909: 08/04/04: Re: Conterfeit parts guidance
130983: 08/04/07: Re: Spartan3 JTAG flash In System Programming over Ethernet
131304: 08/04/18: Re: Simulation tools for Xilinx ISE
131319: 08/04/18: Re: Survey: FPGA PCB layout
131326: 08/04/19: Re: Survey: FPGA PCB layout
131339: 08/04/20: Re: Survey: FPGA PCB layout
131855: 08/05/04: Re: Using SRL16 with reset
132698: 08/06/05: Re: Xilinx vs Altera
132784: 08/06/06: Re: Xilinx vs Altera
132823: 08/06/07: Re: HDL tricks for better timing closure in FPGAs
132865: 08/06/09: Re: SDRAM controller
133350: 08/06/25: Re: FPGA based database searching
133585: 08/07/04: Re: Single ended interface at 70Mhz for FPGAs
133902: 08/07/18: Re: Xilinx/Altera gate equivalence
133953: 08/07/20: Re: Change clock domain for FIFO ...
134168: 08/07/28: Re: Creating new operators
134357: 08/08/07: Re: RTL Schematic as EDIF
134576: 08/08/19: Re: More work, less posts
134851: 08/09/03: Strange Spartan2 behaviour
134877: 08/09/04: Re: Strange Spartan2 behaviour
134878: 08/09/04: Re: Strange Spartan2 behaviour
134881: 08/09/04: Re: Strange Spartan2 behaviour
134963: 08/09/08: Re: Strange Spartan2 behaviour
135021: 08/09/10: Re: Can Soft microprocessor replace DSP's
135143: 08/09/17: Re: Xilinx build system
135208: 08/09/20: Re: Is it hard to detect an ucf sytax error?
135347: 08/09/27: Re: maximum clock rating
135363: 08/09/28: Re: Clocking Sync Burst SRAM
135377: 08/09/29: Re: Sending UDP packets over Ethernet
135378: 08/09/29: Re: Sending UDP packets over Ethernet
135379: 08/09/29: Re: Clocking Sync Burst SRAM
135868: 08/10/19: Re: Entry Level FPGA Jobs and Outsourcing
135874: 08/10/19: Re: Field update
136114: 08/11/02: Re: classic Spartan-3 DDR2 and IOBs
136171: 08/11/04: Re: Tiny JTAG connector
136923: 08/12/14: Re: Doubt about the maximum speed of FPGA clock nets
136991: 08/12/17: Re: Gigabit Ethernet PHY without NDA?
137045: 08/12/20: Re: Large BRAM synthesis
137148: 08/12/28: Re: FPGA > ASIC
137442: 09/01/16: Re: Death of the RLOC?
137792: 09/01/29: Re: What software do you use for PCB with FPGA ?
137793: 09/01/29: Re: What software do you use for PCB with FPGA ?
137794: 09/01/29: Re: What software do you use for PCB with FPGA ?
137800: 09/01/29: Re: What software do you use for PCB with FPGA ?
137804: 09/01/29: Re: What software do you use for PCB with FPGA ?
137856: 09/02/01: Re: Heavily pipelined design
138176: 09/02/08: Re: Is this phase accumulator trick well-known???
138240: 09/02/10: Re: Is this phase accumulator trick well-known???
138361: 09/02/17: Re: DDR3 with Spartan-3
138366: 09/02/17: Re: DDR3 with Spartan-3
138683: 09/03/04: Re: writing current date to a register
138933: 09/03/15: Re: Virtex 5 LVDS
138938: 09/03/15: Re: Virtex 5 LVDS
138954: 09/03/16: Re: SPI controller for FPGA
139266: 09/03/24: Re: Xilinx XAPP052 LFSR and its understanding
139338: 09/03/26: Re: added jitter on FPGAs
139499: 09/04/01: Re: DCM vs PLL
139562: 09/04/03: Re: Maximum frequency
139813: 09/04/14: Re: Mobile low power DDR SDRAM and MIG
139852: 09/04/16: Re: Synchronous clocking between Cyclone III and SDRAM
139866: 09/04/17: Re: Synchronous clocking between Cyclone III and SDRAM
139902: 09/04/18: Re: Synchronous clocking between Cyclone III and SDRAM
139927: 09/04/19: Re: Atari VCS 2600 FPGA Cartridge
140440: 09/05/13: Re: connecting FPGA with PC using ethernet MAC layer only
141031: 09/06/02: Re: Open Source FPGA circuit design.
141106: 09/06/05: Re: digital RGB Video to Analog VGA triple DAC question
141122: 09/06/07: Re: digital RGB Video to Analog VGA triple DAC question
141534: 09/06/26: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
141632: 09/07/01: Re: pinout
141727: 09/07/05: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
142094: 09/07/24: Re: Spartan 3 and DDR2
142113: 09/07/25: Re: Spartan 3 and DDR2
142133: 09/07/26: Re: Spartan 3 and DDR2
142227: 09/07/29: Re: cool chart
142278: 09/08/01: Single ended LVDS into FPGA
142282: 09/08/01: Re: Single ended LVDS into FPGA
142287: 09/08/02: Re: Xilinx 3E design programs fine with 500E but fails with 250E
142295: 09/08/02: Re: Xilinx 3E design programs fine with 500E but fails with 250E
142392: 09/08/08: Re: Peter Alfke
142402: 09/08/09: Re: Spartan-6 Boards - Your Wish List
142403: 09/08/09: Re: Peter Alfke
142441: 09/08/11: Re: Spartan-6 Boards - Your Wish List
142477: 09/08/12: Re: Spartan-6 Boards - Your Wish List
142501: 09/08/13: Re: Spartan-6 Boards - Your Wish List
142524: 09/08/14: Re: Spartan-6 Boards - Your Wish List
142533: 09/08/16: Re: Soft Processor IP core report
142540: 09/08/16: Re: Soft Processor IP core report
142546: 09/08/16: Re: Soft Processor IP core report
142551: 09/08/16: Re: Soft Processor IP core report
142649: 09/08/24: Re: Yet Another Graphics Controller
142650: 09/08/24: Re: Yet Another Graphics Controller
142659: 09/08/24: Re: Yet Another Graphics Controller
142704: 09/08/27: Re: Reading from ADC and writing to DAC at same time
142707: 09/08/27: Re: Reading from ADC and writing to DAC at same time
142721: 09/08/28: Re: Reading from ADC and writing to DAC at same time
142756: 09/08/30: Re: program spartan3 under linux
142873: 09/09/04: Re: Choice of Language for FPGA programming
142874: 09/09/04: Re: Choice of Language for FPGA programming
142888: 09/09/05: Re: Choice of Language for FPGA programming
142896: 09/09/06: Re: Choice of Language for FPGA programming
142906: 09/09/07: Re: Choice of Language for FPGA programming
143034: 09/09/15: Re: 8 phase clock output
143041: 09/09/16: Re: 8 phase clock output
143145: 09/09/23: Re: USB programmable Open Source Hardware
143224: 09/09/27: Re: USB programmable Open Source Hardware
143227: 09/09/27: Re: USB programmable Open Source Hardware
143275: 09/09/29: Re: USB programmable Open Source Hardware
143284: 09/09/29: Re: USB programmable Open Source Hardware
143294: 09/09/30: Re: USB programmable Open Source Hardware
143339: 09/10/03: Re: Implement ARM cores on a FPGA chip?
143343: 09/10/03: Re: Implement ARM cores on a FPGA chip?
143345: 09/10/04: Re: Up-counter with async load/clear and overflow detection (Verilog)
143410: 09/10/10: Re: Implement ARM cores on a FPGA chip?
143434: 09/10/11: Re: Getting started...
143465: 09/10/12: Re: FPGA ruined (?)
143715: 09/10/22: Re: Time stability of clock on FPGA board
143743: 09/10/23: Re: Time stability of clock on FPGA board
143744: 09/10/23: Re: Time stability of clock on FPGA board
143755: 09/10/23: Re: CPLD/FPGA with Linux
143901: 09/11/02: Re: 50+ pages fresh from Antti's brain
143926: 09/11/03: Re: 50+ pages fresh from Antti's brain
143947: 09/11/04: Re: 50+ pages fresh from Antti's brain
143953: 09/11/04: Re: Cyclone IV announced
143981: 09/11/05: Re: Does anyone ever use placement?
144022: 09/11/07: Re: OK Xilinx users, it's time I was let in on the joke...
144482: 09/12/09: Re: A new approach to FPGA and PCB System Development Platform, Santa Clara, CA, USA (By Altium)
144575: 09/12/15: Re: Best clock output pin in Spartan-3
144646: 09/12/21: Re: Please help, Xilinx FIFO problem!
144654: 09/12/21: Re: Please help, Xilinx FIFO problem!
144671: 09/12/22: Re: H.264 on Spartan3A DSP
144680: 09/12/22: Re: Please help, Xilinx FIFO problem!
144719: 09/12/28: Re: Info on heritage Nallatech board?
144741: 09/12/30: Re: How to protect my Virtex5 design without battery?
144876: 10/01/11: Re: E1 clock problem with Spartan3e...
144893: 10/01/12: Re: E1 clock problem with Spartan3e...
144911: 10/01/14: Re: Virtex-5 with DDR3 running @ 50Mhz
145355: 10/02/06: Re: using an FPGA to emulate a vintage computer
145534: 10/02/13: Re: VHDL vs Verilog
145562: 10/02/14: Re: VHDL vs Verilog
146173: 10/03/07: Re: Spartan 3 minimum clock pulse width
146284: 10/03/10: Re: Spartan3AN DDR2 - bad writing zeros
146312: 10/03/11: Re: Tier Logic introduces the world's first 3D FPGA
146455: 10/03/18: Re: Xilinx Spartan6 Virtex6 Rollout
146456: 10/03/18: Re: Xilinx Spartan6 Virtex6 Rollout
146497: 10/03/20: Re: Xilinx only on Avnet now
146607: 10/03/23: Re: Why hardware designers should switch to Eclipse
146609: 10/03/23: Re: Why hardware designers should switch to Eclipse
146626: 10/03/24: Re: Why hardware designers should switch to Eclipse
146636: 10/03/24: Re: Why hardware designers should switch to Eclipse
146659: 10/03/25: Re: Why hardware designers should switch to Eclipse
146675: 10/03/25: Re: EMC discussion
146714: 10/03/26: Re: result on hyperterminal is not displayed
146744: 10/03/27: Re: Multipliers in CoolRunner Series?
146957: 10/04/04: Re: Is there a way to implement division by variables other than 2 in single clock with XST ?
147027: 10/04/09: Re: I'd rather switch than fight!
147489: 10/04/28: Re: xilinx arm finally announced
147490: 10/04/28: Re: xilinx arm finally announced
147514: 10/04/29: Re: xilinx arm finally announced
147519: 10/04/29: Re: xilinx arm finally announced
147526: 10/04/30: Re: xilinx arm finally announced
147533: 10/04/30: Re: Spartan6 and 4GB RAM
147561: 10/05/03: Re: PCI Interrupt
147719: 10/05/19: Re: Xilinx Synthesis Tool generates clock signals from combinatorial logic
147758: 10/05/22: Re: Debugging SDRAM interfaces
147765: 10/05/23: Re: Debugging SDRAM interfaces
147814: 10/05/25: Re: Xilinx Xact software for XC2018 Logic Cell Array
147883: 10/05/29: Re: Anyone else need bigger parts in small (low pin count) packages
147906: 10/06/01: Re: Anyone else need bigger parts in small (low pin count) packages
147941: 10/06/03: Re: Job experience? How?
148154: 10/06/23: Re: altshift_taps for Xilinx?
148185: 10/06/25: Re: fooling the compiler
148263: 10/07/02: Re: DMA operation to 64-bits PC platform
148271: 10/07/03: Re: fooling the compiler
148608: 10/08/05: Re: Vendor Tool Stability
148727: 10/08/18: Re: CE compliance testing
148729: 10/08/18: Re: FPGA PCI BOARD .. Few Questions
148760: 10/08/19: Re: CE compliance testing
148776: 10/08/20: Re: CE compliance testing
148904: 10/09/09: Re: Question about OC PCI Cores
148925: 10/09/10: Re: Question about OC PCI Cores
148944: 10/09/14: Re: Question about OC PCI Cores
148946: 10/09/14: Re: Question about OC PCI Cores
148948: 10/09/14: Re: Question about OC PCI Cores
148983: 10/09/18: Re: New release of HDLmaker
149061: 10/09/27: Re: FPGA For Image Processing[Economical]
149085: 10/09/29: Re: SDRAM for specific use - performance and timing questions
149086: 10/09/29: Re: SDRAM for specific use - performance and timing questions
149117: 10/10/02: Re: FPGA design not working!
149190: 10/10/06: Re: Driving a design via TCP/IP
149362: 10/10/18: Re: Combined Microprocessor and FPGA
149491: 10/10/29: Re: FPGA and ethernet phy problem
149498: 10/10/30: Re: FPGA and ethernet phy problem
149736: 10/11/21: Re: Spartan3 device with long availability
149882: 10/11/30: Re: PCI Architecture Question for Data Acquisition Board
149932: 10/12/02: Re: SPI master controller with no embedded microprocessor
150027: 10/12/06: Re: Linux on Microblaze
150049: 10/12/07: Re: Linux on Microblaze
150083: 10/12/10: Re: LPDDR on spartan-3e
150088: 10/12/10: Re: LPDDR on spartan-3e
150093: 10/12/12: Re: LPDDR on spartan-3e
150237: 11/01/04: Re: Transfer data from one clock domain to another clock created by the same PLL/DCM
150274: 11/01/07: Re: OT: Fast Circuits
150292: 11/01/08: Re: Transfer data from one clock domain to another clock created by the same PLL/DCM
150310: 11/01/09: Re: OT: Fast Circuits
150375: 11/01/13: Re: FPGA to PHY/MAC chip
150379: 11/01/13: Re: FPGA to PHY/MAC chip
150397: 11/01/16: Re: Location constraints questions
150402: 11/01/16: Re: Location constraints questions
150464: 11/01/23: Re: Xilinx news
150524: 11/01/25: Re: FPGA changes behaviour when the resource's usage percentage changes
150564: 11/01/26: Re: FPGA changes behaviour when the resource's usage percentage changes
150584: 11/01/27: Re: FPGA changes behaviour when the resource's usage percentage changes
150590: 11/01/27: Re: FPGA changes behaviour when the resource's usage percentage changes
150599: 11/01/27: Re: Interfacing with a 5v micro controller
150689: 11/02/03: Re: Trivia: Where are you on the HDL Map?
150702: 11/02/04: Re: Trivia: Where are you on the HDL Map?
150712: 11/02/05: Re: Dynamic Voltage switching for FPGA IO
150762: 11/02/09: Re: Designing in Altium
150864: 11/02/17: Re: PLD suggestions for classroom use
151275: 11/03/19: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
151384: 11/03/31: MIPI CSI-2 camera interface to parallel
151406: 11/04/03: Re: MIPI CSI-2 camera interface to parallel
151411: 11/04/04: Re: MIPI CSI-2 camera interface to parallel
151443: 11/04/08: Re: Do people do this by hand?
151544: 11/04/18: Re: Oscilloscope recommendations Ghz range?
151604: 11/04/25: Re: Lattice Breakout Boards
151614: 11/04/26: Re: advice needed for FPGA chip selection
151626: 11/04/27: Re: advice needed for FPGA chip selection
151656: 11/05/03: Re: XC3SD3400A Coprocessor Module
151659: 11/05/03: Re: help with a power pc processor based software
151676: 11/05/04: Re: Raggedstone3 - Altera PCIe Development Board
151688: 11/05/05: Re: Raggedstone3 - Altera PCIe Development Board
151730: 11/05/11: Re: Why feedback clock in SDRAM controllers?
151760: 11/05/15: Re: Best syntheses
151870: 11/05/26: Re: PCI Express Cable
152153: 11/07/14: Re: Looking for a FPGA board
152216: 11/07/22: Re: source synchronous DDR bus with non-continuous clock
152235: 11/07/25: Re: synthesizing
152264: 11/07/29: Re: Bitstream compression
152333: 11/08/10: Re: LUT glitches (was Re: ISE bug?)
152369: 11/08/12: Re: Help needed to emulate a microcontroller.
152422: 11/08/21: Re: VHDL Basic Question
152510: 11/08/29: Re: A free lunch
152572: 11/09/15: Re: Xilinx Tin Whiskers ?
152580: 11/09/15: Re: Xilinx Tin Whiskers ?
152615: 11/09/18: Re: Xilinx Tin Whiskers ?
152629: 11/09/19: Re: Xilinx Tin Whiskers ?
152723: 11/10/10: Re: high speed place and route about xilinx
152743: 11/10/16: Re: Doulos training courses at Xilinx
152748: 11/10/18: Re: Doulos training courses at Xilinx
152759: 11/10/19: Re: Altera FPGA weirdness
152769: 11/10/20: Re: Peter Alfke has passed away
152771: 11/10/20: Re: Peter Alfke has passed away
152780: 11/10/21: Re: FPGA development
152789: 11/10/23: Re: FPGA development
152892: 11/10/30: Re: Altera FPGA weirdness
152921: 11/11/01: Re: Altera FPGA weirdness
152931: 11/11/01: Re: Altera FPGA weirdness
153007: 11/11/10: Re: ASIC design job vs FPGA design job
153016: 11/11/14: Re: Enterpoint New Boards
153036: 11/11/19: Re: Production Programming of Flash for FPGAs and MCUs
153062: 11/11/24: Re: Production Programming of Flash for FPGAs and MCUs
153072: 11/11/25: Re: XC7V2000T, the perfect Thanksgiving gift
153221: 12/01/11: Re: Xilinx SRAM clock-to-out and input constraint with forwarded clock
153230: 12/01/13: Re: balancing IIR filter (after adding extra registers)
153315: 12/01/30: Re: Design Notation VHDL or Verilog?
153343: 12/02/03: Re: Design Notation VHDL or Verilog?
153345: 12/02/03: Re: Design Notation VHDL or Verilog?
153366: 12/02/07: Re: Design Notation VHDL or Verilog?
153368: 12/02/09: Re: Design Notation VHDL or Verilog?
153374: 12/02/10: Re: Dangling all pins, DIA0 through DIA31
153379: 12/02/12: Re: Design Notation VHDL or Verilog?
153456: 12/03/02: Migrating Spartan2 design (xnf)
153463: 12/03/02: Re: Migrating Spartan2 design (xnf)
153542: 12/03/27: Re: FPGA + Mess o' RAM
153551: 12/03/27: Re: FPGA communication with a PC (Windows)
153552: 12/03/27: Re: FPGA communication with a PC (Windows)
153560: 12/03/27: Re: FPGA communication with a PC (Windows)
153577: 12/03/30: Re: Spartan 3A counter speed ?
153646: 12/04/09: Re: Best FPGA for algorithmic acceleration
153648: 12/04/10: Re: Best FPGA for algorithmic acceleration
153718: 12/04/30: Re: Smallest GPL UART
153722: 12/04/30: Re: Smallest GPL UART
153812: 12/05/24: Re: Logic Glitches in Spartan-3?
153924: 12/06/30: Re: Replacement for XC4005E
153925: 12/06/30: Re: Replacement for XC4005E
154105: 12/08/08: Re: spartan 6 ddr2 pinout
154146: 12/08/21: Re: recruit FPGA design engineer in Scotland
154157: 12/08/22: Re: recruit FPGA design engineer in Scotland
154291: 12/09/24: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
154316: 12/09/26: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
154320: 12/09/27: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
154323: 12/09/28: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
154755: 13/01/04: Re: Chisel as alternative HDL
154769: 13/01/05: Re: Chisel as alternative HDL
Nico Fleurinck:
48953: 02/10/28: power on of the XC2V2000 xilinx FPGA
Nico L.:
17047: 99/06/28: .shp, .shx, .dbf file conversion. help !
Nico Toender:
47949: 02/10/08: Cosimulation of VHDL and Verilog Files in ISE?
Nicolas Bier:
17713: 99/08/26: Re: input offset constraint to Xilinx IOB's
17830: 99/09/08: Re: synthesis comparion between Synplify and FPGA express
Nicolas Matringe:
10525: 98/05/27: Altera 10k pin function ??
10523: 98/05/27: Altera 10k pin function ??
10526: 98/05/27: Altera 10k pin function ??
10524: 98/05/27: Altera 10k pin function ??
10529: 98/05/27: Sorry (was:Altera 10k pin function ??)
11190: 98/07/24: Re: Dataio Chipwriter won't burn Altera EPC1 generated with Maxplus2 8.2 or greater???
11493: 98/08/19: Altera FLEX10K ClockLock/ClockBoost ?
11494: 98/08/19: Re: Altera FLEX10K ClockLock/ClockBoost ?
11501: 98/08/19: Re: Example Code
11562: 98/08/24: Re: Altera FLEX10K ClockLock/ClockBoost ?
11759: 98/09/08: DataIO + EPC1 problem
11795: 98/09/10: Re: DataIO + EPC1 problem
11912: 98/09/18: Re: Synthesis warning
15335: 99/03/19: Re: Xilinx Vhdl "'event" synthesis problem
15413: 99/03/23: Re: HDL-307 error
15433: 99/03/24: Re: HDL-307 error
15916: 99/04/21: Re: FPGA for PC Cards
16693: 99/06/03: Altera EPC1 PROM + Data IO ChipWriter
17437: 99/07/28: Problem with Max+PlusII / Flex10k
17444: 99/07/28: Re: Problem with Max+PlusII / Flex10k
18154: 99/10/04: Re: APEX device
18357: 99/10/18: Best FPGA for PCI ?
18474: 99/10/26: Re: generating power on initialisation
18540: 99/10/29: Re: Altera - how to make probe to a routed chip ?
18780: 99/11/15: Re: Altera programming leads
18829: 99/11/18: Re: How to use GSR-net in Virtex?
19129: 99/12/01: Timing constraint not met
19132: 99/12/01: Re: Timing constraint not met
19154: 99/12/02: Virtex and JTAG configuration
19171: 99/12/03: Re: Virtex and JTAG configuration
19288: 99/12/10: Xilinx COREgen memory initialization files
19314: 99/12/13: Virtex hard macro
19346: 99/12/15: Re: memory init file format for Foundation simulator ?
19368: 99/12/16: Re: Virtex Configuration Trouble
19529: 99/12/29: Re: Virtex Config Help
19725: 00/01/10: Re: Xilinx Spartan2
19753: 00/01/11: Altera Flex10K bitstream compatibility ?
19815: 00/01/13: Re: Reliability of programming SRAM FPGAs
20100: 00/01/27: Re: microcontroller in vhdl
20271: 00/02/03: Spartan 2 & Foundation
20360: 00/02/07: Floating license & Foundation Express
20362: 00/02/07: Re: Floating license & Foundation Express : Ooops
20428: 00/02/10: Spartan/Foundation Latch reset problem
20575: 00/02/15: Re: clock
20820: 00/02/23: Re: Installing Xilinx Foundation on PC
20866: 00/02/24: Xilinx PCI pinout ?
20883: 00/02/25: Re: Xilinx PCI pinout ?
20887: 00/02/25: Re: Xilinx PCI pinout ?
21366: 00/03/20: Clock disabling
21395: 00/03/21: Re: Clock nets using non-dedicated resources
21413: 00/03/22: Re: Foundation 2.1: Prevent Optimizing away of open Signals/Pins ?
21993: 00/04/11: Re: LUT
22285: 00/05/04: Re: Init/ line - CRC error ???
22290: 00/05/04: Re: Init/ line - CRC error ???
22454: 00/05/09: Looking for Altera programmer in France
22537: 00/05/11: Re: FPGA emulators?
23140: 00/06/15: Re: CoreGenerator and VHDL
23248: 00/06/19: Re: Problem copying text from the Spartan II data sheet
23362: 00/06/23: Re: What tools do people use for Xilinx FPGAs?
23371: 00/06/23: Re: What tools do people use for Xilinx FPGAs?
23641: 00/07/04: Re: Altera Ships Largest PLD
24031: 00/07/24: Re: Xilinx Core Generators.
24135: 00/07/27: Re: Implementation
24230: 00/07/31: Re: Free-running Oscillator.
24252: 00/08/01: Desperatly needing a SpartanII
24270: 00/08/02: Re: Desperatly needing a SpartanII
24276: 00/08/02: Re: Desperatly needing a SpartanII
24315: 00/08/03: Re: 8251A USART
24341: 00/08/04: Re: XST?
24411: 00/08/07: Re: Xilinx Foundation 3.1i
24514: 00/08/11: Virtex CLKDLL and Leonardo
25029: 00/08/24: Xilinx map trimming error
26079: 00/10/03: Re: "Xilinx Adds FPGA Support to Free Web Design Tools"
26174: 00/10/06: Re: programm Xilinx FPGAs via JTAG
26425: 00/10/16: Re: PCI host
26490: 00/10/18: Virtex pull-up/down resistors question
26504: 00/10/18: Re: Virtex pull-up/down resistors question
26665: 00/10/24: Xilinx configuration: JTAG and SPROM
26888: 00/11/02: clock multiplication and Spartan2 DLL placement constraints
26891: 00/11/02: Re: clock multiplication and Spartan2 DLL placement constraints
26892: 00/11/02: Re: clock multiplication and Spartan2 DLL placement constraints
26911: 00/11/03: Re: clock multiplication and Spartan2 DLL placement constraints
27160: 00/11/13: Xilinx WebPack dll problem
27206: 00/11/15: Re: Webpack 3.2WP3.x from Xilinx is useless
27499: 00/11/24: Re: FPGA Express warning ???
27591: 00/11/29: Re: Virtex bitstream generation
27661: 00/12/01: Xilinx's www down again?
27876: 00/12/13: Setup violation
27883: 00/12/13: Re: Setup violation
28520: 01/01/16: Xilinx UCF/ngdbuild problem
28525: 01/01/16: Re: Xilinx UCF/ngdbuild problem
28530: 01/01/16: Re: Xilinx UCF/ngdbuild problem
28563: 01/01/17: Re: Xilinx UCF/ngdbuild problem
29488: 01/02/23: UCF mode for Emacs?
29720: 01/03/06: Re: rising_edge() on virtex
29779: 01/03/09: Re: Problem with Xilinx 3.3-sp7
29906: 01/03/16: xilinx Webpack missing speed grade
29939: 01/03/19: Re: xilinx Webpack missing speed grade
29941: 01/03/19: Re: xilinx Webpack missing speed grade
29985: 01/03/20: Re: xilinx Webpack missing speed grade
30183: 01/03/27: Re: Logic trimmed (XCS40 F3.1)
30308: 01/04/02: Re: pseudo random numbers
30365: 01/04/04: Re: pseudo random numbers
30398: 01/04/06: Re: Modlesim5.5
30455: 01/04/09: Re: Modlesim5.5
30541: 01/04/13: Re: not IOB
30544: 01/04/13: Re: Modlesim5.5
30726: 01/04/26: Re: Configuration via PCI JTAG
30878: 01/05/02: Re: USB CORE IN VHDL
31010: 01/05/09: Re: BUFG output is constant0 at 200MHz in post timing
31608: 01/05/31: Re: Help with vhd
32630: 01/07/03: Re: Nets with more than one driver
33309: 01/07/23: Homemade Xilinx parallel cable problem
33315: 01/07/23: Re: Homemade Xilinx parallel cable problem
33353: 01/07/24: Re: Homemade Xilinx parallel cable problem
33383: 01/07/25: Re: Homemade Xilinx parallel cable problem
33384: 01/07/25: Re: FPGA Express or Spectrum?
33429: 01/07/26: Re: Prom: Download problem
33585: 01/07/31: Re: ERROR
33683: 01/08/02: Re: ERROR
33818: 01/08/06: Re: Homemade Xilinx parallel cable problem + new question
33909: 01/08/08: Re: Spartan-2 and homemade parallel cable
34310: 01/08/20: Xilinx XC18V PROM problem
34824: 01/09/10: Re: Xilinx dev. kit for Linux?
34846: 01/09/11: Re: Using falling and rising clock mistery.
34941: 01/09/14: Re: A vs. X
34965: 01/09/17: Re: A vs. X
35175: 01/09/25: Xilinx Virtex RLOC question
35187: 01/09/25: Xilinx implementation problem
35431: 01/10/04: Xilinx Spartan2E samples availability?
35449: 01/10/05: Re: Xilinx Spartan2E samples availability?
35929: 01/10/24: Re: Bidirectional port is converted to input during synthesis
35930: 01/10/24: Re: map,place &route
36116: 01/10/30: Re: Autostart Problem SPROM->FPGA
36398: 01/11/08: Re: "Illegal assignment" message, NEED HELP, PLEASE!!!
36458: 01/11/09: Re: "Illegal assignment" message, NEED HELP, PLEASE!!!
36460: 01/11/09: Xilinx unconnected logic
36479: 01/11/09: Re: Xilinx unconnected logic - always connected!
37403: 01/12/10: Re: SpartanIIE
38177: 02/01/08: Re: multiply (*) 11000000000
38509: 02/01/16: Re: Leonardo + Xilinx tools help
38521: 02/01/16: Re: Leonardo + Xilinx tools help
40020: 02/02/25: Re: Synplify warning that I don't understand
40968: 02/03/19: Re: FIFO general question
43725: 02/05/31: Lattice .ldf to VHDL help
44780: 02/07/01: Re: How can I preserve FFs in LeonardoSpectrum?
45287: 02/07/18: Re: Problem with OpenCore PCI IP Core
45849: 02/08/07: Getting crazy: abnormal behavior (Xilinx Spartan2E)
45870: 02/08/08: Re: Getting crazy: abnormal behavior (Xilinx Spartan2E)
46455: 02/08/30: Re: problem configration spartan2 with prom.
51554: 03/01/16: Re: Xilinx Constraint Problem
53122: 03/03/04: Re: xilinx Dsgnmgr does not support Asynchronous Fifo on Spartan II
53334: 03/03/11: Re: comp.arch.fpga : VCC shorted to GND within FPGA???
64579: 04/01/08: Re: old articels of this newsgroup
64916: 04/01/16: Power-up input value detection
67398: 04/03/11: Re: very strange error
67408: 04/03/11: Re: very strange error
67748: 04/03/18: Re: "WARNING:Xst:528 - Multi-source in Unit <entity> on signal <sig>
68474: 04/04/06: Re: Problem for CNA/CAN conversion
69903: 04/05/24: Re: VHDL simple question: is 2-D array synthesizable
70175: 04/06/08: Re: Good SDRAM Controller
70380: 04/06/15: Re: >Math Skills = >Engineer ?
71893: 04/08/03: ISE WebPack and IPs (no CoreGen)Xilinx
72159: 04/08/10: Re: Now I am really confused!
72375: 04/08/17: Xilinx WebPack Spartan3 DCM implementation problem
72408: 04/08/18: Re: Xilinx WebPack Spartan3 DCM implementation problem
72416: 04/08/18: Porting design constraints from A to X: help
73386: 04/09/21: Re: Verilog vs VHDL for Loops
73679: 04/09/28: Re: VHDL inout used for non bidirectional uses
74740: 04/10/18: Re: Internal Capture of clock in FPGA
74794: 04/10/19: Re: Experiences with SPARTAN3?
74425: 04/10/11: Xilinx Spartan3 config problem
74463: 04/10/12: Re: Xilinx Spartan3 config problem
74466: 04/10/12: Re: Xilinx Spartan3 config problem
75415: 04/11/05: Re: chipscope pro problem (par)
75507: 04/11/08: QuartusII, Flex10K & fan-out
75545: 04/11/09: Re: [ANN] InFormal 0.1.1 Released
75546: 04/11/09: Re: chipscope pro problem (par)
75822: 04/11/16: Re: OpenCore USB 2.0
76382: 04/12/01: Altera equivalent for Xilinx's "async_reg" attribute
76547: 04/12/06: Re: JTAG recognise xcv50e instead of xc2s50e
76605: 04/12/07: Re: adding signals to chipscope pro debugging
77376: 05/01/05: Altera Flex10K Fast Output Register warning
77403: 05/01/06: Re: Altera Flex10K Fast Output Register warning
77601: 05/01/12: Re: Signaltap - Finding Nodes - FSM state register
77822: 05/01/18: Re: Creating a pyramid of shift registers
77828: 05/01/18: Re: Creating a pyramid of shift registers
78626: 05/02/04: Altera, QuartusII and internal tristates
84251: 05/05/16: Altera Apex20KE PLL output jitter problem
84665: 05/05/24: Re: Xilinx Answer Record 21127
84787: 05/05/27: Re: Altera Apex20KE PLL output jitter problem
88057: 05/08/08: Re: Holding in output registers
89676: 05/09/21: Re: Xilinx ModelSim VHDL Running Two Models
89677: 05/09/21: Re: Xilinx ModelSim VHDL Running Two Models
89807: 05/09/26: Re: vhdl state maching problem
90123: 05/10/05: Re: vhdl question
91841: 05/11/15: Re: i2c slave does not acknowlege
91940: 05/11/17: Re: Trying to define Opendrain Outputs
94746: 06/01/17: Re: Unassigned pins
97500: 06/02/23: ARCnet interface gate count
97588: 06/02/24: Re: ARCnet interface gate count
101513: 06/05/02: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
105902: 06/08/02: Re: generating sine-like waveforms
105956: 06/08/03: Re: generating sine-like waveforms
106012: 06/08/05: Re: DDR Controller
106087: 06/08/07: Re: verilog versus vhdl
110491: 06/10/16: Re: how to change cclk frequency ?
111118: 06/10/29: Re: A spectre is haunting this newsgroup, the spectre of metastability
111231: 06/10/31: Re: A spectre is haunting this newsgroup, the spectre of metastability
111517: 06/11/04: Re: PCI
113131: 06/12/06: Re: VHDL Variable Length Input file.
113423: 06/12/13: Re: Tarfessock1
113912: 06/12/28: Re: remove logic redundancy
113932: 06/12/29: Re: remove logic redundancy
115755: 07/02/19: Re: Testing FPGA
117646: 07/04/05: Re: OT Re: Gray code in asynchronous FIFO design
118355: 07/04/24: Re: VHDL editing with UltraEdit
124661: 07/09/29: Re: Own soft-processor
125624: 07/10/30: Updating my bookshelf
127290: 07/12/17: How to use a generic memory with Xilinx ?
128066: 08/01/14: Re: Complex Multiply
128069: 08/01/14: Re: Complex Multiply
128902: 08/02/09: Re: function/process to generate sine and cosine wave
131341: 08/04/20: Re: Very simple VHDL problem
131388: 08/04/21: Re: Very simple VHDL problem
131849: 08/05/04: Re: Old FPGA question
132415: 08/05/26: Re: How to update a row and a column at the same clock cycle?
133723: 08/07/11: Re: VHDL code for DDFS
135498: 08/10/05: Spartan 3E overmapping problem
135512: 08/10/06: Re: Spartan 3E overmapping problem
135534: 08/10/06: Re: Spartan 3E overmapping problem
135604: 08/10/09: Re: More Actel 'Funnies'
135678: 08/10/12: Re: More Actel 'Funnies'
135716: 08/10/13: Re: More Actel 'Funnies'
136695: 08/12/01: Re: simulation results is correct but synthesis result is not correct
137165: 08/12/29: Re: Code Indentation
137583: 09/01/22: Re: Digilent USB Cable supported Devices
138953: 09/03/16: Re: SPI controller for FPGA
140236: 09/05/05: ISE & VHDL : how to include time/date
140246: 09/05/05: Re: Setting top level VHDL generics in XST
140350: 09/05/10: Re: ISE & VHDL : how to include time/date
140631: 09/05/20: Re: Port assignment question
143124: 09/09/22: Xilinx XST and counter synthesis problem
148356: 10/07/15: Another Xilinx webpack download rant
148371: 10/07/15: Re: Another Xilinx webpack download rant
148376: 10/07/16: Re: Another Xilinx webpack download rant
149397: 10/10/21: Re: ZIGBEE with FPGA
150188: 10/12/29: Re: Error in Clock Divider!
150496: 11/01/24: Re: Xilinx news
151124: 11/03/08: Re: Pull up/down resistors on Spartan-3E configuration inputs
152384: 11/08/17: Altera Flex10K support ?
152387: 11/08/17: Re: Altera Flex10K support ?
153557: 12/03/27: Re: FPGA communication with a PC (Windows)
153780: 12/05/17: Re: Xilinx ISE Multiple Drivers Error
153783: 12/05/17: Re: Xilinx ISE Multiple Drivers Error
154458: 12/11/05: Re: Xilinx XC3S400 reproducibility madness
154462: 12/11/06: Re: Xilinx XC3S400 reproducibility madness
154536: 12/11/25: Re: VHDL expert puzzle
154537: 12/11/25: Re: VHDL expert puzzle
154548: 12/11/26: Re: VHDL expert puzzle
154725: 12/12/29: Re: Which to learn: Verilog vs. VHDL?
154849: 13/01/18: Re: Button clock
155254: 13/06/19: Re: Chasing Bugs in the Fog
156604: 14/05/11: Re: need coding
157460: 14/12/11: Re: difference between fpga and epld
160297: 17/11/04: Re: Digital-to-Analog Converter LTC 2624, Spartan-3A
160472: 18/02/01: Re: Interface on board ADC to Spartan 3E startkit
160476: 18/02/04: Re: Interface on board ADC to Spartan 3E startkit
160920: 18/12/18: Re: Philips LA PM3585 disassembler software wanted
160954: 19/01/05: Re: Can I use Verilog or SystemVerilog to write a state machine with
160956: 19/01/05: Re: Can I use Verilog or SystemVerilog to write a state machine with
161106: 19/02/02: Re: Open Source Synthesis Tools
161354: 19/04/22: Re: FIFO timing, the right way
161355: 19/04/22: Re: Up/Down Binary Counter with Dynamic Count-to Flag
161357: 19/04/22: Re: FIFO timing, the right way
Nicolas Paul Collin Gloster:
116642: 07/03/14: Re: /* synopsys enum state_code */ on XST???
Nicolas Schwarzentrub:
80705: 05/03/10: looking for PCI board with fpga and 1394 interface
80765: 05/03/11: Re: looking for PCI board with fpga and 1394 interface
81160: 05/03/18: 1394 Dcam wiht Xilinx FPGA
NICOLAS TRIBIE:
1985: 95/09/28: Xilinx Flash FPGA ??
nicolas.gac:
79686: 05/02/23: re:xil_malloc vs malloc
Nicole Y. Chen:
29860: 01/03/13: Programming CPLD and FPGA on XESS board for Ethernet.
<Nicolette.Sheriden@Nude.Here.com>:
Niels Sandmann:
100408: 06/04/08: Compiler to FPSLIC
100443: 06/04/09: Re: Compiler to FPSLIC
100444: 06/04/09: Re: Compiler to FPSLIC
100445: 06/04/09: Re: Compiler to FPSLIC
100446: 06/04/09: Re: Compiler to FPSLIC
100447: 06/04/09: Re: Compiler to FPSLIC
100448: 06/04/10: Re: Compiler to FPSLIC
Niels Thomsen:
52251: 03/02/05: Distributing component without source
nierveze:
127500: 07/12/29: a newbie question
nig:
65700: 04/02/04: I comes up against a STA probem by tool PrimeTime
Nigel:
73446: 04/09/21: Using C++ on NIOS
73522: 04/09/22: Re: Using C++ on NIOS
102738: 06/05/19: CPLD (CoolRunner) failures.
102794: 06/05/20: Re: CPLD (CoolRunner failures)
102854: 06/05/22: Re: CPLD (CoolRunner failures)
102855: 06/05/22: Re: CPLD (CoolRunner failures)
102895: 06/05/22: Re: CPLD (CoolRunner failures)
102896: 06/05/22: Re: CPLD (CoolRunner failures)
102897: 06/05/22: Re: CPLD (CoolRunner failures)
102901: 06/05/22: Re: CPLD (CoolRunner failures)
Nigel Burrows:
3765: 96/07/27: Re: Clearing security fuse on Lattice ispLSI2032?
Nigel Elliot:
157160: 14/10/22: Re: [cross-post] verification vs design
Nigel Gulstone:
72297: 04/08/13: Re: Xilinx 804 Aurora vhdl Design patch
72384: 04/08/17: Re: Xilinx 804 Aurora vhdl Design patch
Nigel Gunton CEMS STAFF:
70953: 04/07/02: nios-run ignores kbd.
71006: 04/07/05: Re: nios-run ignores kbd.
Nigel Orr:
19265: 99/12/09: Re: hobbyist friendly pld?
<nigel.gunton@uwe.ac.uk>:
78389: 05/01/31: quartus hierarchy strangeness
78508: 05/02/02: Re: quartus hierarchy strangeness
NigelE:
110615: 06/10/18: Re: Scoreboard and Checker in Testbench?
110651: 06/10/19: Re: Scoreboard and Checker in Testbench?
110683: 06/10/19: Re: Scoreboard and Checker in Testbench?
111450: 06/11/03: Re: SystemVerilog not use Mail-box directly in VMM and AVM ?
111458: 06/11/03: Re: SystemVerilog not use Mail-box directly in VMM and AVM ?
118435: 07/04/26: Re: Modelsim simulation progress in batch/command line mode?
139648: 09/04/08: Re: Two stage synchroniser,how does it work?
143922: 09/11/03: Re: ModelSim view internal signals in instantiated verilog modules
143935: 09/11/04: Re: ModelSim view internal signals in instantiated verilog modules
143939: 09/11/04: Re: ModelSim view internal signals in instantiated verilog modules
nigelg:
74581: 04/10/14: Re: Same Bitstream: Different Performance
80037: 05/02/28: Re: RocketIO, where to start?
80110: 05/03/01: Re: RocketIO, where to start?
niggu:
80801: 05/03/11: Re: looking for PCI board with fpga and 1394 interface
Niieg:
142606: 09/08/20: Wildcards in Quartus TCL Scripting
142623: 09/08/22: Re: Wildcards in Quartus TCL Scripting
142629: 09/08/22: Re: FM Broadcast receiver on Lyrtech SFF SDR Kit using vertex 4
143052: 09/09/17: Quartus top level entity name vs names of generated files
143104: 09/09/21: Re: Quartus top level entity name vs names of generated files
Nik Simpson:
63293: 03/11/19: Re: 400 Mb/s ADC
63328: 03/11/19: Re: 400 Mb/s ADC
63345: 03/11/19: Re: 400 Mb/s ADC
63391: 03/11/20: Re: 400 Mb/s ADC
nike:
139406: 09/03/28: XST segmentation fault on top level synthesis
139413: 09/03/28: Xilinx options (synthesis and map) in Synplify Pro
Nikhil Bhatia:
46753: 02/09/07: symplicity conv_integer problem
Nikhil Krishna:
18375: 99/10/20: Re: New to FPGA
Nikhil Kumar Mittal:
31443: 01/05/24: Need allegro footprint for Intel's IXP1200 ?
nikhil w:
56801: 03/06/16: FPGA topics for study
nikhilghanathe@gmail.com:
160664: 18/09/07: System Verilog Import package error
niki:
30435: 01/04/08: Re: Handel-C
30440: 01/04/08: Re: Handel-C
30451: 01/04/08: Re: Handel-C
30493: 01/04/11: Re: Handel-C
30494: 01/04/11: Re: Dist_ram :Memory instantiation
30534: 01/04/12: Re: Handel-C
Niki Steenkamp:
32698: 01/07/05: Re: 8031 microcontroller on FPGA development board :-(
32846: 01/07/10: Re: What chip!?
65860: 04/02/08: Opinion on Altium's nVisage VHDL tools?
65946: 04/02/10: Re: Synchronization of signals
Nikiforakis Manos:
32219: 01/06/20: Gray counter STRUCTURAL (VHDL)
32274: 01/06/21: Re: Gray counter STRUCTURAL (VHDL)
Niklas Holsti:
133559: 08/07/03: Re: External Clock Generator
138806: 09/03/11: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
147508: 10/04/29: Re: I'd rather switch than fight!
152289: 11/08/03: Re: Regarding process time calculation
153068: 11/11/25: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
<niklas_molin@hotmail.com>:
135756: 08/10/14: Virtex 5, DDR2 access
135775: 08/10/15: Re: Virtex 5, DDR2 access
Niko Zhang:
56677: 03/06/11: Re: HDLmaker update available
Nikola Dragas:
64928: 04/01/16: WebPACK and foldback nands
Nikolaos Kavvadias:
149211: 10/10/07: ANN: Multi-port register-file (memory) generator
152122: 11/07/11: [ANN] HercuLeS high-level synthesis tool
152130: 11/07/12: Re: HercuLeS high-level synthesis tool
152132: 11/07/12: Re: HercuLeS high-level synthesis tool
152135: 11/07/12: Re: HercuLeS high-level synthesis tool
152147: 11/07/13: Re: HercuLeS high-level synthesis tool
152187: 11/07/17: Re: Issues with Soft-Cores
152903: 11/10/31: [ANN] Free web access to the HercuLeS high-level synthesis tool
155202: 13/06/03: [ANN] XMODZ-Fast modulo reduction VHDL IPs
155204: 13/06/04: Re: XMODZ-Fast modulo reduction VHDL IPs
155206: 13/06/04: Re: XMODZ-Fast modulo reduction VHDL IPs
155207: 13/06/05: Re: XMODZ-Fast modulo reduction VHDL IPs
155221: 13/06/13: [ANN] LOOPGEN-Fast hardware looping VHDL IPs
155222: 13/06/13: Re: New soft processor core paper publisher?
155495: 13/07/02: Free evaluation of HercuLeS high-level synthesis now available from
155967: 13/10/30: FREE download of HercuLeS high-level synthesis!
155970: 13/10/30: Re: draw lines, circles, squares on FPGA by mouse and display on VGA
155977: 13/11/01: Re: FREE download of HercuLeS high-level synthesis!
156001: 13/11/05: Re: Verilog Binary Division
156003: 13/11/05: Re: Verilog Binary Division
156009: 13/11/08: Re: Verilog Binary Division
156016: 13/11/09: Re: FREE download of HercuLeS high-level synthesis!
156047: 13/11/13: Re: Verilog Binary Division
156627: 14/05/15: Re: need coding
156779: 14/06/24: Re: A free VHDL simulator
157069: 14/09/22: Re: opencores.org
157085: 14/10/07: [RFC] METATOR: A look into processor synthesis - What's next?
157086: 14/10/07: elemapprox -- The Rosetta stone of elementary functions approximation
157094: 14/10/09: Re: looking for systemC/TLM 2.0 courses
157098: 14/10/10: Re: looking for systemC/TLM 2.0 courses
157113: 14/10/13: Re: [RFC] METATOR: A look into processor synthesis - What's next?
157114: 14/10/13: Re: [RFC] METATOR: A look into processor synthesis - What's next?
157323: 14/11/21: Re: Bypass Xilinx flexlm license check
157847: 15/04/17: Re: Division by a constant
159463: 16/11/19: Re: Tools on Linux
Nikolay:
19995: 00/01/21: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20018: 00/01/24: Re: Indexing functions
20431: 00/02/10: Data conversion tools
Nikolay Rognlien:
22114: 00/04/25: Re: which pci board?
22221: 00/05/02: Re: Verilog Compiler ?
23863: 00/07/13: Re: AHDL question
Nikos:
8621: 98/01/14: Foundation or Workview Office?
Nikos Annitsakis:
58713: 03/07/31: Novice problem with Altera MaxPlusII and VHDL
Nikos Mouratidis:
8665: 98/01/19: Re: Foundation or Workview Office?
<nikos@bops.com>:
16912: 99/06/16: JOB: Employment Opportunities at BOPS (Chapel Hill, NC)
Nils:
93451: 05/12/22: Re: real-time compression algorithms on fpga
96176: 06/01/31: ERROR message when programming FPGA with Altium Designer 2004
96183: 06/01/31: Re: ERROR message when programming FPGA with Altium Designer 2004
96595: 06/02/07: Re: ERROR message when programming FPGA with Altium Designer 2004
135783: 08/10/16: Re: free cpu 8051 verilog code
157606: 14/12/28: Re: Prime number in verilog
Nils Koehler:
5099: 97/01/23: Altera Max Plus 2 Software bug
5662: 97/03/05: Altera LPM_MUX Function
79695: 05/02/23: Altera JTAG Jam STAPL player portet to Linux for Byteblaster?
Nils Petter Vaskinn:
55447: 03/05/08: Re: Software and hardware monopoly is bad
Nils Strandberg:
74938: 04/10/21: Re: interfacing a PC based program with a FPGA
nimayshah:
100496: 06/04/10: Distributed Arithmetic
100497: 06/04/10: Re: Distributed Arithmetic
100521: 06/04/10: Re: Distributed Arithmetic
<nimby@jetlink.net>:
5990: 97/04/02: Re: New Technology
Nimrod Mesika:
34881: 01/09/12: Re: QPSK modulator with no multipliers
35290: 01/09/27: Re: fir filter on ASIC
43842: 02/06/04: VirtexE DLL Output clock phase
43885: 02/06/05: Re: VirtexE DLL Output clock phase
53217: 03/03/06: Re: Implementation of latch in FPGA
Nina Pinto:
1206: 95/05/13: Re: Looking for a few good web sites.
<ningxue2000@yahoo.com>:
89673: 05/09/21: Re: SoC embedded FPGA
Nir:
57792: 03/07/07: Nios bash acting bizzar
57833: 03/07/07: Re: Nios bash acting bizzar
Nir Dahan:
32584: 01/07/01: DLL/PLL inside
33889: 01/08/07: Re: eine Frage
122566: 07/07/31: ASIC Digital Design Blog
122580: 07/07/31: Re: ASIC Digital Design Blog
122621: 07/08/01: Re: ASIC Digital Design Blog
123508: 07/08/29: Re: Interview Questions
124170: 07/09/13: Re: Uses of Gray code in digital design
129140: 08/02/15: Re: how to implement this...
129161: 08/02/16: Re: how to implement this...
129380: 08/02/22: Re: Interview questions
<niraj0703@my-dejanews.com>:
11545: 98/08/22: FPGA beginner searching for the proper direction
Niranjan Cooray:
1066: 95/04/24: Re: SIS (where do I find it)
Niranjandas:
53354: 03/03/11: Help understanding 7408 and gate chip
53472: 03/03/13: Re: Help understanding 7408 and gate chip
53473: 03/03/13: About VLCT
53555: 03/03/15: Re: About VLCT
53690: 03/03/19: Re: Help understanding 7408 and gate chip
Nirav:
133491: 08/07/01: Board for Hardware in loop
134497: 08/08/13: Hardware in Loop
134760: 08/08/28: Re: Hardware in Loop
Nirav Raval:
81561: 05/03/27: A newbie question (Xilinx or Altera Env?)
101520: 06/05/02: ESL and Spartan Starter Kit
Nirav Shah:
73900: 04/09/30: System Generator.
77794: 05/01/17: FPGA Board with RF Front end
77809: 05/01/17: Re: FPGA Board with RF Front end
nishad:
144127: 09/11/12: max. sinking current of XC95144xl cpld
144139: 09/11/12: Re: max. sinking current of XC95144xl cpld
Nisheeth:
80017: 05/02/28: Re: block adder for Altera!
<nishioka@my-deja.com>:
26130: 00/10/05: Re: Category : virtex e I/O bank contention
26131: 00/10/05: Re: Category : virtex e I/O bank contention
28148: 00/12/23: Re: "lo profile" PLCC sockets
Nisreen Taiyeby:
27657: 00/12/01: fpga: 32 bit parity generation in 4 ns for virtexE
27829: 00/12/11: Fpga:How can I specify RLOC constraint in Leonardo
27865: 00/12/12: fpga :CLB locking prevents flops to be in IOB's
27656: 00/12/01: fpga: 32 bit parity generation in 4 ns for virtexE
30843: 01/05/01: Exemplar: If-elsif synthesises to Muxcy in virtexE
34597: 01/08/30: FPGA: time_sim.sdf does not have the setup times f
34650: 01/09/01: Re: FPGA: time_sim.sdf does not have the setup times f
35587: 01/10/11: Exemplar : LUT's are ix & Nets are nx
Nitesh:
88463: 05/08/18: Download bit stream onto ml310 ( virtex 2 pro ) using uart cable
88471: 05/08/18: Re: Download bit stream onto ml310 ( virtex 2 pro ) using uart cable
89239: 05/09/08: EDK 7.1 simulation
89266: 05/09/09: compedklib error
89310: 05/09/12: modelsim simulation problem
89320: 05/09/12: Re: modelsim simulation problem
89606: 05/09/20: OPB bus communication
89723: 05/09/23: Re: OPB bus communication
89741: 05/09/23: Re: OPB bus communication
89792: 05/09/26: chipscope pro
89828: 05/09/27: Re: chipscope pro
89833: 05/09/27: Re: chipscope pro
89864: 05/09/28: Re: chipscope pro
89879: 05/09/28: Re: chipscope pro
90022: 05/10/02: Re: for...generate loop with generics, constants (vhdl)
91560: 05/11/08: pci ml310 board
91614: 05/11/09: Re: pci ml310 board
91618: 05/11/09: Re: pci ml310 board
93140: 05/12/14: FPGA-pci communication
93206: 05/12/15: Re: FPGA-pci communication
93263: 05/12/16: Re: FPGA-pci communication
93279: 05/12/18: Re: FPGA-pci communication
93478: 05/12/22: Re: FPGA-pci communication
93650: 05/12/27: ERROR:iMPACT:585
94039: 06/01/04: Re: FPGA-pci communication
94198: 06/01/07: DMA over pci
94201: 06/01/07: DMA with powerspan II -Fpga card
94225: 06/01/08: Re: DMA with powerspan II -Fpga card
94241: 06/01/08: Re: DMA with powerspan II -Fpga card
94213: 06/01/08: dma on fpga pci card
94323: 06/01/09: Re: dma on fpga pci card
95645: 06/01/24: Re: dma on fpga pci card
95747: 06/01/25: Re: dma on fpga pci card
99913: 06/03/30: ISE 8.1, EDK 8.1 installation
104758: 06/07/05: PLB master without xilinx ipif
105111: 06/07/13: PLB slaves
105882: 06/08/02: MPD file option HDL
106008: 06/08/04: Re: MPD file option HDL
108584: 06/09/13: Re: removing Ethernet_MAC kills mini-module project
133009: 08/06/13: Re: chipscope analyzer error
Nithin:
77394: 05/01/05: HDMI/TMDS source driver
nithin jayavarapu:
142333: 09/08/05: dcm
<nithin.pal@gmail.com>:
90718: 05/10/19: Spartn 3 configuration failure
Nitin:
61838: 03/10/13: Pass transistor logic in a FPGA
62288: 03/10/24: Pass transistor logic and multi-valued logic in a FPGA
nitin:
36184: 01/11/01: Registered as well as unregistered outputs?
36254: 01/11/03: Re: Registered as well as unregistered outputs?
36255: 01/11/03: Re: Altera Local Routing
36324: 01/11/06: Re: Altera Local Routing
36452: 01/11/09: Is ALtera using segmented routing in Mecury?
36453: 01/11/09: Carry chain in Virtex II
36550: 01/11/12: Re: Carry chain in Virtex II
36668: 01/11/14: ALTDIG & DIG ?
36674: 01/11/15: Re: Carry chain in Virtex II
45065: 02/07/11: Dynamic Addition Subtraction
Nitin Chandrachoodan:
40740: 02/03/14: Proto boards for labs
41011: 02/03/19: Re: Proto boards for labs
41013: 02/03/19: Re: Proto boards for labs
59686: 03/08/25: FPGA minimum operating frequencies
Nitin Jain:
67090: 04/03/05: Viterbi Decoders with 4x throughput
67390: 04/03/10: High throughput Viterbi Decoders
nitinbabukm:
137738: 09/01/28: Re: fpga mac controller with tcp/ip/dhcp
nitins:
88832: 05/08/29: beginner [ query : resources and guidance for a newbie]
Nitro:
68618: 04/04/09: Re: I2C bus and tristate interface for V2pro
75351: 04/11/03: Re: FPGA/CPLD Basics
79370: 05/02/18: Re: DNL and INL calculation
79442: 05/02/19: Re: DNL and INL calculation - Would Bit error rate be better?
79555: 05/02/21: Re: DNL and INL calculation
83851: 05/05/08: Re: Parallel Cable IV opened in "Compatibility Mode"
91356: 05/11/03: Re: use ppc405 on virtex-II pro
93316: 05/12/19: Re: Virtex II Pro XC2VP100
115038: 07/01/29: Re: USB 2.0 Streaming using FPGAs
115039: 07/01/29: Re: Linux on Virtex 4?
123384: 07/08/26: Re: xilinx impact 9.2 problem
133035: 08/06/14: Re: CPLD beginner questions
133837: 08/07/17: Re: First CPLD project
<nitul.das@gmail.com>:
96072: 06/01/29: Acquiring video frames and processing pixels in Xilinx
niv:
38836: 02/01/26: Xlx simprim library
38837: 02/01/26: Re: Xlx simprim library
39187: 02/02/03: Coregen & PAR
39314: 02/02/06: RE Xilinx 3.3SP8, Beware!
40845: 02/03/16: Virtex & CLKDLL
41564: 02/04/02: Re: floorplanning for FPGA
Niv:
39642: 02/02/15: Xilinx Virtex XCV300
40478: 02/03/07: CLKDLL in Virtex
41256: 02/03/23: Too many clocks
41746: 02/04/06: Re: A learner of Modelsim
45376: 02/07/21: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
46492: 02/09/01: Multiplexing a tristate bus?
46947: 02/09/12: Xilinx TBUFs
49895: 02/11/24: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
56903: 03/06/18: Re: WR/RD Problem
62312: 03/10/26: Virtex2 DCMs
67530: 04/03/13: Virtex2 config
67866: 04/03/21: Virtex2
67868: 04/03/21: Re: Virtex2
67912: 04/03/22: Re: Virtex2
70776: 04/06/28: Re: simprim X_FF component
73185: 04/09/15: Xilinx DCMs
73195: 04/09/15: Re: Xilinx DCMs
73196: 04/09/15: Re: Xilinx DCMs
73269: 04/09/17: Re: Xilinx DCMs
112729: 06/11/28: Re: problems with verilog SDRAM models
123148: 07/08/17: Actel APA1000 and JTAG
Niv (KP):
115185: 07/02/02: ProAsic-plus PLL
119690: 07/05/24: Actel timing constraints
119720: 07/05/25: Re: Actel timing constraints
120313: 07/06/05: Re: Actel timing constraints
139709: 09/04/10: Noise in Stratix3?
140048: 09/04/25: Re: Noise in Stratix3?
140052: 09/04/25: Re: Noise in Stratix3?
nivesh:
130944: 08/04/06: Use of floating point numbers in xilinx EDK .........
niyander:
144410: 09/12/04: fpga clock resolution
147617: 10/05/07: Floating Point Division
147625: 10/05/08: Re: Floating Point Division
NJ:
63985: 03/12/10: Re: Soldering of FPGAs
64023: 03/12/12: Re: Which PCI version on my motherboard
64024: 03/12/12: Re: Soldering of FPGAs
64061: 03/12/15: Re: How LVDS Drivers kills?
Nju:
86875: 05/07/07: Re: Verilog exponential operator issues in simulation (ISE 7.1 SP3 w/ ModelSim 6.0a)
Nju Njoroge:
71733: 04/07/28: RISCWatch w/ Linux running on ppc405D: Virtual/Physical mem issues
71797: 04/07/30: Re: RISCWatch w/ Linux running on ppc405D: Virtual/Physical mem issues
74271: 04/10/06: Xilinx ISE 6.3i 'include construct issue
76029: 04/11/22: EDK 6.3i "Entry Point Not Found" error
76030: 04/11/22: Re: How to get the PPC profiler to work in Xilinx VP2 platform?
76064: 04/11/23: Re: EDK 6.3i "Entry Point Not Found" error
76077: 04/11/23: Re: EDK 6.3i "Entry Point Not Found" error
78184: 05/01/25: Designing a simple PLB master using EDK 6.3i
78238: 05/01/26: Re: Designing a simple PLB master using EDK 6.3i
78432: 05/01/31: Re: Designing a simple PLB master using EDK 6.3i
78487: 05/02/01: Re: Designing a simple PLB master using EDK 6.3i
78659: 05/02/04: Re: PPC on Virtex2P: Jumpstart, recommended reading?
79324: 05/02/17: Re: PLB
79354: 05/02/17: Re: PLB
79357: 05/02/17: PPC 405 in Virtex 2 Pro 30-Turning off "Critical-word first" loads
79374: 05/02/17: Re: PLB
79415: 05/02/18: Re: PPC 405 in Virtex 2 Pro 30-Turning off "Critical-word first"
79861: 05/02/25: Re: Ml310(xc2vp30) with ppc 405,multi processor share memory?
79953: 05/02/26: PLB Retry (Rearbitrate ) Request from PLB DDR Slave Controller
80991: 05/03/15: Re: PLB_EDK_Simulation
81244: 05/03/19: Re: DATA2MEM, how do I get the ELF file?
81853: 05/04/02: Re: Question regarding EDK
82532: 05/04/13: Re: PPC405 Performance Monitoring
82552: 05/04/13: Re: PPC405 Performance Monitoring
82554: 05/04/13: Re: PPC405 Performance Monitoring
82557: 05/04/13: Re: PPC405 Performance Monitoring
82619: 05/04/14: Re: PPC405 Performance Monitoring
84745: 05/05/25: Re: RISCWatch and JTAG
85736: 05/06/14: EDK 7.1 installation error: Missing libPortability.dll file
85744: 05/06/15: Re: EDK 7.1 installation error: Missing libPortability.dll file
85769: 05/06/15: Re: EDK 7.1 installation error: Missing libPortability.dll file
86749: 05/07/05: EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a
86790: 05/07/06: Re: EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a
86803: 05/07/06: Re: EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a
86870: 05/07/07: Verilog exponential operator issues in simulation (ISE 7.1 SP3 w/ ModelSim 6.0a)
86874: 05/07/07: Re: Verilog exponential operator issues in simulation (ISE 7.1 SP3 w/ ModelSim 6.0a)
88881: 05/08/30: Re: EDK core wrapping and include files
92153: 05/11/23: Simulating PLB DDR in EDK 7.1 SP2 using ModelSim 6.0a
92213: 05/11/23: Re: Simulating PLB DDR in EDK 7.1 SP2 using ModelSim 6.0a
92262: 05/11/24: ChipScope 7.1 w/ EDK 7.1 data port bit ordering issue
96302: 06/02/01: PLB DDR Controller : Sl_rearbitrate issue
96334: 06/02/02: Re: PLB DDR Controller : Sl_rearbitrate issue
96408: 06/02/03: Re: IP2IP_Addr in IPIF
96486: 06/02/04: Re: IP2IP_Addr in IPIF
97463: 06/02/22: Checkpointing PPC Smartmodels in ModelSim 6.0b Issues
97870: 06/02/28: Re: Checkpointing PPC Smartmodels in ModelSim 6.0b Issues
97933: 06/03/01: Re: IP2IP_Addr in IPIF
99421: 06/03/23: Accessing ModelSim Environment variables in Verilog code
99480: 06/03/24: Re: Accessing ModelSim Environment variables in Verilog code
115213: 07/02/02: data OCM BRAM Issues
115432: 07/02/10: Re: data OCM BRAM Issues
119439: 07/05/18: EDK 8.1i to EDK 9.1i UCF file errors
119519: 07/05/21: Re: EDK 8.1i to EDK 9.1i UCF file errors
Njuguna Njoroge:
81872: 05/04/03: XMD : Running XMD with Caches on
njwang:
137311: 09/01/08: New to FPGA's, please help
nk:
33341: 01/07/23: Re: free VHDL and/or Verilog tools?
33343: 01/07/23: Re: Xilinx Software free
nkishorebabu123:
82328: 05/04/11: Xilinx Platform Studio - Vertex II Pro board
<nkishorebabu123@rediffmail.com>:
84007: 05/05/11: Test the code on FPGA Board...
84928: 05/06/01: Query -V2Pro fpga programming
85095: 05/06/03: Query - ChipScope Pro analyzer
85149: 05/06/06: problem with bitstream file in ChipScope Pro analyzer ..
<nkmlists@gmail.com>:
101044: 06/04/24: vhdl cpu emulator (any interest?)
nmatringe@gmail.com:
152429: 11/08/21: Re: Altera Flex10K support ?
152430: 11/08/21: Re: Altera Flex10K support ?
154453: 12/11/05: Xilinx XC3S400 reproducibility madness
154454: 12/11/05: Re: Xilinx XC3S400 reproducibility madness
154456: 12/11/05: Re: Xilinx XC3S400 reproducibility madness
155555: 13/07/18: Xilinx ISE GUI vs tcl script problem
157103: 14/10/13: ISE 14.6 and picoblaze synthesis problem (translate_on/off directives
157115: 14/10/14: Re: ISE 14.6 and picoblaze synthesis problem (translate_on/off
157116: 14/10/14: Re: ISE 14.6 and picoblaze synthesis problem (translate_on/off
157117: 14/10/14: Re: ISE 14.6 and picoblaze synthesis problem (translate_on/off
<nmm1@cam.ac.uk>:
146846: 10/03/30: Re: Which is the most beautiful and memorable hardware structure in a
146887: 10/03/31: Re: Which is the most beautiful and memorable hardware structure in a CPU?
152569: 11/09/15: Re: The Manifest Destiny of Computer Architectures
152599: 11/09/17: Re: The Manifest Destiny of Computer Architectures
152601: 11/09/17: Re: The Manifest Destiny of Computer Architectures
152604: 11/09/17: Re: The Manifest Destiny of Computer Architectures
152608: 11/09/18: Re: The Manifest Destiny of Computer Architectures
152626: 11/09/19: Re: The Manifest Destiny of Computer Architectures
152627: 11/09/19: Re: The Manifest Destiny of Computer Architectures
152631: 11/09/19: Re: The Manifest Destiny of Computer Architectures
nmn:
104970: 06/07/11: sopc -apex20ke1500xxxx
NN:
131485: 08/04/22: FPGA Verilog state machine lock up
<nnadal@terra.es>:
137596: 09/01/22: Spartan chip expulses an extrange substance
137637: 09/01/25: Re: Spartan chip expulses an extrange substance
137748: 09/01/28: Re: Spartan chip expulses an extrange substance
<nnn>:
111258: 06/10/31: Question about bandwidth of scope?
111269: 06/10/31: Re: Question about bandwidth of scope?
111274: 06/11/01: Re: Question about bandwidth of scope?
111337: 06/11/01: Need flash adc with plcc format?
111378: 06/11/02: Re: Need flash adc with plcc format?
111393: 06/11/02: Re: Need flash adc with plcc format?
nnnnnnnnnnnn:
33902: 01/08/07: Re: URL for XILINX's free 314-page design and sythesis guide (and a question about the Quick Start Guide)
nntp:
66210: 04/02/14: Re: Artificial Intelligence/FPGA
nntp.lucent.com:
53119: 03/03/04: Newbie: Help
nntpman68:
138905: 09/03/14: Re: Cyclone III, DP RAM, and Verilog
138906: 09/03/14: Re: Send data from FPGA to PC via USB
138960: 09/03/17: Re: Send data from FPGA to PC via USB
no one:
154643: 12/12/09: Where to move for an embedded software engineer.
154651: 12/12/11: Re: Where to move for an embedded software engineer.
No This Rat:
72800: 04/09/03: the global output enable pins of lattice ispxpld 5000mv
<no-one@nowhere.com>:
3529: 96/06/15: Re: FPGA Conversions
NO-SPAM damiano:
15216: 99/03/15: Want to learn about FPGA.
15362: 99/03/20: From VHDL to FPGA?
15380: 99/03/21: Re: From VHDL to FPGA?
15393: 99/03/22: Re: From VHDL to FPGA?
15414: 99/03/23: What do you think about philips XPLA?
15544: 99/03/30: Re: From VHDL to FPGA?
15739: 99/04/11: Lattice
15890: 99/04/19: Schematics
15889: 99/04/19: VHDL compiler and simulator?
16320: 99/05/15: Re: Who do you know? Motorola FPGA
<no.email.address.entered@none444.yet>:
26718: 00/10/25: New Web Hosting - $3.95 for 35Mb/CGI/Your Domain and 2Gb Monthly Traffic !!!
no@spam no@spam J.Szamosfalvi:
7176: 97/08/11: Re: Download FLEX10K over the LPT port
no_one:
45510: 02/07/25: Re: Translate the design from FPGA to Custom IC
no_reply:
125318: 07/10/20: Building a Huffman codebook in VHDL
<no_spa2005@yahoo.fr>:
136822: 08/12/07: Re: ISE doesn't work after a crash
137506: 09/01/21: Re: Ethernet on Spartan 3A to send Data to PC
138855: 09/03/12: Re: How to initialize the Xilinx FIFO with predetermined value on
140176: 09/05/01: Re: ISE/EDK/SDK 11.1 licensing
no_spam:
49719: 02/11/20: spartan-II Block RAM
noam:
13080: 98/11/15: This is the Subject line !
13090: 98/11/16: Sorry
Nobby Anderson:
140749: 09/05/25: Re: Architecture of FPGA
140774: 09/05/25: Re: Architecture of FPGA
140802: 09/05/26: Re: Architecture of FPGA
141296: 09/06/16: Re: what is non-aligned -- memory accesses ?
144228: 09/11/20: Re: EDK11 under 64-bit OS
151490: 11/04/13: Re: Altium Limited closing up shop - Altium Designer discontinued
151497: 11/04/13: Re: Altium Limited closing up shop - Altium Designer discontinued
151502: 11/04/14: Re: Altium Limited closing up shop - Altium Designer discontinued
Nobby Here:
133633: 08/07/07: Virtex 4 expected production end-of-life
nobody:
141797: 09/07/09: pullup
141811: 09/07/10: Re: About configuring FPGAs
141815: 09/07/10: pullup
141816: 09/07/10: Re: pullup
141826: 09/07/10: Re: pullup
141836: 09/07/11: Re: pullup
142911: 09/09/07: Bidirectional Bus
142925: 09/09/08: bidirectional bus
142930: 09/09/08: Re: Bidirectional Bus
142938: 09/09/09: Re: Bidirectional Bus
142945: 09/09/09: Re: Bidirectional Bus
142950: 09/09/09: Re: Bidirectional Bus
142967: 09/09/10: Re: Bidirectional Bus
142975: 09/09/11: Re: Bidirectional Bus
143128: 09/09/22: USB programmable Open Source Hardware
143142: 09/09/23: Re: Problem with using write and write function
143144: 09/09/23: Re: USB programmable Open Source Hardware
143157: 09/09/23: Re: USB programmable Open Source Hardware
143176: 09/09/24: Re: USB programmable Open Source Hardware
143205: 09/09/25: Re: USB programmable Open Source Hardware
143257: 09/09/28: Re: USB programmable Open Source Hardware
143281: 09/09/29: Re: USB programmable Open Source Hardware
143293: 09/09/30: Re: USB programmable Open Source Hardware
143298: 09/09/30: Re: USB programmable Open Source Hardware
143664: 09/10/20: Teammates, interested?
143665: 09/10/20: Re: Any interest in a group Xilinx FPGA board build/buy ??
143693: 09/10/21: Re: Teammates, interested?
144356: 09/11/30: Re: Reading Altera datasheets
157769: 15/03/10: Compiling Xilinx libraries for ModelSim PE 10.4 simulation out of ISE 8.2i
157787: 15/03/27: Interpret a VHDL statement within a serial to paralell port
157802: 15/03/30: Re: Interpret a VHDL statement within a serial to paralell port
157803: 15/03/30: Re: Interpret a VHDL statement within a serial to paralell port
160592: 18/05/08: CPLD 1.8V to 3.3V bidirectional SDA
160593: 18/05/08: Re: CPLD 1.8V to 3.3V bidirectional SDA
Nobody:
52348: 03/02/07: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
Nobody Here:
120642: 07/06/12: Virtex-4 pre-configuration pull-ups
120780: 07/06/16: Re: Virtex-4 pre-configuration pull-ups
120790: 07/06/16: Re: Virtex-4 pre-configuration pull-ups
133645: 08/07/08: Re: Virtex 4 expected production end-of-life
<nobody@nowhere.com>:
8498: 97/12/25: Re: Xilinx Copy Protection
<nobody@nowhere>:
14258: 99/01/22: DTMF Decoder in a FPGA/XILINX ?
Noddy:
30877: 01/05/02: Newbie
30943: 01/05/04: Configuration Problems: Newbie
31217: 01/05/15: Can't drive?
31751: 01/06/05: Download problems
31991: 01/06/10: Newbie
32500: 01/06/28: Primitive vs. Core
32612: 01/07/02: Re: Digital PLL, frequency multiplication: looking for problem : )
32781: 01/07/09: Clock buffers
32783: 01/07/09: Online threshold limit counter
32835: 01/07/10: Re: Online threshold limit counter
32836: 01/07/10: Re: Two's complement to binary translation problem
32842: 01/07/10: Adder/Subtracter Core???
32929: 01/07/12: Design entry
33085: 01/07/17: Unconnected nets
33134: 01/07/18: Project implementation
33204: 01/07/19: Taking 4MSB a problem in 2's complement?
33350: 01/07/24: Reset during accumulation
33357: 01/07/24: Re: Reset during accumulation
33407: 01/07/25: Digital Mixer
33589: 01/07/31: Schematic user info
34621: 01/08/31: Ugly signal output...
34692: 01/09/04: Open collector outputs
34752: 01/09/06: Missing bits
34775: 01/09/07: Re: Missing bits
34844: 01/09/11: Timing constraints
34853: 01/09/11: Missing bits Part 2!
34855: 01/09/11: Re: Missing bits Part 2!
34871: 01/09/12: Error messages
35061: 01/09/20: Timing constraints...
35067: 01/09/20: Re: Timing constraints...
35131: 01/09/22: Complex mixer LUT
35132: 01/09/22: Re: Complex mixer LUT
35147: 01/09/24: Re: Complex mixer LUT
35160: 01/09/24: Registered outputs...
35180: 01/09/25: Logical constraints of LUT
35185: 01/09/25: CLKDLL question
35186: 01/09/25: Re: How to fix the hold time violation (clock skew>data skew) in QuartusII
35252: 01/09/27: Re: Logical constraints of LUT
35258: 01/09/27: Block RAM instantiation
35259: 01/09/27: Re: Block RAM instantiation
35272: 01/09/27: Re: Logical constraints of LUT
35278: 01/09/27: Re: Logical constraints of LUT
35305: 01/09/28: Global Clock to Pad constraint
35335: 01/09/29: Timing on output
35357: 01/10/01: 45 degree mixer
35360: 01/10/01: Re: 45 degree mixer
35421: 01/10/04: Re: Xilinx Foundation vs. ISE
35714: 01/10/15: Improving timing
35738: 01/10/16: Re: Improving timing
35769: 01/10/17: Recommended Newsgroup
35959: 01/10/25: Recommend a book
36394: 01/11/08: Bit scaling
39549: 02/02/13: Foundation 4.1 vs. ISE 4.1?
39596: 02/02/14: Re: Foundation 4.1 vs. ISE 4.1?
40747: 02/03/14: Re: Proto boards for labs
40916: 02/03/18: Re: just bought...
40917: 02/03/18: Re: just bought...
40918: 02/03/18: Re: just bought...
41347: 02/03/26: Re: Xilinx 4.2i not working on my design
41435: 02/03/28: Filter design problem
41638: 02/04/04: Re: Signals pollution.
42366: 02/04/22: Signal saturation
42454: 02/04/24: Frequency synthesiser
42486: 02/04/25: Re: Frequency synthesiser
42502: 02/04/25: Re: Frequency synthesiser
42522: 02/04/26: Re: Frequency synthesiser
42787: 02/05/02: Re: Frequency synthesiser
42864: 02/05/05: Re: Frequency synthesiser
42867: 02/05/05: Re: Frequency synthesiser
42880: 02/05/06: Re: Frequency synthesiser
42919: 02/05/07: Timing Scores
43450: 02/05/21: Re: Signal Fan-out
43451: 02/05/21: Re: Driving high speed external devices from an FPGA
43501: 02/05/22: PROM programming
43670: 02/05/29: Re: extend jtag downloadcable
43954: 02/06/07: Quick newbie question...
44013: 02/06/10: Cascaded PROMS
44018: 02/06/10: Re: Cascaded PROMS
44019: 02/06/10: Power supply caps on PCB
44114: 02/06/12: Re: Digital FM demodulator in FPGA
44172: 02/06/13: Re: Digital FM demodulator in FPGA-continue
44174: 02/06/13: Re: Digital FM demodulator in FPGA-continue
45130: 02/07/13: Re: Accurate Oscillator
45286: 02/07/18: Good VHDL Book...
45326: 02/07/19: Re: Getting started with WebPACK and Verilog
45606: 02/07/29: Complex FIR low pass filters
46035: 02/08/15: Re: Xilinx tools: which one? Esp. schematic
46093: 02/08/19: Polyphase filtering...
46097: 02/08/19: Re: to reduce the circuit design
46136: 02/08/20: Re: Polyphase filtering...
46137: 02/08/20: Re: Polyphase filtering...
46791: 02/09/09: Re: Polyphase filtering...
46862: 02/09/10: Re: Polyphase filtering...
46903: 02/09/11: Re: Polyphase filtering...
47816: 02/10/04: Re: PCB Design for Altera FPGA
48219: 02/10/14: Upgrading...
48266: 02/10/15: Re: Upgrading...
48283: 02/10/15: Re: Upgrading...
48573: 02/10/21: Device support
48574: 02/10/21: ISE vs. Foundation
48598: 02/10/21: Re: Device support
48599: 02/10/21: Re: ISE vs. Foundation
48712: 02/10/23: Re: LCD driver implement with FPGA
48840: 02/10/25: Just some newbie ISE questions...
48870: 02/10/25: Re: Just some newbie ISE questions...
48950: 02/10/28: Re: Just some newbie ISE questions...
48951: 02/10/28: Phased clocks...
48967: 02/10/28: Re: Phased clocks...
48992: 02/10/29: Re: Phased clocks...
48994: 02/10/29: Re: Phased clocks...
49001: 02/10/29: Re: Modelsim help
49002: 02/10/29: Re: Phased clocks...
49003: 02/10/29: SDA FIR Filter CoreGen...
49617: 02/11/18: Re: Anyone has VHDL code for decimator and interpolater?
49793: 02/11/21: Sub-busses...
49933: 02/11/26: Simulator probes...
51261: 03/01/09: External RAM...
51795: 03/01/22: Re: Xilinx Foundation and ISE compatibility
52027: 03/01/29: Re: Installing 2 versions of Xilinx software in the same machine
52195: 03/02/04: First ISE design...
53005: 03/02/28: SDA FIR Filter...
53059: 03/03/02: Re: SDA FIR Filter...
53068: 03/03/03: Startup latency...
53106: 03/03/04: Re: Startup latency...
53132: 03/03/04: Xilinx support...
53339: 03/03/11: Re: FIR Filter from Xilinx
53419: 03/03/13: Re: Adding delay to a signal?
53420: 03/03/13: Re: [Xilinx] Looking for Parallel Cable III ...
53430: 03/03/13: Re: [Xilinx] Looking for Parallel Cable III ...
<nodrog2@my-deja.com>:
23363: 00/06/23: Re: Looking for 'FREE' FPGA software
Noel Klonsky:
35965: 01/10/25: Re: handel-C
35981: 01/10/25: Re: What's the JBits ?
36833: 01/11/21: Re: Elliptic Curves
37451: 01/12/11: Re: Choice of Processor Cores in FPGAs - Both Embedded & Soft
37642: 01/12/18: Re: random number generator in Handel-C?
38064: 02/01/03: Re: asic vs. fpga
41567: 02/04/02: Re: Handel-C vs SystemC
44152: 02/06/12: Re: ALtera SOPC Builder
45314: 02/07/18: Re: HDL generate from handel-C can be accepted by synthesis tools?
46601: 02/09/04: Re: C/C++ to Verilog/VHDL ?!
47667: 02/10/01: Re: TCP/IP in FPGA
49156: 02/11/03: Re: C\C++ to VHDL Converter
49978: 02/11/27: Re: Anybody know of vendors of PCI boards with FPGAs?
54634: 03/04/15: Re: Hardware acceleration for raytracing purposes
57827: 03/07/07: Re: Interfaces in Handelc
Noelia:
34736: 01/09/05: Xilinx design flow
noelia:
28912: 01/01/29: set/reset
28935: 01/01/30: Re: set/reset
29290: 01/02/12: dedicated carry logic
noitarf:
<NOj.duranNO@bcn.NOservicom.es>:
31178: 01/05/14: Re: Getting Started with FPGAs
Nokia_E61i : I am waiting for you!!!!!!:
117996: 07/04/16: How to design a SDIO peripheral card?
NokioGL:
28507: 01/01/15: http://www.datasheetlocator.com/nl
nola94:
143818: 09/10/27: save data from adc in text file
143941: 09/11/04: Re: save data from adc in text file
<nomad@vagabond.com>:
16816: 99/06/11: test 6651
nomalus:
103882: 06/06/13: null waveform element and webpack
noman:
43551: 02/05/23: FPGA and VHDL: question about RAM initialization
nomanland:
63650: 03/11/27: Re: IDE Ultra DMA on a SPARTAN II
None:
116495: 07/03/10: Re: odd warning in Xilinx ISE webpack
none:
37777: 01/12/20: Re: Clock pins in Virtex-E
37809: 01/12/20: Re: Clock pins in Virtex-E
37847: 01/12/21: Re: CE on XILINX FFs and Metastability
68413: 04/04/03: Re: The Logic Behind License Renewal
117038: 07/03/22: Re: XST coverage
129155: 08/02/15: Re: distorted sine wave
131587: 08/04/25: Re: -. . ..- ... --. .-. --- ..- --- .--.
131647: 08/04/27: Re: Problem writing quadrature decoder
136598: 08/11/24: IDELAYCTRL for Xilinx virtex 5
nonoe:
80263: 05/03/03: Re: FPGA tool benchmarks on Linux systems
80266: 05/03/03: Re: Need suggestion abt FFs without RST for pipelined datapath.
80685: 05/03/10: Verilog-2001 and Xilinx ISE 7.1?
Nony Moose:
124837: 07/10/06: Re: FiberChannel SOF
Noob:
152267: 11/07/29: Re: Bitstream compression
152832: 11/10/26: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
152833: 11/10/26: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
152861: 11/10/28: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
152934: 11/11/02: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
153056: 11/11/24: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants
noob13:
149612: 10/11/11: Spartan3 bidirectional 3.3V 5V level shifter
149656: 10/11/15: Re: Spartan3 bidirectional 3.3V 5V level shifter
noone:
63617: 03/11/26: Re: IDE Ultra DMA on a SPARTAN II
<noone@aol.com>:
47784: 02/10/03: Parallel asyncronous configuration of an Altera FPGA
Norbert:
64071: 03/12/15: download ise foundation
64078: 03/12/16: Re: download ise foundation
64085: 03/12/16: Re: download ise foundation
Norbert Abel:
78392: 05/01/31: IPIF
Norbert Bierlox:
30560: 01/04/17: Re: state encoding in Synplify!!!
31206: 01/05/15: Re: Virtex Handbook
Norbert Hermann Pramstaller - nhp:
52496: 03/02/11: Distributed RAM/ROM
Norbert Hoppe:
22715: 00/05/19: Re: FPGA emultaion of a microprocessor
Norbert Kroth:
8056: 97/11/12: xilinx xc4kE and PCI LogiCORE
Norbert Pedersen:
47194: 02/09/19: Old xc5200 with new software
Norbert Stuhrmann:
109301: 06/09/23: Generating PAD report very slow
109659: 06/10/02: Re: Looking for HDL code for sin( a ) and x ** y Functions
113824: 06/12/23: Re: What next next big thing coming for HDL?
<noreeli.schmidt79@gmail.com>:
159688: 17/02/02: Re: VHDL Editors (esp. V3S)
<noreeli.schmidt@gmail.com>:
159129: 16/08/12: Lattice Mico32 Simulation in Modelsim
159132: 16/08/16: Re: Lattice Mico32 Simulation in Modelsim
159133: 16/08/16: Re: Lattice Mico32 Simulation in Modelsim
<noreply.larthe@gmail.com>:
125707: 07/11/01: ISE ignores LOC constraints for BUFGMUX clock buffers
125710: 07/11/01: Re: ISE ignores LOC constraints for BUFGMUX clock buffers
Norm Dresner:
22516: 00/05/10: Re: EETools Topmax
58040: 03/07/13: Re: edge card connectors and high speed design
79222: 05/02/15: Re: Announcing Samplify for Windows: high-speed sampled data compression
Norm Ebsary:
18599: 99/11/02: Job Posting
18619: 99/11/03: NEBS PC
18762: 99/11/12: Career Opportunity
21145: 00/03/08: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
Norman:
54332: 03/04/08: FPGAs & CPLDs driving an LCD
Norman Bollmann:
133268: 08/06/23: FPGA based database searching
133409: 08/06/27: Re: FPGA based database searching
Norman Desal:
25158: 00/08/29: Spurious errors in full FPGA?
Norman Gillaspie:
15837: 99/04/16: FS: Ariel dual DSP cards $300.00 two 320-C31-40 and 2megs of ram
Norman Klein:
5: 94/07/27: Learning about FPGAs
Norman Lo:
160585: 18/04/27: Xilinx Custom IP accessing 16-bit bram
Norman U Adre:
1426: 95/06/21: XNF (XC2018) to ABEL translator available???
Norman Yang:
36167: 01/10/31: Re: timing difference
42032: 02/04/13: DLL property control in UCF
42064: 02/04/15: Re: DLL property control in UCF
norman yang:
31215: 01/05/15: BUFG in Virtex_E
Normand Bélanger:
50418: 02/12/10: Re: hardware image processing - log computation
50466: 02/12/11: Re: hardware image processing - log computation
50474: 02/12/11: Re: hardware image processing - log computation
Norris Leong:
44688: 02/06/27: FPT - Final Call for Papers
nospam:
6768: 97/06/26: Re: Any designs to avoid in FPGAs
46386: 02/08/28: Re: Any FSM optimizer?
46792: 02/09/09: Re: minimalist FPGA system
46817: 02/09/09: Re: Metastability numbers
46834: 02/09/10: Re: Metastability numbers
48292: 02/10/15: Re: VHDL v. Verilog, Xilinx v. Altera.
49057: 02/10/31: Re: How important is simulation?
49565: 02/11/15: Re: cpld pin configuration is wrongly assigned
49613: 02/11/18: Re: Metastability in FPGAs
49635: 02/11/18: Re: Metastability in FPGAs
49659: 02/11/19: Re: Metastability in FPGAs
49660: 02/11/19: Re: Metastability in FPGAs
49825: 02/11/21: Re: clock enable timing analysis
49838: 02/11/22: Re: Metastability in FPGAs
50947: 02/12/23: Re: thermal issues on FPGA
52307: 03/02/06: Re: Max+PlusII: Design Doctor: synchronized by another clock
53813: 03/03/24: Re: Xilinx FPGAs available?
54145: 03/04/03: Re: uP interface question
55049: 03/04/25: Re: Challenge: (n mod 3) in hardware???
56145: 03/05/29: Re: 20 to 5 encoder optimization?
56605: 03/06/10: Re: XC95288 programming problem
56845: 03/06/17: XST verilog problem
56939: 03/06/19: Re: XST verilog problem
56987: 03/06/20: Re: XST verilog problem
57185: 03/06/25: Re: Interfacing IDE
57190: 03/06/25: Re: Interfacing IDE
58719: 03/07/31: Re: DDS question. How to generate a square from a sine wave?
58739: 03/07/31: Re: DDS question. How to generate a square from a sine wave?
58747: 03/08/01: Re: DDS question. How to generate a square from a sine wave?
58809: 03/08/01: Re: DDS question. How to generate a square from a sine wave?
59721: 03/08/27: Re: Thinking out loud about metastability
67032: 04/03/04: Xilinx Webpack 6.2 and Verilog `define ?
69464: 04/05/11: Re: Which board to buy? Status of open source tools?
69508: 04/05/12: virtex dev board?
73808: 04/09/29: Re: Pricing info for Synplify Pro Xilinx...
73867: 04/09/30: Re: A better way to do embedded Floating point?
77179: 04/12/28: Google is turning usenet into crap - was Primers for Handel-C
77187: 04/12/28: Re: Google is turning usenet into crap - was Primers for Handel-C
77320: 05/01/04: Re: Procedure exit on global signal
77342: 05/01/05: Re: Procedure exit on global signal
77343: 05/01/05: Re: Whither common courtesy ?
78953: 05/02/10: Re: Spartan-3 Starter Kit supplier in the UK?
78966: 05/02/10: Re: Spartan-3 Starter Kit supplier in the UK?
78972: 05/02/10: Re: Spartan-3 Starter Kit supplier in the UK?
79103: 05/02/14: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
79132: 05/02/15: Re: Using the 7 segment displays on Xilinx Spartan 3 kit
79982: 05/02/28: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
79987: 05/02/28: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
80256: 05/03/03: Re: EDK evaluation version with Spartan 3 board arrived today
80282: 05/03/03: Re: EDK evaluation version with Spartan 3 board arrived today
80629: 05/03/09: Re: Using LM317S adjustable linear regulator for Spartan 3?
81530: 05/03/26: Re: cheap Xilinx tricks
81535: 05/03/26: Re: cheap Xilinx tricks
82929: 05/04/20: Re: source control and Xilinx ISE 6 and 7
82953: 05/04/20: Re: source control and Xilinx ISE 6 and 7
90290: 05/10/08: Re: Question about metastability that's been on my mind for a while
97042: 06/02/15: Re: Altera RoHS Irony
97052: 06/02/15: Re: Altera RoHS Irony
101392: 06/04/30: Re: Pull up resistors on Spartan 3 mode pins
101689: 06/05/04: LVDS inputs on Cyclone II
101703: 06/05/05: Re: LVDS inputs on Cyclone II
101704: 06/05/05: Re: LVDS inputs on Cyclone II
101991: 06/05/09: Re: Can an FPGA be operated reliably in a car wheel?
102174: 06/05/11: Re: CoolRunner XPLA3 getting axed?
105100: 06/07/13: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
106076: 06/08/07: Re: verilog versus vhdl
112187: 06/11/17: Re: pulse jitter due to clock
115574: 07/02/14: Re: Typical clock frequencies of FPGA designs
115953: 07/02/26: Re: Spartan-3AN
123067: 07/08/15: Re: Delaying a pulse train
123981: 07/09/10: Quick question for an Altera wizard
128905: 08/02/09: Re: My first verilog/cpld project
129057: 08/02/13: Re: My first verilog/cpld project
132043: 08/05/11: Re: Problem writing quadrature decoder
137615: 09/01/23: Re: Spartan chip expulses an extrange substance
138172: 09/02/08: Re: Is this phase accumulator trick well-known???
nospam.eric@gmail.com:
89684: 05/09/22: Network-on-Chip Architectures
89884: 05/09/29: ... failed to route using a CLK template
90060: 05/10/04: Re: vhdl question
90405: 05/10/12: Re: Avoiding meta stability?
92748: 05/12/06: Re: Multi-layer switch network?
92865: 05/12/08: Re: How to connect 2 FPGA?
<nospam@aol.com>:
51592: 03/01/16: Re: Bug in Quartus2 Web 2.2
<nospam@lizard.net>:
24203: 00/07/29: Re: Microprocessors in FPGA
<nospam@newsguy.com>:
41204: 02/03/22: Re: Clock termination affecting JTAG interface
<nospam@nospam.com>:
83000: 05/04/21: FIFO as a Logic Analyzer; Clock synthesizer
84761: 05/05/26: State Machines.. and their efficiency.
153899: 12/06/28: Modelsim MXE on wine?
154304: 12/09/25: Multiple IDELAYCTRLs in V-5: how, and why?
<NOSPAM@NOSPAM.invalid.com>:
59704: 03/08/26: Free FPGA samples anywhere?
<NOSPAM@NOSPAM.NOSPAM>:
29589: 01/02/27: Re: cpul vs vhdl
<nospam@nowhere.com>:
156535: 14/04/17: Re: Help: Altera megafunctions, Quartus II
156545: 14/04/21: Recovering verilog source file from build files.. possible?
<nospam_martin_thompson@yahoo.com>:
18044: 99/09/25: Re: Flex 10k: power-on initialisation of FSM. How to do?
<_nospam_nshimizu_at_bosei_cc_@bosei.cc.u-tokai.ac.jp>:
45590: 02/07/28: SFL2VL now output compatible verilog with Exemplar
Nossum:
78516: 05/02/02: Re: Virtex II Slice Design - ARGH!
Not:
134941: 08/09/07: Re: LVDS Receiver in FPGA
Not Really Me:
74243: 04/10/06: Re: embedded linux on FPGA?
Not who you think:
586: 95/01/12: ASIC '95 Call For Papers
notaxilinx employee:
120159: 07/06/01: Re: 180 differential inputs each 800Mbps using V5
<notgetting@myaddress.com>:
11038: 98/07/14: Re: Reed-Solomon encoding
NoThisRAT:
72810: 04/09/03: the pci signal
72859: 04/09/06: cypress's 32bit pci target reference design?
75284: 04/11/01: compactflash interface problem
74709: 04/10/17: a pci implemenation problem, thanks
74793: 04/10/19: Re: a pci implemenation problem, thanks
74886: 04/10/21: Re: a pci implemenation problem, thanks
75456: 04/11/06: the compactflash true ide mode access
75461: 04/11/06: Re: Problem with Nios Development Board (Cyclone)
75474: 04/11/07: Re: the compactflash true ide mode access
76084: 04/11/24: the irq of IDE/ATA interface
NotMe:
34665: 01/09/02: Re: DSP in OTP
34895: 01/09/13: Re: delay
34899: 01/09/13: Re: Fixed or Floating point for MP3 algorithim?
35153: 01/09/24: Re: comp.arch.fpga : Unusual clock divider ckt
35223: 01/09/26: Re: Gated clocks and shortage of clock buffers
35401: 01/10/03: Re: Barrel Shifter
35611: 01/10/11: Re: High level synthesis will never work well :)
35789: 01/10/17: Re: memory cell
NotTooSmart:
69166: 04/04/28: I think I fried my I/O bank... (virtex-E question)
novato:
72300: 04/08/13: [CPLD] Novice
72318: 04/08/14: Re: [CPLD] Novice
novice:
80287: 05/03/03: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
Novice:
98646: 06/03/14: How do I handle this memory related issue?
98660: 06/03/14: Re: How do I handle this memory related issue?
99094: 06/03/20: What are the major difference between MXE 6.0 and MXE 5.7?
novice09:
142268: 09/07/31: Sarter Kit Spartan-3E Ethernet
Noway2:
90722: 05/10/19: Re: MAC Architectures
91527: 05/11/08: Re: Suggestions/Recommendations with CPLD's and Software
91636: 05/11/10: Re: Suggestions/Recommendations with CPLD's and Software
91748: 05/11/11: Re: Factory Mutual Approvable Sealed Lead Acid Battery
91977: 05/11/18: Re: synthesis
92071: 05/11/21: Re: synthesis
92093: 05/11/22: Re: Quartus Problem
93675: 05/12/28: Re: Can Altera Cyclone device's clock input directly used as CLK with PLL?
94920: 06/01/19: Re: How much do you trust your CAD Program?
95577: 06/01/24: Re: FPGA board with High Speed LVDS
95007: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95016: 06/01/20: Re: OT:Shooting Ourselves in the Foot
96779: 06/02/10: Re: Altera EPLD
96796: 06/02/10: Re: Altera EPLD
97146: 06/02/17: Re: Communication between FPGA and PC with ethernet
97527: 06/02/23: Re: altera max 7128s blanking
97528: 06/02/23: Re: need byteblaster II source code
97601: 06/02/24: Re: altera max 7128s blanking
98145: 06/03/06: Re: How to choose FPGA/CPLD ?
98414: 06/03/09: Nios2 and Shared Bus Resources
105131: 06/07/14: Re: Need for reset in FPGAs
105780: 06/07/31: Re: DDR2 SRAM Stratix II questions
106574: 06/08/15: Webpack ISE simulator error
124883: 07/10/09: Legacy support of a Max 7000S
124942: 07/10/11: Re: Legacy support of a Max 7000S
125381: 07/10/24: Re: Addresses of subsystems
125393: 07/10/24: Re: Addresses of subsystems
134476: 08/08/12: Re: Altera question - MAX3000 vs MAX7000
NPK:
17256: 99/07/15: Easy money !!! and it's REAL
NRClark:
131179: 08/04/14: "Multi-source in Unit" Verilog synthesis woes
136827: 08/12/07: Inverting bus connection order in Verilog
<nrivera.eng@gmail.com>:
86166: 05/06/22: DES core for Xilinx Virtex 2Pro for the EDK and PLB
86185: 05/06/22: User Core to PLB Bus example for Virtex 2P in EDK.
ns:
54420: 03/04/10: Re: Webpack 5.2 and Win98se
59311: 03/08/14: Re: Actel: Libero/Synplify "Run" button disabled
nshimizu:
76738: 04/12/09: Re: Spartan3 Block RAM from WebPACK
76789: 04/12/12: Re: Spartan3 Block RAM from WebPACK
<nshimizu_no_spam@bosei.cc.u-tokai.ac.jp>:
44351: 02/06/18: Re: [ANN] Free SFL to Verilog converter (with 6502/z80 core)
nshrestha:
92668: 05/12/03: Problem Timing Simulation CoolRunner II Design Kit
92816: 05/12/07: Problem programming CoolRunner II xc2c256_tq144 CPLD using IMPACT
93210: 05/12/15: Re: Parallel Cable III is not detected
nskri:
142378: 09/08/07: can't write to a bram module (verilog)
142386: 09/08/08: Re: can't write to a bram module (verilog)
142768: 09/08/31: Re: can't write to a bram module (verilog)
nsrsn:
117051: 07/03/22: Matrix inversion in FPGA
<nstrater@mcmail.com>:
7544: 97/09/20: Hacking bitstream formats
7562: 97/09/22: Re: Hacking bitstream formats
7603: 97/09/26: Re: Hacking bitstream formats
ntinsider:
53368: 03/03/12: Re: comp.arch.fpga : VCC shorted to GND within FPGA???
NTM:
21234: 00/03/12: Freeware Newsreader
<nubont@gmail.com>:
134261: 08/08/02: cpu,fpga, clock, dac, initialize sequence
null:
147774: 10/05/23: About CLB inter-slice communication in Virtex
151649: 11/04/30: Synplify compile points keep getting resynthesized
<null@I.Hate.Spam>:
12939: 98/11/05: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
12993: 98/11/10: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
nullandvoid:
24090: 00/07/26: Re: Variable shifting
24134: 00/07/27: Re: Variable shifting
Number Cruncher:
18414: 99/10/23: Re: ABEL for CPLD Design
18692: 99/11/08: LATTICE SEMICONDUCTOR INTRODUCES THE PLD OF ANALOG CHIPS
18693: 99/11/08: Re: Analog FPGA ?!
19565: 99/12/31: Design security
19574: 00/01/01: Re: Design security
19896: 00/01/16: Re: Benchmarks
20232: 00/02/01: Re: Lattice isp & FPGA
20950: 00/02/29: Recommended VHDL titles wanted ...
20973: 00/03/01: Re: Recommended VHDL titles wanted ...
Nurit Eliram:
39175: 02/02/03: DCM relationship question
39199: 02/02/04: Re: DCM relationship question
39214: 02/02/04: Terabit Networking Forum
39308: 02/02/05: Re: ClkEnable vs gated clock
42581: 02/04/28: fpga unpackaged dies
nurit eliram:
36763: 01/11/19: DLL cycle-to-cycle jitter
<Nurit.Eliram@mailandnews.com>:
37000: 01/11/28: Re: DLL cycle-to-cycle jitter
37044: 01/11/29: Re: DLL cycle-to-cycle jitter
nustartup:
45980: 02/08/13: Re: AES (rijndael) Ip core
nwreader:
143589: 09/10/16: Any interest in a group Xilinx FPGA board build/buy ??
143604: 09/10/17: Re: Any interest in a group Xilinx FPGA board build/buy ??
143611: 09/10/18: Re: Any interest in a group Xilinx FPGA board build/buy ??
143663: 09/10/20: Re: Any interest in a group Xilinx FPGA board build/buy ??
143678: 09/10/20: Re: Any interest in a group Xilinx FPGA board build/buy ??
143700: 09/10/21: Re: Teammates, interested?
nylander:
103870: 06/06/13: Does anyone have documentation for an insight DS-V2LC board
Nyoman Yani H:
59239: 03/08/12: Virtex: Foundation 3.1 Error
NZG:
125246: 07/10/18: Re: Quartus II 7.2 web edition - Linux or not?
ånønÿmøu§:
53454: 03/03/13: footprints
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