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I don't think ISA is going to be around much longer. Why bother. But to answer your question, no. But you can damage by driving an ISA output, or an ISA I/O while it is an output. "Ru-Chin Tsai" <m8931612@student.nsysu.edu.tw> wrote in message news:d22f039b.0209281203.769d7a99@posting.google.com... > I need to communicate FPGA with PC. PC transfer the testbench to FPGA. > FPGA response with the processing result to PC. I can choose PC ISA or > PCI interface. But I don't sure the I/O pins on PC ISA or PCI slot can > connect to FPGA without adding protection circuit machinism between > them. IF I do connection between FPGA and PC. Does any damage be > caused accidently. What is the safe interface FPGA device and PC slot?Article: 47576
For Layout, I found that I liked the Eagle for Windows free layout program. You can make boards up to a certain size, which is OK for a lot of stuff. Something like 3x4 inches? For FPGA, it depends on size. What is your first design going to be? "RCU" <nemesis@icequake.no_spam.net> wrote in message news:pan.2002.09.29.06.52.37.566023@icequake.no_spam.net... > > Hi, > > I read some of the previous posts of the topic, but wanted to get the > current opinion of the group. > > I want to get started with FPGA and microcontroller programming. I > purchased a CPS144 PICALL 3.42 kit from Amazon Electronics, and some 16F84 > chips. Along with the free picasm software, I think I am reasonably set > there. > > However, on the FPGA side, I am undecided as to what would be a good > starter kit. I have been playing with GNU Electric, which is a VHDL > simulator and compiler. I see that Altera has a ByteBlaster programming > cable that is reasonably flexible. I have also seen others recommend > Altera FLEX 6K series of chips. Is this a reasonable way to go? I am not > sure what to look for really, having taken a design class, but being > pretty much a complete newbie to the FPGA market otherwise. > > Some of the kits I have run across: > http://www.al-williams.com/pbx84.htm (Xilinx) > http://www.hvwtech.com/intro-fpga.htm (Altera Max) > > I am also looking into homebrew PCB layout. Press-N-Peel seems like a > good solution. Any other suggestions? > > Thanks for any insight.Article: 47577
One of the stupidest things about Altera Quartus S/W (at least the first versions, I don't know about later ones) was that hidden about 4 submenus down, was the setting for what to do with unused pins, the default choice; "As Outputs Driving Ground". What if you have the board made first, with the I/O in place, and want to add the various interface blocks of the design in incrementally? You can get some real hot chips. You must know about this setting, and find it and change it to "As Tri-State Inputs", and remember to do so with any design revisions, or your prototype is toast. I tried to tell Altera, but to no avail. The other problem was with their programmer window in Quartus. Everytime you burn a chip, it tells you your configuration has changed, and asks if you want to save it, when in fact, it hasn't. ================================================== > > The device on my the Altera board connects to external RAMs and other > > devices. > > > > If all unused pins were left as "outputs driving gnd", would it be a > > problem if an output pin of another device on the board connected to > > an APEX pin, which is also set as an output (and driving gnd) ? Since > > I'm not using the external RAM, I would consider such a pin as unused.Article: 47578
Does anyone have any detailed information about the size of xilinx fpga's over the years? I'm trying to do some research on what has and what will fit on an fpga? thanks MattArticle: 47579
The Altera Stratix and APEX families have PLL's that allow clock frequency synthesis. More details can be found in: http://www.altera.com/literature/an/an200.pdf (using PLL's with Stratix devices) http://www.altera.com/literature/an/an156.pdf (using GPLL's iwth APEX devices) http://www.altera.com/products/devices/stratix/features/stx-pll_features.htm l (Stratix clock management features) This functionality is accessed through the Megawizard Plug In manager. You can access this from the Quartus II Tools->Megawizard Plug In Manager. The ALTCLKLOCK Plug In is listed under I/O in the second panel. - DS "Dennis" <dennislwm@hotmail.net> wrote in message news:Xns9298C69F1BD3nobodydotcom@210.49.20.254... > Hi, > > How do I design a multiplier that outputs a signal 3x > that of the input clock signal? > > Background: > The clock signal is 100 Mhz and the design is to be > downloaded to an FPGA. > > Thanks. > > Dennis (dennislwm@hotmail.com) > > PS Reply to .com (not .net)Article: 47581
Does anyone have any detailed information about the size of altera fpga's over the years? I'm trying to do some research on what has and what will fit on an fpga? thanks MattArticle: 47582
> For Layout, I found that I liked the Eagle for Windows free > layout program. You can make boards up to a certain size, > which is OK for a lot of stuff. Something like 3x4 inches? What about the actual physical manufacturing of a board? I see lots of homebrew-available kits (Press N Peel, et al), and a few homebrewn methods: http://www.netcomuk.co.uk/~wwl/pcbs.html for example. > For FPGA, it depends on size. What is your first design > going to be? I have no idea. :) I thought it would be fun to implement a MIPS core or something similar. If that turns out to be too complex for the bits I can afford, then I might play with implementing old hardware anew, such as a portable Super NES, or something along those lines. I don't think anything I would want to do is anywhere near, say, a CPU produced even in the last 5 years. I just want flexibility for experimentation. If that makes any sense. Thanks!Article: 47583
Not sure if the new version of Chipscope has a faster trigger circuit, but there is nothing magical about the Chipscope trigger, so if you want a faster trigger, hardwire theirs inactive and design your own and bring it in the external trigger port. Regards, Jay "H.L" <alphaboran@yahoo.com> wrote in message news:<an6s70$oku$1@ulysses.noc.ntua.gr>... > Hello all, > > I use the Xilinx Chipscope 3.3 for monitoring the signals of my FPGAs. In > this version the ILA core generated has too many logic levels in the trigger > part thus the timing is not so good, is the same in the new version of the > Chipscope or are there any changes in the cores so to succeed better timing > without the need of floorplaning e.t.c? > > Greetings , > HarrisArticle: 47584
Ray, The one I've got now is in excess of 200MHz for the top frequencies. Don't forget it's not the toggle rate its the loading, distances and IR drop that kill speed. Ray Andraka wrote: > What are your speed requirements that FPGAs won't hit? Many ASIC apps are > achievable with a proper FPGA design (note that such a design is usually much > more heavily pipelined and is floorplanned, a direct port of your ASIC code is > going to be slow in an FPGA). Your density numbers are certainly high, and I > think well above the industry average. > > bulletdog7 wrote: > > >>Blackie, you are exactly right! (Please don't think I'm flaming you, >>its not intended) The ASICs I make though don't fit that category. To >>justify the cost, they are 4 to 10 clock domains, fully synchronous >>within each domain, but very asynchronous, dissimilar. Gate counts; >>well its rare to be under 1 million but they range from 500K to 10 >>million gates. Embedded risk processors, embedded rams and ROMs >>multiple large FIFOs and analog blocks; a variety of PHYs etc. are >>typical. Then you have the test circuitry to add even more timing >>complexity. Timing closure is not automatic, and, yes we earn the >>money, and the customers are usually very happy. because 10 million of >>these were still cheaper than 20 to 30 million FPGA's. that it would >>have taken for FPGA's assuming we could have reached the required speeds >>in an FPGA. >> >>Yes we use FPGA's too, mostly for prototyping and proof of concept. >>Yes for the smaller designs they have a very valid place in the >>business. But I haven't seen them hit the speeds we need with the >>density we need. Nor can they satisfy the gate counts required ... yet. >> >>Blackie Beard wrote: >> >> >>>I'm not sure about the first statement, since if I had a chip with >>>custom DSP, custom DPLL, and say, 50-100K gates, and 1 >>>clock, and I was going to sell 10 Million of them, and it only used >>>1 clock, why would I not make an ASIC? We shouldn't need to >>>break out the calculator to make my point. >>> >>>Also, the design should take into place the transition between >>>multiple domains, and force synchronization between them. >>>I suppose if you couldn't use FIFO bucket for data transfer >>>between two domains, then you'd have big timing concerns, >>>because depending upon a race condition not occuring would >>>be just plain old hokey. >>> >>>BB >>> >>>====================================================== >>> >>> >>> >>>>Anything complicated enough to make an ASIC out of would tend to have >>>>multiple clock domains, etc. It would tend to be synchronous within each >>>>domain, but if "timing closure is nearly automatic" were true then why >>>>do we at Tality get paid piles of dosh to do the layout for so many >>>>designs? >>>> >>>> >>>> >>> >>> > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > > >Article: 47585
The easiet way to do it, is to shift your signal 1 bit to the ledt and then add
it to the signal, it gives you 2+1=3 and it can easily be implemented inside a
FPGA at 100 MHz, a hardware multiplier is good if you want to multiply larger
values, but in your case, it is easier to make a simple multiplier yourself.
This the VHDL code I used to test it out:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all;
ENTITY test1 IS
PORT(
clk : IN std_logic;
dbus0 : IN std_logic_vector (15 DOWNTO 0);
reset : IN std_logic;
dout1 : OUT std_logic_vector (17 DOWNTO 0)
);
-- Declarations
END test1 ;
-- hds interface_end
ARCHITECTURE rtl OF test1 IS
signal dtemp1 : std_logic_vector(17 downto 0);
signal dtemp2 : std_logic_vector(17 downto 0);
BEGIN
process (clk, reset)
begin
if reset = '1' then
dtemp1 <= (others =>'0');
dtemp2 <= (others =>'0');
elsif clk'event and clk = '1' then
dtemp1(15 downto 0) <= dbus0;
dtemp2(16 downto 1) <= dbus0;
dout1 <= dtemp1 + dtemp2;
end if;
end process;
END rtl;
Leonardo reporter 122 MHz for Spartan II and , 120.1 MHz for Virtex, 130.1 MHz
on Virtex E and 206.0 MHz on a virtex 2.
For Altera, Acex 1k gave 69.2 MHz, 185.0 MHz for Apex 20C and 192.3 MHz on a
Apeck 20K.
The actual maximum frequency you can run, is normaly very different than these
values, and highly dependent on your system, number of bits etc.
Regards,
/Farhad
Dennis <dennislwm@hotmail.net> wrote:
>Hi,
>
>How do I design a multiplier that outputs a signal 3x
>that of the input clock signal?
>
>Background:
>The clock signal is 100 Mhz and the design is to be
>downloaded to an FPGA.
>
>Thanks.
>
>Dennis (dennislwm@hotmail.com)
>
>PS Reply to .com (not .net)
Article: 47586Blackie Beard wrote: > I've always wanted to, but never had a job doing (IC) layout, > so I wouldn't know about the big bucks you "back end" folks > make. Yessiree, I just get them vectors made and toss it over > the fence. I wouldn't mind working for a company that pays > the big bucks (I'm getting laid off on Thursday, yippee). In Sorry to hear that. Its been rough for too long. > any case, the quantities are high because the design is for > arc detector, which NEC has mandated to be in every > bedroom of every new home in the USA. Leviton and TI are > highly interested (quietly), and so is Boeing, Eaton, FAA and > Navy in the aerospace (400 Hz) field. Hendry's stealth > project I worked on had the best working technology in the > world, bar none, but ran out of money (probably not > because I make the big bucks). It's frustrating as hell to > see that happen. For more details about arc detection, > see UL1699. > > In any case, my personal belief is that certain things in > design can't be avoidable, such as multiple clock domains > caused by the necessity to have different frequency bases > for different communications interfaces (some freq for > RS232, some other freq for system, some other freq for > audio codec, etc). But there are design techniques to > avoid problems there. And what I don't agree with is that > we should nilly willy create extra clocks by inserting clock > delays so that some ripple counter output can be latched, > nor creating clock dividers using toggle flops. Absolutely agree with you there. We reuse and/or acquire a lot of junk sometimes. And I understand that point. Happens way too much. Maybe I should've reread the thread again. It just looked like you were pushing a single clock design only point and its just not reality. Maybe it's > OK if you _never_ plan on going to ASIC, though. That > point has been a very well driven nail by the previous > comments of others to this thread. And this has been a > very long and delightful thread, I must say. > > BB > ========================================= > >>bulletdog7 wrote: >> >> >>>Blackie, you are exactly right! (Please don't think I'm flaming you, >>>its not intended) The ASICs I make though don't fit that category. To >>>justify the cost, they are 4 to 10 clock domains, fully synchronous >>>within each domain, but very asynchronous, dissimilar. >>> > >Article: 47587
Interesting point, but very wrong. ISA may not be around long in standard PCs, but it is still very much in use in embedded computers and PC/104 systems. PC/104 is still on the upswing and will continue to be a viable market for many years to come. Blackie Beard wrote: > > I don't think ISA is going to be around much longer. > Why bother. But to answer your question, no. But > you can damage by driving an ISA output, or an ISA > I/O while it is an output. > > "Ru-Chin Tsai" <m8931612@student.nsysu.edu.tw> wrote in message > news:d22f039b.0209281203.769d7a99@posting.google.com... > > I need to communicate FPGA with PC. PC transfer the testbench to FPGA. > > FPGA response with the processing result to PC. I can choose PC ISA or > > PCI interface. But I don't sure the I/O pins on PC ISA or PCI slot can > > connect to FPGA without adding protection circuit machinism between > > them. IF I do connection between FPGA and PC. Does any damage be > > caused accidently. What is the safe interface FPGA device and PC slot? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47588
>Interesting point, but very wrong. ISA may not be around long in >standard PCs, but it is still very much in use in embedded computers and >PC/104 systems. PC/104 is still on the upswing and will continue to be >a viable market for many years to come. I thought PC/104 was PCI rather than ISA. What am I missing? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 47589
Hal Murray wrote: > > >Interesting point, but very wrong. ISA may not be around long in > >standard PCs, but it is still very much in use in embedded computers and > >PC/104 systems. PC/104 is still on the upswing and will continue to be > >a viable market for many years to come. > > I thought PC/104 was PCI rather than ISA. > > What am I missing? That is a very open ended question... ;) PC/104 is electrically ISA with lower current requirements on most pins. PC/104+ adds a second connector which is PCI electrically. I seem to recall that they leave off a few pins that are seldom if ever used, like JTAG, for example. There are a few PC/104+ CPU boards along with a couple of video boards. Everything else is just plain old PC/104 (mostly). -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47590
Well, you learn something everyday! Kewl. ================================= "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3D97C70E.8493B5EE@yahoo.com... > Interesting point, but very wrong. ISA may not be around long in > standard PCs, but it is still very much in use in embedded computers and > PC/104 systems. PC/104 is still on the upswing and will continue to be > a viable market for many years to come. > > > Blackie Beard wrote: > > > > I don't think ISA is going to be around much longer. > > Why bother. But to answer your question, no. ButArticle: 47591
For your own board manufacture, there was some Iron-on stuff that only works for traces over 20 mil., or so. Then there's them cool machines that use a router, my last company had that. But you can't do fine traces with that either. Better to just bite the bullet. There are prototype shops you can just email your gerbers to, 2-3 day turn, low quantity. For MIPS core, you aren't going to get that for free, me thinks! But you can sometimes buy a test chip for around $10-20, and build the SoC interconnects using an FPGA. You'll probably need at least 400K equiv gates. That won't be cheap either. Good luck, and reply if you find something interesting. "RCU" <nemesis@icequake.no_spam.net> wrote in message news:pan.2002.09.30.02.18.12.141498@icequake.no_spam.net... > > > For Layout, I found that I liked the Eagle for Windows free > > layout program. You can make boards up to a certain size, > > which is OK for a lot of stuff. Something like 3x4 inches? > > What about the actual physical manufacturing of a board? I see lots of > homebrew-available kits (Press N Peel, et al), and a few homebrewn > methods: > http://www.netcomuk.co.uk/~wwl/pcbs.html > > for example. > > > For FPGA, it depends on size. What is your first design > > going to be? > > I have no idea. :) I thought it would be fun to implement a MIPS core or > something similar. If that turns out to be too complex for the bits I can > afford, then I might play with implementing old hardware anew, such as a > portable Super NES, or something along those lines. > > I don't think anything I would want to do is anywhere near, say, a CPU > produced even in the last 5 years. I just want flexibility for > experimentation. If that makes any sense. > > Thanks! >Article: 47592
I have a MC68VZ328 system interfacet to a Acex 1K30 device, i have a doubt, the processor are a 32bit but the system bus are 16bit, i want to include the a core int the FPGA for ide interface, but the whisbone slave core for ide have 32bit registers, and SEL_i need to be 1111 32bit data, it's posible to cahnge the master controler to drive this 32 bit data from he 16 bit bus of the system¿? Any help will be apreciated.Article: 47594
Dear All,
Any way to implement a fast 128 to 1 multiplexer with VHDL?
Moky
Article: 47595You need to optimize a 128 to 1 mux targetting for optimal timing. I guess you can make it to 5ns in a 0.35 CSM process... Qijun. "Moky" <plmok@ee.cityu.edu.hk> wrote in message news:an9b9g$9g1@news.cityu.edu.hk... > Dear All, > > Any way to implement a fast 128 to 1 multiplexer with VHDL? > > Moky > >Article: 47596
Is your homework getting too tough already? "Moky" <plmok@ee.cityu.edu.hk> wrote in message news:an9b9g$9g1@news.cityu.edu.hk... > Dear All, > > Any way to implement a fast 128 to 1 multiplexer with VHDL? > > Moky > >Article: 47597
If you use Quartus's native link feature for Leo, have a look in the ls_work\*.log file from Leo directly, maybe this helps. I sometime had the problem, that the *.vwf file got into Leo's file list and created an error. Ralph Michael Tornow <turmick@gmx.net> wrote in message news:<Xns929664D94DC2Bmichaeltornowgmxnet@130.133.1.4>... > Sometimes I get an error box "Full compilation was cancelled due to an > error" while compiling a design written in vhdl with Quartus 2 v2.1 (appers > on lower version aswell), but there is no error in the Message window. > It appears during the logic synthesizer is running. > I have checked this vhdl code with Leonardo Spectrum too. No errors were > found. But aslong I use LPM-functions with black boxes Quartus is running > the logic synthesizer aswell. > I'm compiling designs for 20K1500E and ARM-based Excalibur EPXA10. > For compilation I use an P4 with 1GB RAM so hardware shouldn'd be the > Problem, am I rigth? > Does anyone have an idea? > > thanks > > Michael TornowArticle: 47598
I am using synplify for a test. That is the log file of it. I am not sure what does the System Line mean? Can any body give me a hand? Thanks in advance. Requested Estimated Requested Estimated Clock Starting Clock Frequency Frequency Period Period Slack Type ---------------------------------------------------------------------------------------------- Clk 200.0 MHz 192.1 MHz 5.000 5.205 -0.205 inferred System 200.0 MHz 816.3 MHz 5.000 1.225 3.775 system ============================================================================================== -- Ensoul Chee <mpub@163.com> MSN : <mpub@163.com> ICQ : 135925467Article: 47599
I'd have though a better question would be: Any way to implement a fast 128 to 1 multiplexer for a ______ device. Also a definition of fast - data rate or latency? Can you pipeline the mux over several stages? Are you building it out of transistors or LUTs/FFs etc. --- cds Moky (plmok@ee.cityu.edu.hk) wrote: : Dear All, : Any way to implement a fast 128 to 1 multiplexer with VHDL? : Moky
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Compare FPGA features and resources
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