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"Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in message news:<3d9a0049$0$8514$cc9e4d1f@news.dial.pipex.com>... > www.opencores.com is a brilliant place to bookmark. They even have a USB2 > core :) Paul ! How could you ?! You beat me to it ! Thats my line ! ;*) BTW, you will need an external single chip PHY with the OpenCores USB 2.0 IP core. Check out Agere(sic?) and SMCS web sites for PHYs. The USB 2.0 core is currently being tested by another customer of mine with an Spartan 2e ... Best Regards, rudi ---------------------------------------------- www.asics.ws - Solutions for your ASIC needs - > "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message > news:anctr2$2brl$1@msunews.cl.msu.edu... > > Hello, > > I am developing an instrument that is currently communicating over a > > special high speed parallel board. The data rate is 6.4 million 8 bit > words > > per second. The board works great but it costs in excess of $1600 US per > > copy. It also occupies a full sized PCI slot. We are considering > > implementing an alternative I/O arrangement such as USB2 or ethernet > > (TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some > > other FPGA friendly technology? Note: target FPGA is a Spartan2E (or if > > absolutely necessary, Virtex2). > > > > Thanks, > > Theron > > > >Article: 47676
Hi again RCU, > > Possibly you could consider the B5-X300 board, with Xilinx > > XC2S300E FPGA, from BurchED to get you started > > http://www.burched.biz/b5x300.html > > You've got me drooling. I wish I could afford it. (student here) > I hear you, RCU, re affordability (oh, and thanks for the kind comment too:) ). We've really tried hard on pricing to make all of our units affordable for students, self-learners, and development labs. > > The XC2S300E FPGA is more-than large enough > > to implement a MIPS core, and many other CPU cores. > > Some free or open source cores that are > > available on the web include 8051, PIC, 68HC11, > > Z80, 6502. Opencores has some microprocessor projects > > http://www.opencores.org/projects/ > > Do you have anything maybe a bit smaller at around half the price? I > just can't drop that much cash right now, as much as I'd like to. > We really wish that we could offer the same units at at a lower price, but, as mentioned above, we've tried hard to keep the pricing as low as possible. Especially with the 10% discount this week. However, we wouldn't really want to offer a smaller version, at least at this stage. 300K gates is alot, and opens up great possibilities for projects. It is also the largest device that is supported by the free WebPACK software. Support in the free WebPACK software was really important for us. It is fairly ceratin that cost of the "pay-for" tools would break the budgets of most students, beginners, and self-learners. Incidentally, the free WebPACK tools are very excellent and powerful, thanks to Xilinx. And thanks to Xilinx, Altera, Atmel and other programmable logic vendors, we are in a "golden age of gates", and it is only getting better. You only have to look back a couple of years, when discussing FPGAs with colleagues and friends, the mention of 300K gates would result in much excited exclamations and jaw-dropping:) To have this kind of device on a board, at this price, has seemed like a distant dream for many, but now it is here! (You can tell I am excited by the technlology:) ). > > There is a great book called "Rapid Prototyping > > of Digital Systems - a Tutorial Approach", by > > Thanks for that mention! I will check it out. > > > Hope that helps:) Above all, enjoy and have fun! > > Will do. Thanks for the reply. > You're welcome:) Best regards Tony Burch http://www.BurchED.biz FPGA boards for System-On-Chip prototyping and education * * 10% off the normal price of all products, sale now on * *Article: 47677
I am desperately looking for someone who is an expert on the AMD9513. We have a purchased ISA timer counter board that we are trying to run via VxWorks. What we need to do is change the frequency every 1ms for a period of time. Actually the counter chip isn't the AMD9513, it is another mfg who has emulated the AMD9513, CTS9513-2 is the chip number. We are currently running the board in 8 bit mode and the counters are running in mode D. Sometimes it works and other times it seems as if some bogus value gets written into the data register, yielding an undesirable frequency. We have hooked up a data analyzer to one of the 9513 chips and it appears as if everything on the bus is good. I'm looking for somebody that knows the intricacies of this chip. The data sheet we have is lousy and we think that we might be writing to the load register incorrectly, or at a time when the counter is fetching from it, which might be causing an unstable state. We are not even sure that we are correctly programming the counter either, although we do see our algorithm work at times. Appreciate any help. RobArticle: 47678
On Tue, 01 Oct 2002 16:19:22 -0000, hmurray@suespammers.org (Hal Murray) wrote: >[suggest software] >> iam not looking for such a solution TCP/IP in hardware is it feasible > >Look at the source code for a TCP stack. It's a huge state machine. >Just take a page or two of code and try to convert that to hardware. > >I haven't seen any reports of doing TCP in hardware, but I could >easily have missed something. (But somebody would probably mention >it here.) > Three different companies I know of are shipping TCP/IP in hardware. And I know of two more that developed product, but never shipped it. Do a search for iReady. Theirs is the most commercially available. >As an example, consider just routing, a small part of the TCP/IP stack. >High end routers do some of the table lookup in hardware, but they >normally drop back to software for the hard/rare cases.Article: 47679
Brett Cline wrote:
> Hi All-
>
> Synthesis from a C/C++ algorithm is absolutely possible and has been in
> use for some time. Even "plain vanilla C" algorithms can be used with the
> right synthesis product.
Show me. Nothing I've seen can handle C code that was not specifically written
to create hardware. I think your next sentence probably validates that as
well. Plain vanilla C has nothing in it to support concurrency, and I know of
no product that can infer that concurrency from existing (not written
specifically to map to hardware, usually using special extensions) code.
> Obviously it does take some amount of hardware
> knowledge to get reasonable hardware out the backend. All that should be
> required is to add the hardware interface structure to the C/C++ algorithm.
> For that we recommend using SystemC (there is a reference implementation
> available under an open source license at www.SystemC.org). SystemC provides
> the necessary abstraction in C++ to add concurrency, bit accuracy, and other
> hardware-isms to the C/C++ algorithm.
>
> To take the algorithm to hardware (RTL Verilog or VHDL) my company offers
> a product called "Cynthesizer" for high-level synthesis from SystemC. We've
> had a number of customers take generic algorithms (some even from the web)
> such as filters, encryption, multimedia, etc. and convert them directly to
> RTL Verilog and VHDL. The resulting RTL can be put into any FPGA or ASIC
> synthesis tool as well as any other tool that operates on RTL.
But at what price? Is the performance and density reasonably close to a what a
skilled hardware designer can accomplish?
>
>
> For more information check out our web site at www.ForteDS.com or feel free
> to email me directly.
>
> Best regards,
> Brett
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3D894809.ECF33E30@andraka.com...
> > Not exactly. There are several vendors that have C to hardware
> compilers,
> > but don't expect to take plain vanilla C and compile it directly to
> hardware.
> > For the most part, these tools use subsets and extensions to C to permit
> > description of hardware and all the parallelism that implies in a C-like
> > environment. It raises the level of abstraction, and as a result you tend
> to
> > get a design that is more bloated and slower than one done closer to the
> > hardware. The point is that there is no free lunch, there is a
> considerable
> > engineering effort to convert your software to something that will run at
> a
> > reasonable speed in an FPGA that you can afford to buy.
> >
> > mike wrote:
> >
> > > I can't claim to be an expert, but what I think you want to do isn't
> > > going to work. You can't take any arbitrary C/C++ program and convert
> it
> > > into VHDL code that will run on an FPGA. For making something like a
> > > hardware mp3 player, you may want to look at something like a
> > > programmable DSP board. Also, you should check on what, if any, analog
> > > outputs are avilable from the FPGA you're using. For example, on the
> > > Altera student board, the only analog output is for a VGA monitor, so if
> > > you wanted to make an mp3 player using one you'd need to build an
> > > interface to convert the decoded digital audio into analog audio.
> > > Mike
> > >
> > > On Tue, 17 Sep 2002 09:27:21 +0000, DJohn wrote:
> > >
> > > > Hi all VHDL experts,
> > > > Is there any tools which can convert a C\C++ source file to VHDL .
> For
> > > > example If I have a C source code for a MP3 decoder , Can any tool can
> > > > convert it into VHDL equivalent. There is some facility in FPGA
> > > > Advantage to generate a wrapper VHDL for a C File , what exactly is
> > > > that ? Does that mean I can synthesize a C\C++ file by creating a VHDL
> > > > Wrapper. Please help
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47680russelmann@hotmail.com (Rudolf Usselmann) writes: > The USB 2.0 core is currently being tested by another customer of > mine with an Spartan 2e ... How many LUTs does the USB 2.0 core require?Article: 47681
"Jamie Morken" <jmorken@shaw.ca> writes: > I would like to implement a high speed 12 bit ADC and a high speed 12 bit > DAC using the 200Kgate Spartan IIE device. [...] > What would the maximum sampling rate be for the ADC and the DAC using the > maximum clock speed for the FPGA? > Is there any chance of the sampling rate being 40MSPS at 12 bits? I'm not an expert, but I don't think it's likely. 40 MSPS 12 bit A/D was the bleeding edge for dedicated silicon not too long ago. Now you can get 200 MSPS 12 bit A/D, but it doesn't come cheap. I haven't seen any 12-bit Sigma-Delta ADCs faster than 3 MSPS, but perhaps some exist.Article: 47682
Hi, > I haven't seen any 12-bit Sigma-Delta ADCs faster than 3 MSPS, but perhaps > some exist. Is there another type of ADC that could be implemented in an FPGA other than sigma-delta that would be faster (say 20MSPS) and still have 12 bits resolution? cheers, Jamie MorkenArticle: 47683
Anything faster than a sigma-delta would probably require a resistor-ladder DAC so couldn't be contained in an FPGA. -Kevin "Jamie Morken" <jmorken@shaw.ca> wrote in message news:1Kvm9.437802$v53.19792636@news3.calgary.shaw.ca... > Hi, > > > I haven't seen any 12-bit Sigma-Delta ADCs faster than 3 MSPS, but perhaps > > some exist. > > Is there another type of ADC that could be implemented in an FPGA other than > sigma-delta > that would be faster (say 20MSPS) and still have 12 bits resolution? > > cheers, > Jamie Morken > >Article: 47684
Mea Culpa. Looks like I read the Xilinx Handbook too fast. Thanks Ray for the correction. Dali Ray Andraka wrote: > Bad information. You certainly can run a clock in on a regular I/O pin. > Instantiate an IBUF at the pin and feed that to a BUFG. I don't think the tools > will automatically infer the BUFG in this case, but instantiation gets around it > just fine. The main thing to note is that your clock will not have the controlled > pin to BUFG delay it had with the IBUFG so if your clock relationship with other > I/O pins is critical you need to be careful (and use a CLKDLL). > > Dali wrote: > > >>It doesn't work that way. In order to take advantage of the clock tree >>brovided by the BUFG primitive you need to use an IBUFG instead of an >>IBUF. So a normal IO pins does not do the job. >> >>For further details, look at the Xilinx Handbook. >> >>Dali >> >>Ho Wong wrote: >> >>>Hello. I'm using a pin to drive a process but the thing is that it's already >>>been soldered onto a normal IO pin. I've been trawling through past posts >>>and newsgroups and I still haven't found a answer yet. I'm just a beginner >>>to fpgas so i'm not very familiar with the low level logics. I tried doing >>>PIN -> IBUF -> BUFG -> signal, but it told me the input pad net of PIN has >>>illegal connection Would it be possible to short my normal IO to one of the >>>dedicated I,GCK ? I'm using a Spartan 2 programming in VHDL with the ISE >>>Webpack. >>> >>> >> > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 47685
Jamie Morken wrote: > > Hi, > > > I haven't seen any 12-bit Sigma-Delta ADCs faster than 3 MSPS, but perhaps > > some exist. > > Is there another type of ADC that could be implemented in an FPGA other than > sigma-delta > that would be faster (say 20MSPS) and still have 12 bits resolution? > > cheers, > Jamie Morken Sigma-Delta ADC's are fundamentally bit-serial integrators. Being integrators, they are extremely component-spread tolerant. You can use maths summation filters to effectively oversample, and so increase the apparent sample rate, but there is no free lunch - you loose step response, and so find that values depend on those that came before. To get 12 bits with a Bit-serial integrator, at 20MSPS, gives a virtual clock of 20 x 4096, or 81GHz (!). Also, consider jitter of 100ps -> one part in 500, or appx 9 bits, so you need 10ps region for 12 bits. Other ADC topologies are Successive approximation, and FLASH. Both use high performance comparitor(s), and increasing component precision, to give better numbers at lower clock rates. FPGAs have no precision analog numbers, so you will need external analog blocks to achieve 20Msps There may be scope for using some simple analog precision ( eg 1% resistors, multiple outputs ) to simplify SD-ADCs, ( just as they can simplify DACs ), but I have not seen info on this. viz For a DAC, you can use two 6 bit DACS, and a 64:1 summing junction ( two good tolerance resistors ), to give 12 bit DAC, but with 6 bit clock rates. DPLLs in FPGAs could give interesting scope for finer time-definition. -jgArticle: 47686
Peter Alfke wrote: > Altera was never prohibited from calling their devices "FPGA". Others did it, > Actel and Quicklogic come to mind. The acronym never was protected by any > copyright > What stopped Altera from using this appropriate name is not such a mystery: > > During the time of the lawsuit between Altera and Xilinx, Altera wanted to > emphasize that their LUT-based devices were not really just a copy of Xilinx > FPGAs. Any little bit of nomenclature juggling was used to help the cause. Now > that the lawsuit is over, Altera can use common sense and call their devices > FPGAs. That must be scaling new heights of legal paranoia since I can remember seeing parts called `Field Programmable Gate Arrays' in one of the TI "orange" TTL data books (vol 3 I think) a long time before Xilinx was born. Did anyone ever use them ? Maybe no one at Altera dated from the TTL era so they didn't know ...Article: 47687
> -----Original Message----- > From: Robert S. Sierk [mailto:rss@appcongroup.com] > Subject: AMD9513 Timer Chip > I am desperately looking for someone who is an expert on the > AMD9513 [...] > I'm looking for somebody that knows the intricacies of this > chip. The data sheet we have is lousy [...] When I worked for AMD for a short spell in the late 80s, the FAEs there were forever tearing their hair out a) trying to understand the 9513 b) trying to help customers understand it c) working around the bugs in it So it's not impossible you've stumbled on a bug. If your data sheet is lousy, I wonder if it's worth trying to find any of the original AMD appnotes and data sheets? They were usually pretty well written. And it might be of interest for you to know that a certain well-known and somewhat senior Xilinx HQ apps engineer, who has been known to post here, was with AMD for a while too :-) Sorry I can't help you myself. When I get back home this weekend I'll trawl through the paper databook archives and see if I can find anything interesting, if you haven't got an answer by then. -- Jonathan Bromley HDL Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project = Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 = 1AW, UK Tel: +44 (0)1425 471223 mail: = jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: = http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. = reserves all rights of privilege in respect thereof. It is intended for the use = of the addressee only. If you are not the intended recipient please delete = it from your system, any use, disclosure, or copying of this document = is unauthorised. The contents of this message may contain personal views = which are not the views of Doulos Ltd., unless specifically stated.Article: 47688
Peter Alfke wrote: > > > On paper, PLLs have advantages. In reality the more robust DLL beats a > PLL in most respects. > > About the only real advantages of PLLs are clock multiplication and clock/data recovery from a modulated data stream. For the first of these the V-II DCM can now do values other than x2 in frequency synth mode but the jitter can be fierce depending on the M/D ratios. For the second of these there's nothing to be done, at least not directly, a shame since it means I can't put a whole Ethernet conroller inside an FPGA. O.k. I could use the 4-phase trick for 10 Mb/sec. but that won't cope with 100Mb.Article: 47689
Hi Cisa, Why do you think that it doesn't work? Are you monitoring some pins against some expected values? You could do a simple 'debug' design to see if your design is not held on reset all the time and that is why your FFs are not doing what they are supposed to do. I would suggest to create a new design, with an input clock, some simple inputs (jumpers or something easy to drive) and then combinational outputs and synchronous outputs. If the combinational outputs are doing th right thing (just invert an input) then your image is in :o), if the registerd outputs are not doing the right thing (like a synchronous inverter) then your chip is held on reset or your clock is not there (assuming no CE is used). If your chip is held on reset you could bring out that signal to a test point to see what it does. If your reset is low all the time, I don't know, it could be at synthesis level (did you check if you get FD and FDP type FFs, I don't know if this makes any difference anyway). During the build process I always use the default configuration options in ISE (STARTUP section) -> Done (C4), Enable Outputs (C5), Release Set/Reset (C6), Release Write Enable (C6), Release DLL (No Wait) and I don't instantiate the STARTUP block at all in my code. I hope it helps, good luck :o) Regards Ulises Hernandez Design Enginner ECS Technology Ltd. www.ecs-tech.com "Cisa" <jjyy@hotmail.com> wrote in message news:ee794a2.1@WebX.sUN8CHnE... > Thanks. > I don't remove the cclk after configuration completes,so it should have enough cclks. > I use a programmer to download my design into EPROM,and use selectMAP > slave mode to configure from EPROM > in PCB board.I have also noticed that after configuration cs signal of the FPGA is low.Is it irrelevant > for FPGA to start?What's wrong with > my configuration?Help,Pls. >Article: 47690
Hmm.. I'm looking at the timing diagram for the Block Ram and I've got a question about the clock timing. Data sheets say that for single port ram, the maximum time for the clock to go high or low is 1.9ns.. which i find very fast. That's 263MHz 50%duty... i'm not sure if my external chip can even go that fast... So do i have to obey these restrictions to clock my ram? Would it fry and die if i clocked my ram whenever i felt like it so long as i obey the minimum time before sampling restrictions?(1.4-2.8ns) eg. I set my inputs (address, data, we etc..) then a second later decide to sample these and write to my ram. then decide to turn the clock back low and hour later.?Article: 47691
Austin Lesea ha scritto nel messaggio <3D9A2F6A.56F92F06@xilinx.com>... >TANSTAAFL: > >(There ain't no such thing as a free lunch*). > >Austin > >*Robert Heinlein's classic SF novel "The Moon is a Harsh Mistress" > Dear Austin, IMHO, an FPGA development tool is not a lunch. It is only the knife and the fork indispensable to eat the FPGAs. LuigiArticle: 47692
hombecker1962@hotmail.com (Dan) writes: > I have a quick question. We are looking to get a new computer to > simulate Virtex II pro (1 power pc processor). I was curious as to > recommendations. I see they recommend 2-3 gigs of ram for this > particular device. Does anyone out there know if Xilinx ISE 5.1 runs > faster on dual processor SMP machines that are mainly dedicated to The Xilinx software does not support multiple threads (I would like to be proven wrong on that one). Under Solaris you can run multiple PAR iterations on multiple machines or as multiple processes on a SMP (or a combination of the two). I thought that Windows only gives you two gigs¹ per process so getting more memory will not help you much. Does Modelsim provide a SWIFT interface to be able to simulate the powerpc SWIFT model under Windows? Does any Windows based simulators support SWIFT? If not you are better off getting a 64-bit SUN with a SWIFT compatible simulator like VCS. Petter ¹except for a special/expensive version of NT where you get three gigs for your process -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 47693
I didn't read it properly ^^;;;;;; Hmm... can't seem to delete the post..... "Ho Wong" <s354411@student.uq.edu.au> wrote in message news:aned57$2ai$1@bunyip.cc.uq.edu.au... > Hmm.. I'm looking at the timing diagram for the Block Ram and I've got a > question about the clock timing. Data sheets say that for single port ram, > the maximum time for the clock to go high or low is 1.9ns.. which i find > very fast. That's 263MHz 50%duty... i'm not sure if my external chip can > even go that fast... So do i have to obey these restrictions to clock my > ram? Would it fry and die if i clocked my ram whenever i felt like it so > long as i obey the minimum time before sampling restrictions?(1.4-2.8ns) > eg. I set my inputs (address, data, we etc..) then a second later decide to > sample these and write to my ram. then decide to turn the clock back low and > hour later.? > >Article: 47694
Peter Alfke (peter@xilinx.com) wrote: Peter, Thanks for adding another meaning to my understanding of the word 'Fast' - it seems the more meanings a word gets, the more meaningless it becomes ;-) --- cds : There are two aspects to "fast": : data throughput, and speed of change on the select input. : I can build a 128-input 200 MHz mux in just four or five CLBs, but it : might take many microseconds to change it, using partial reconfiguration. : Might not be useful in all cases, but is good for some... : Peter Alfke, Xilinx Applications : ========================================= : Christopher Saunter wrote: : > I'd have though a better question would be: : > Any way to implement a fast 128 to 1 multiplexer for a ______ : > device. : > : > Also a definition of fast - data rate or latency? Can you pipeline the : > mux over several stages? Are you building it out of transistors or : > LUTs/FFs etc. : > : > --- : > : > cds : > : > Moky (plmok@ee.cityu.edu.hk) wrote: : > : Dear All, : > : > : Any way to implement a fast 128 to 1 multiplexer with VHDL? : > : > : MokyArticle: 47695
Jan Gray <jsgray@acm.org> wrote: > In my review of the 5.1i materials, I have just come across the RPM_GRID > notion, and this app note, written by Mr. Wade: RPM_GRID was possible in Virtex-II in 4.2i also. Is it supported in Virtex-E now? Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 47696
Dan <hombecker1962@hotmail.com> wrote: > I have a quick question. We are looking to get a new computer to > simulate Virtex II pro (1 power pc processor). I was curious as to > recommendations. I see they recommend 2-3 gigs of ram for this > particular device. Does anyone out there know if Xilinx ISE 5.1 runs > faster on dual processor SMP machines that are mainly dedicated to > that task (i.o.w. does it use multiple threads)? If so do you suggest The tools themselves won't use multiple CPUs, but a second CPU is useful for other stuff; screen updates, disk I/O, run TRCE/Floorplanner/etc while routing (if you have enough RAM etc). Or Run VNC to connect while routing (VNC is a bit of a CPU hog in my experience.) > P4 ? AMD XP+? I would think the large cache on the 2.8 GHz P4's would > be a big advantage. Also RAMBUS is sort of expensive compared to DDR, > is it worth the 2-3x increase in price ? We will probably go with 3 The best route machine I have is dual P-III 866 MHz with 2Gb of SDRAM, so I can't really comment. Haven't tried AMD yet for routes but planning to. By the way, from what I hear, Windows applications can't use more than 2Gb anyway. If your route needs more, it will crash. So 3Gb of RAM might not be worth it, unless you will run other memory-intensive tasks at the same time as PAR. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 47697
Dali <dadicool@ifrance.com> wrote: > From previous experience with the xilinx tools at my compagny, if you > delete the files generated by the place&route tool when you want to > rerun the flow, it makes the P&R faster and gives better results. This > is due to the P&R tool taking old files as a "reference", just like > reentrant routing. It only does this if you tell it to. (Maybe the GUI behaves differently; use the command line if so.) Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 47698
Georg Acher <acher@in.tum.de> wrote: > That is maybe related to the (sorry Xilinx) crappy installer which runs under > Java. I always had problems with it (even under Solaris). I have made my own > installation script by directly calling the installer-class, much faster than > the GUI: http://wwwbode.cs.tum.edu/~acher/xilinx/ > > I will never understand why an installation needs Java, since a simple .tar.gz > (like in the early days of Xact) is much faster and user friendly than the > current colorful, Valium-installation. No disagreement from me there. I assumed it was a Java problem. Thanks, I'll try your method. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 47699
AcroDesign Technologies has announced results from its work on an embedded processor for the Tcl language. More information, and a recent presentation is available at: http://www.gmvhdl.com/acrodesign/research.html#tob --Scott Thibault AcroDesign Technologies
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