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Messages from 49050

Article: 49050
Subject: Re: Concepts: What is "Clock Edge"?
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Wed, 30 Oct 2002 22:37:56 +0000 (UTC)
Links: << >>  << T >>  << A >>
VirtualSean <VirtualSean@fastdial.net> wrote:
: <insert neophyte question>

: What is "clock edge"??? Anyone care to take a moment to enlighten the unwashed?

The moment when clock changes from 0 to 1  (leading edge) or from 1 to 0
(trailing edge). 

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 49051
Subject: How important is simulation?
From: joefrese@hotmail.com (Joe Frese)
Date: 30 Oct 2002 14:40:07 -0800
Links: << >>  << T >>  << A >>
First off, thanks to all who responded to my last post, re: FPGA
fullness.  Your comments and suggestions were incredibly helpful.

We recently purchased Active-HDL 5.1XE, and in experimenting with it,
I discovered an FPGA design that does not simulate (post
place-and-route) correctly . . . which is strange, as the design has
been tested and verified as operating correctly in actual hardware. 
Digging a little deeper, I was able to identify a number of constructs
in the design that cause problems in simulation, but should NOT cause
problems in real hardware.

Now, I could fix these areas so that the design simulates correctly,
but the problem constructs are sprinkled heavily throughout, so to do
so would be no small undertaking.  My question is, therefore: how
important is it to have a completely clean simulation?  Is it
important enough to renovate a working and tested design?  Thanks in
advance for your input.

Joe Frese

Article: 49052
Subject: Re: GlobalReset hogging routing resources
From: Ray Andraka <ray@andraka.com>
Date: Wed, 30 Oct 2002 22:50:23 GMT
Links: << >>  << T >>  << A >>
Assuming that you mean the dedicated global reset network, not a BUFG, then the problem may be that you have one or more flip-flops somewhere in your design that do not use the global reset.  You also need to use the startup block to get the input signal onto the GSR net.

FPGA admirer wrote:

> Hello all, hopefully you can help me with some idea as to what is causing my problem.  Instead of the GSR being distributed on a global buffer, the GSR input is being sent to a CLB then from that CLB being sent to every other CLB in the design that uses Global Reset.  This is causing extremely high fanout for this signal and I believ consuming massively unneeded routing requirements.  I did not notice this problem till I saw the hgih fanout in the floorplanner and checked the design in the FPGA editor, and wow! this signal is all over the chip in nearly every CLB but not on a global net.
>
> During synthesis I receive this warning:
>
> Warning: No global set/reset (GSR) net could be used in the design becuase the design contains the unlinked cell '/ver7-Optimized/AWGFIFOIntergace/AddressCounterRAM'
>
> The RAM referred to was generated using Logiblox, although I do not understand what the unlinked cell means.  The RAM is being used by the design and doesn't seem to be optimized out from my observation.
>
> I have specified an input pad on the chip as GlobalReset.  This signal is instantiated onto the GSR input of the STARTUP block.  I then pass the GlobalReset signal onto each of my VHDL modules.  Am I supposed to pass the GSR signal instead of the GlobalReset?  I have two clock buffers in use that are not giving me this error and there are global/clock buffers still available.
>
> Thanks for any help!

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 49053
Subject: Re: Concepts: What is "Clock Edge"?
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 30 Oct 2002 15:03:53 -0800
Links: << >>  << T >>  << A >>
In a digital system, it is the clock that orchestrates or controls the sequence of
events ( like the conductor controlling an orchestra). The clock is itself a
digital signal that is either High or Low. In most system only one clock
transition ( "edge") really matters, in many cases it is the rising edge, the
transition from Low to High, but it might also be the opposite, from High to Low,
and in some modern systems both edges cause an action.
When you stomp your feet to the music, it is the falling edge of your foot
movement that signals the beat.
Enough analogies?

Peter Alfke
===============
Virtual Sean wrote:

> <insert neophyte question>
>
> What is "clock edge"??? Anyone care to take a moment to enlighten the unwashed?
>
> Thanks much.
>
> --
> VirtualSean


Article: 49054
Subject: Re: How important is simulation?
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Wed, 30 Oct 2002 16:24:30 -0800
Links: << >>  << T >>  << A >>
Joe Frese wrote:

>
> My question is, therefore: how
> important is it to have a completely clean simulation? 


For a synchronous design, passing static timing is the
essential requirement.

> Is it important enough to renovate a working and tested design?


If asynchronous sections are causing the problem,
a design change is indicated.

If this is an HDL design consider syncing things up
and simulating the code rather than gates -- it's much quicker.

     -- Mike Treseler


Article: 49055
Subject: Re: How important is simulation?
From: "Steve Casselman" <sc@vcc.com>
Date: Thu, 31 Oct 2002 01:00:09 GMT
Links: << >>  << T >>  << A >>
Simulations are worse case. So your design may work at 3.3v and room temps
but fail under other conditions.


Steve


"Joe Frese" <joefrese@hotmail.com> wrote in message
news:c176b8c2.0210301440.4b91e39f@posting.google.com...
> First off, thanks to all who responded to my last post, re: FPGA
> fullness.  Your comments and suggestions were incredibly helpful.
>
> We recently purchased Active-HDL 5.1XE, and in experimenting with it,
> I discovered an FPGA design that does not simulate (post
> place-and-route) correctly . . . which is strange, as the design has
> been tested and verified as operating correctly in actual hardware.
> Digging a little deeper, I was able to identify a number of constructs
> in the design that cause problems in simulation, but should NOT cause
> problems in real hardware.
>
> Now, I could fix these areas so that the design simulates correctly,
> but the problem constructs are sprinkled heavily throughout, so to do
> so would be no small undertaking.  My question is, therefore: how
> important is it to have a completely clean simulation?  Is it
> important enough to renovate a working and tested design?  Thanks in
> advance for your input.
>
> Joe Frese



Article: 49056
Subject: Re: Information--conference paper
From: "Steve Casselman" <sc@vcc.com>
Date: Thu, 31 Oct 2002 01:03:32 GMT
Links: << >>  << T >>  << A >>
 EXTENDED SUBMISSION DEADLINE: Monday, November 4th 2002


  The 10th Reconfigurable Architectures Workshop (RAW 2003)

                NICE, France, April 22, 2003

             http://www.ece.lsu.edu/vaidy/raw03/

 This year the main Focus covers
 Run-Time & Dynamic Reconfiguration:
      foundations, algorithms, architectures, SoC,
      devices, technologies, tools, applications
 and many other topics.




"Stelios Zontos" <zontos@telecom.ntua.gr> wrote in message
news:aplo1b$91b$1@ulysses.noc.ntua.gr...
> Dear all,
>
> me and my partners have designed and successfully implemented the
electronic
> part of a WDM ring node (Burst Mode Rx/Tx, data storage, MAC protocol).
The
> electronic part consists of two boards and many FPGAs. We tested our
> equipment and we are now interested to present our work to a
> conference/journal. Can somebody give me information on some conferences
and
> on the content of the paper? It is the first time we like to edit a paper
on
> hardware implementation :)
>
> Thanks in advance
> H.
>
>
>



Article: 49057
Subject: Re: How important is simulation?
From: nospam <nospam@please.com>
Date: Thu, 31 Oct 2002 04:10:18 +0000
Links: << >>  << T >>  << A >>
joefrese@hotmail.com (Joe Frese) wrote:

>Digging a little deeper, I was able to identify a number of constructs
>in the design that cause problems in simulation, but should NOT cause
>problems in real hardware.

Maybe you should describe one of these 'constructs'. The only allowable
simulation failures I can think of are setup/hold violations on latches
used to synchronise asynchronous signals. 

I don't see a design having too many of those or that you could 'renovate'
the design to avoid them. 

>Is it important enough to renovate a working and tested design? 

Depends if you want it to work in the next chip you buy :).



Article: 49058
Subject: Re: From NCD to Bitstream (Xilinx FPGA)
From: Utku Ozcan <utku.ozcan@netas.com.tr>
Date: Thu, 31 Oct 2002 09:17:23 +0200
Links: << >>  << T >>  << A >>
Weifeng Xu wrote:
> 
> Hi, guys
>    I wanna know whether I can write a script file to generate a final
> bitstream from NCD file,
> can "bitgen" take NCD file directly?
>   Thanks!
> 
> Weifeng

Yes!

Utku

Article: 49059
Subject: Anyone has VHDL code for decimator and interpolater?
From: chankwanchien@yahoo.com (chankc)
Date: 30 Oct 2002 23:54:20 -0800
Links: << >>  << T >>  << A >>
I am currently working on this two multirate signal processing. Anyone
has VHDL code for decimator and interpolater for my reference?

Article: 49060
Subject: Chip for fine delays
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Thu, 31 Oct 2002 21:02:59 +1300
Links: << >>  << T >>  << A >>
Just spotted this interesting looking device at OnSemi
It has 10-bit digital index, nominally 10ps LSB, plus a Analog
pin for 0-60ps delay control.

http://www.onsemi.com/productSummary/0,4317,MC100EP196,00.html

Main purpose is delay trim, but there are more interesting 
ideas this could serve..

Digital + Fine Control VCO 40MHz-200MHz
Aperture Effect Test Systems
MetaStable Effect Test Systems
Phase modulation
Transit delay measurement systems
.....

-jg

Article: 49061
Subject: CLK4p in Nios board schematic
From: Christian Kramer <RemoveThis_christian.kramer@isw.uni-stuttgart.de>
Date: Thu, 31 Oct 2002 09:03:13 +0100
Links: << >>  << T >>  << A >>
Hi!

In the schematic of the Nios development board CLK4p  (Pin N4) is used 
as an output.
In the compiler settings CLK4p is defined as an dedicated clock and is 
therefor an input.

Is there any way to use the CLK4p-pin as an _output_ for a clock-signal 
to other devices connected to the APEX?

Thank you for any help!

Christian



Article: 49062
Subject: Which PCI-IO-Chip manufacturer to prefer?
From: Markus Wolfgart <xx_markus.wolfgart@dlr.de>
Date: Thu, 31 Oct 2002 10:05:29 +0100
Links: << >>  << T >>  << A >>
Hi NG,

I need Your advise for may first pci-io card project.
I would like to transfer a serial data stream (ttl, ecl,
diff-ecl in nrz, bi-phase-l  etc. code, up to 100mbit/s)
to hd or a raid array.
I would like to use the win driver software by jungo.
But I'm not quit sure which io-chip to take, as they
support many brands (PLX,V3,Galileo,Altera,QuickLogic, 
PLDA and AMCC).
So I'm hopeing you could give me some hints on this topic.
In addition I had to mentioned, that my pcb design tool
only support 4x multilayer pcb and I had the need to solder
the pci-chip by hand for my prototype.

Hope this constellation could make it?

Thanks in advance

Markus

============================================

Markus Wolfgart

DLR

============================================
PS.: remove the xx_ from email adr. to reply
============================================

Article: 49063
Subject: XST Constraint
From: theronw@hotmail.com (Theron Wong)
Date: 31 Oct 2002 01:26:39 -0800
Links: << >>  << T >>  << A >>
I have several questions about constraint setting using XST (the one
bundled with ISE 4.1)

1. I am used to writing constraint in ucf file for FPGA express. But
it seems XST does not read my ucf file, does it ? ( I do not see any
hint that XST is using it ) I find there is a synthesize option of XST
called "Synthesis Constraints File", but it does not accept .ucf file
but .cst file. What's .cst file ?

2. There is an option in XST called "Writing Timing Constraints". Its
default value is off. Help file says "this property allow placing the
timing constraints to ncg file". I can't find any ncg file and
besides, isn't that there is something called pcf file ? Can someone
explain these to me.

Thanks.


Theron Wong

Article: 49064
Subject: Re: XST Constraint
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Thu, 31 Oct 2002 09:37:21 +0000 (UTC)
Links: << >>  << T >>  << A >>
Theron Wong <theronw@hotmail.com> wrote:
: I have several questions about constraint setting using XST (the one
: bundled with ISE 4.1)

: 1. I am used to writing constraint in ucf file for FPGA express. But
: it seems XST does not read my ucf file, does it ? ( I do not see any
: hint that XST is using it ) I find there is a synthesize option of XST
: called "Synthesis Constraints File", but it does not accept .ucf file
: but .cst file. What's .cst file ?

You can add .ucf files to a project. It worded for me for pin locking.

: ...

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 49065
Subject: Re: Chip for fine delays
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Thu, 31 Oct 2002 10:08:37 GMT
Links: << >>  << T >>  << A >>
On Thu, 31 Oct 2002 21:02:59 +1300, Jim Granville
<jim.granville@designtools.co.nz> wrote:

>Just spotted this interesting looking device at OnSemi
>It has 10-bit digital index, nominally 10ps LSB, plus a Analog
>pin for 0-60ps delay control.
>
>http://www.onsemi.com/productSummary/0,4317,MC100EP196,00.html
>
>Main purpose is delay trim, but there are more interesting 
>ideas this could serve..
>
>Digital + Fine Control VCO 40MHz-200MHz
>Aperture Effect Test Systems
>MetaStable Effect Test Systems
>Phase modulation
>Transit delay measurement systems
>.....

A close look at the datasheet reveals:

1.  The delay isn't guaranteed to increase monotonically with the
applied digital code.

2.  It isn't guaranteed to produce glitch-free changes in delay.
Considering that the MSB switches a 5ns delay line, the glitches could
be quite severe.

It seems to have been designed for *static* delay trim.  A pity, it
could have been quite useful otherwise.

Regards,
Allan.

Article: 49066
Subject: Re: XST Constraint
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 31 Oct 2002 11:46:28 +0100
Links: << >>  << T >>  << A >>
"Theron Wong" <theronw@hotmail.com> schrieb im Newsbeitrag
news:b847520e.0210310126.5e19405a@posting.google.com...
> I have several questions about constraint setting using XST (the one
> bundled with ISE 4.1)
>
> 1. I am used to writing constraint in ucf file for FPGA express. But
> it seems XST does not read my ucf file, does it ? ( I do not see any
> hint that XST is using it ) I find there is a synthesize option of XST

XST does NOT read the *.ucf , since UCF is first read by translate.

--
MfG
Falk





Article: 49067
Subject: Spartan-II configuration
From: Thomas Heller <theller@python.com>
Date: 31 Oct 2002 11:59:35 +0100
Links: << >>  << T >>  << A >>
I'm planning to configure a Spartan-II device from a small uP in slave
parallel mode.

From looking at the datasheet I have the impression that the following
could work (the processor I want to use is an AMD Am186ED):

Connect the processor's decoded chip select ~PCS signal to the FPGA's
~WR input.

Connect the processor's write signal ~WR to the FPGA's ~CS input, and
also connect this to the FPGA's CCLK input.

Does anyone have some words of wisdom whether this should work?

Thanks,

Thomas Heller

Article: 49068
Subject: 250MHz Data Bus connected directly to Xilinx Virtex-II
From: Song Qian <songq@tsinghua.edu.cn>
Date: Thu, 31 Oct 2002 19:12:12 +0800
Links: << >>  << T >>  << A >>
Hi, everyone

I want to connect a 300MHz data bus directly to Xilinx Virtex-II FPGA,
but I am not very sure about the stability. Is here anybody who have
done it before? I plan to store the datas into FIFOs in FPGA, generated
from dual-port BlockRAM. The timing seems very tight, and would you
point out whether it is worth my effort? Or should I just use a external
demux logic to half the data rate? Welcome all comments.

Song Qian


Article: 49069
Subject: Re: 3.3V Device Programmer Suggestions ?
From: Petter Gustad <newsmailcomp3@gustad.com>
Date: 31 Oct 2002 12:18:07 +0100
Links: << >>  << T >>  << A >>
rrr@ieee.org (Rajeev) writes:


> I think I understand, however the devices of interest are 17S200A
> in 8-pin DIP and are not JTAG devices. While I have no objection to
> using the 18V family, they're bigger packages only and won't fit the
> socket on my development board.

I have never used the 1700's only the 1800's and I made the gross
mis-assumption that the 1700's could be programmed using the JTAG
port like the 1800's - sorry.

Petter
-- 
________________________________________________________________________
Petter Gustad         8'h2B | ~8'h2B        http://www.gustad.com/petter

Article: 49070
Subject: Re: CLK4p in Nios board schematic
From: FermiLab <egads@fnal.gov>
Date: Thu, 31 Oct 2002 06:41:33 -0600
Links: << >>  << T >>  << A >>
In article <apqo6q$a4u$1@news.uni-stuttgart.de>, 
RemoveThis_christian.kramer@isw.uni-stuttgart.de says...
> Hi!
> 
> In the schematic of the Nios development board CLK4p  (Pin N4) is used 
> as an output.
> In the compiler settings CLK4p is defined as an dedicated clock and is 
> therefor an input.
> 
> Is there any way to use the CLK4p-pin as an _output_ for a clock-signal 
> to other devices connected to the APEX?

The only dedicated clock output is the CLKLK_OUT2 pin that comes from a 
PLL driven by the CLK2 pin.  I don't have a datasheet in front of me, 
but I'm pretty sure you can't use CLK4 as anything but a clk input
-- 
                                                                     gad
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
=-=
=          Greg Deuerling, Fermi National Accelerator Laboratory          
=
= P.O.Box 500 MS368  Batavia, IL 60510  (630)840-4629, FAX  (630)840-
5406 =
=                  Electronic Systems Engineering Group                   
=
=            Work: egads@fnal.gov       Personal: gad@elnet.com           
=
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
=-=

Article: 49071
Subject: Re: Information--conference paper
From: "Stelios Zontos" <zontos@telecom.ntua.gr>
Date: Thu, 31 Oct 2002 15:39:38 +0200
Links: << >>  << T >>  << A >>
thanks for your replies...


"Stelios Zontos" <zontos@telecom.ntua.gr> wrote in message
news:aplo1b$91b$1@ulysses.noc.ntua.gr...
> Dear all,
>
> me and my partners have designed and successfully implemented the
electronic
> part of a WDM ring node (Burst Mode Rx/Tx, data storage, MAC protocol).
The
> electronic part consists of two boards and many FPGAs. We tested our
> equipment and we are now interested to present our work to a
> conference/journal. Can somebody give me information on some conferences
and
> on the content of the paper? It is the first time we like to edit a paper
on
> hardware implementation :)
>
> Thanks in advance
> H.
>
>
>



Article: 49072
Subject: V2Pro board with gigabit Ethernet?
From: christopher.saunter@durham.ac.uk (Christopher Saunter)
Date: Thu, 31 Oct 2002 15:00:18 +0000 (UTC)
Links: << >>  << T >>  << A >>
Dear All,

	I am investigating supplimenting a small AMD/Linux/Gigabit
Ethernet cluster we opperate with some FPGA processers.  The processing
done by the cluster is carried out by parallel processes communicating via
MPI.

I am interested in offloading some calculations (FFT ;-) to the FPGA
fabric of a V2Pro, using a RocketIO port to talk to the gigabit interlink
and using off the shelf TCP/IP and MPI code for the PPC as a basis of
bridging the hardware accelerators transparently into the cluster.

So the big question is: Is anyone aware of existing or upcoming
evaluation/dev boards suitable for such an excercise?  Such a board would
have a medium to large V2Pro onboard, 1 (or more ;-) RocketIOs configured
with the appropriate hardware for gigabit ethernet over copper (not fiber)
cabling, with 16+ megs of external RAM that can be used by the FPGA etc.

If you are making or planning to make such a board, I'd be interested to
hear about it, and also any general feedback on the idea is wellcome.

Regards,
	Chris Saunter

Article: 49073
Subject: Coding HDL for Reviewability // Link to paper + 2003 MAPLD Conf
From: vhdlcohen@aol.com (ben cohen)
Date: 31 Oct 2002 07:09:44 -0800
Links: << >>  << T >>  << A >>
Added to my link page
http://members.aol.com/vhdlcohen/vhdl/links.html

http://klabs.org/richcontent/MAPLDCon02/ProgramSessions/Session_P.html  
Paper P30  Coding HDL for Reviewability  Ben Cohen
Presentation: p30_cohen_s.ppt,  p30_cohen_s_appendix.ppt


http://klabs.org/richcontent/MAPLDCon02/MAPLDCon02.html  
2002 MAPLD International Conference September 10-12, 2002

http://klabs.org/richcontent/MAPLDCon03/MAPLDCon03.html 
2003 MAPLD International Conference
Reagan International Trade Center
Washington, D.C. September 9-11, 2003
 
----------------------------------------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  
http://www.vhdlcohen.com/                 vhdlcohen@aol.com  
Author of following textbooks: 
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 
* Component Design by Example ",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

Article: 49074
Subject: Re: Spartan-II configuration
From: Peter Wallace <pcw@karpy.com>
Date: Thu, 31 Oct 2002 07:22:43 -0800
Links: << >>  << T >>  << A >>
On Thu, 31 Oct 2002 02:59:35 -0800, Thomas Heller wrote:

> I'm planning to configure a Spartan-II device from a small uP in slave
> parallel mode.
> 
> From looking at the datasheet I have the impression that the following
> could work (the processor I want to use is an AMD Am186ED):
> 
> Connect the processor's decoded chip select ~PCS signal to the FPGA's
> ~WR input.
> 
> Connect the processor's write signal ~WR to the FPGA's ~CS input, and
> also connect this to the FPGA's CCLK input.
> 
> Does anyone have some words of wisdom whether this should work?
> 
> Thanks,
> 
> Thomas Heller
 
If you get a write signal (~WR) without a chip select (another device
accessed), you will get a configuration abort.
also the CCLK hold time versus CS may be a problem


Peter Wallace



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2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

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