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On Fri, 19 Jul 2002 03:33:30 GMT, bbdjsk <bbd@ksl.com> wrote: That's putting it mildly. >The slump seems to have hit the San Jose area (California's "Silicon Valley") pretty hard.Article: 45326
Or how 'bout something which makes some LED's flash! :) adrian > Regarding the question of how you can get started with ISE > WebPACK, I will recommend that as soon as you finish the tutorials and > understand how the design flow works, start designing something > practical. > In my case, I wanted to connect an FPGA to a computer, so I started > developing a PCI IP core, and after a year of development, it works > fine. > I used Insight Electronics Spartan-II PCI card which cost me $145 back > then (It now costs something like $225.) to test my PCI IP core with a > computer. > If a PCI IP core doesn't fascinate you, develop a 5-state 32-bit RISC > processor. > If you don't want to develop your own instruction set, borrow MIPS, ARM, > or SPARC's instruction set. > You shouldn't have any legal problems (i.e., Getting sued for patent > infringement.) using SPARC's instruction set.Article: 45327
So ok sounds like a bigger project. If you compare DSP and FPGA, I would do the following 1) Where are the areas of your algorithms (you have them in C right) which are most time consuming ? There might be a 80/20 rule 80 % of the code running in 20 % of the time. 2) Now figure out the possibility to develop parralel algorithms for, this is the area where the FPGA comes into the picture. Since you develop your own hardware for an FPGA the strength is really if you can do things parallel. Example: a filter needs some macs on a dsp. For each point you send through the filter you probably need one mac. So if you have a 32 tap filter each symbol needs 32 clock cycles. In an FPGA you can create a filter-structure with 32 mac components, such that in each clock cycle one symbol can be fed through. So I dont have experience with your application but there are many of those optimizations you can do using an FPGA. But forget reusing anything you have (except as reference) is is really a difference to develop parallel algorithms versus sequential ones, which is in fact what it boils down to. Best Regards Andreas "Jay" <kayrock66@yahoo.com> wrote in message news:d049f91b.0207170952.6bd274d4@posting.google.com... > What frame rate/resolution are you targeting? One of the available > MPEG2 ASICs will give you the lowest power solution. I'm not sure if > a DSP can do real time MPEG2 with motion prediction and all that. It > would certainly be the highest power. The FPGA would be somewhere in > the middle and give you the luxury of a custom solution. > > And as far are reusing DSP code, no way, especially if its been tuned > for the particular DSP you're using. The fact that you know the > algorithms because you wrote the C code will be great help as you > recode your design for hardware implimentation. > > Regards > > "paul hill" <paul.hill@bristol.ac.uk> wrote in message news:<aguabf$j5c$1@helle.btinternet.com>... > > Hi, > > > > I'm currently trying to spec a project that needs to do some serious video > > processing (mpeg2 encoding or similar) in a mobile (wearable) environment. > > i.e. battery powered. > > > > Does anyone have any opinion on what dsp platform would be suitable. People > > have been talking about xilinx chips or something similar. However, I'm > > most familiar with DSP programming on ti processors (such as C67xx) but > > would an implementation using ti processors take too much power and be too > > slow. > > > > Ideally I would like to reuse the c-code that I have already for the mpeg2 > > codec but with xilinx chips this would not be possible. > > > > Any ideas anyone? > > > > Paul HillArticle: 45328
Hello, I am trying to use black box components with parameters in Verilog using Synplify. One way of doing this is: module MyModule(....) /* synthesis syn_black_box MyParameter = 3 */; input ... output ... endmodule In this case however, the parameters are the same for all instances of MyModule, which is not what I want. I was wondering if it is allowed to do the following: module MyModule(....) /* synthesis syn_black_box */; parameter MyParameter = 3; input ... output ... endmodule such that the parameter can be defined when instantiating the component? Does Synplify still regards the component (including the parameter) as a black box? Any help appreciated, Regards, JohanArticle: 45329
Sure, they're in production right now, and available through Memec. (probably better known as impact or insight) grtx, chris "Dick Ginther" <dick.ginther@wavecom.ca> wrote in message news:<uj975qs5oagu60@corp.supernews.com>... > Hi, > I'm wondering if there is any good news on the availability of > the Xilinx Virtex-2 XC2V1500 and XC2V2000 parts? Are we > going to be able to get them soon? > Thanks.Article: 45330
hi, you can start with the webpack from xilinx, which is a free software development platform.. Training is available from various sources. In germany for example, it would be PCL2. Expensive but quite good. On the xilinx website, there are also getting-started-with-vhdl- manuals. grtx, chris zy_don@inhe.net (yi don) wrote in message news:<bda385ee.0207120246.51dcb58f@posting.google.com>... > i am interesting in fpga designing,but few experience of designing > fpga,and i am eager to design fpga,so anyone can help me how improve > my experience and where? > > regards.Article: 45331
Than how come that we see tons of postings about jobs in the San Jose area for IC / FPGA designers? (and most of the US?) You guys are lucky, there are tons of job postings for you. Here in Ottawa, there's nothing!! "Spam Hater" <spam_hater_7@email.com> wrote in message news:3d37a61a.2056645@64.164.98.7... > On Fri, 19 Jul 2002 03:33:30 GMT, bbdjsk <bbd@ksl.com> wrote: > > That's putting it mildly. > > >The slump seems to have hit the San Jose area (California's "Silicon Valley") pretty hard. >Article: 45332
Hello, Lattice http://www.latticesemi.com/products/fpga/xpga/index.cfm?CFID=1440042&CFTOKEN =67800398 has just announced a new FPGA family that has used EEPROM on the FPGA to hold the configuration data. One of their rep's FAEs told me that this can not be pirated. The design does not need an external configuration process. Does anyone know if Xilinx or Altera is planning a similar approach ? Dan.Article: 45333
Hi All, I am planning to do my own stand alome software that programs Altera APEX via ByteBlasterMV with *.SOF and *.POF (FlexChain and JTAG) files, so I do not need Altera QuartusII for sending data to device. (Can use my HW design w/o huge QuartusII software...) So, I have been looking all over WWW to find out information about how does Quartus do programming and how those those signals acts on ByteBlasterMV cable. Can you help me where to find some kind of timing waveform / wavediagram where I can start to learn ByteBlasterMV "protocol? Is it possible to do that kind of program...? If there is existing softwares I am also intrested in those *.EXE files. Thank You vert much and have a nice weekend :-) Sincerely, Juha Pajunen, Hw EngineerArticle: 45334
Have a look at our tutorial at http://www.al-williams.com/pictutor. Mostly schematic entry but there is some Verilog and it covers a few things about WebPack that I didn't find obvious at first. The target chip is not the Spartan, but the design flow should be about the same. Al Williams AWC http://www.al-williams.com/awce/pbx84.htmArticle: 45335
We have applications which require high-speed counters. Does anyone have performance metrics that tabulate counter speed & size for various FPGA and/or CPLD manufacturers and speed grades? BTW: An engineer at Digilent said they have run 8-bit counters on Spartan II FPGAs at 400 MHz. Thx, Tom SeimArticle: 45336
In article <iSUZ8.15748$Db.1112005@news20.bellglobal.com>, Dan <daniel.deconinck@sympatico.ca> wrote: >Hello, > >Lattice >http://www.latticesemi.com/products/fpga/xpga/index.cfm?CFID=1440042&CFTOKEN >=67800398 has just announced a new FPGA family that has used EEPROM on the >FPGA to hold the configuration data. One of their rep's FAEs told me that >this can not be pirated. The design does not need an external configuration >process. Actually, this is probably slightly easier to pirate than the Virtex 2 approach: since the bits are static, delid and directly probe the interconnect and configuration. Nothing is IMPOSSIBLE to pirate, it just takes different amounts of work. >Does anyone know if Xilinx or Altera is planning a similar approach ? Probably not, since Xilinx is highly performance and cost oriented, as is Altera, and the processing steps needed to add EEPROM hurt perfromance and/or yield and/or cost. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 45337
Counters come in many flavors. Slowest are the synchronous loadable up-down counters. They use the built-in carry structure, and depending on bit-length, 200 to 300 MHz may be an upper limit. At the other extreme are event counters with an input enable. These are best implemented as ripple-cascaded binaries and can easily do 500 MHz, 1000 MHz with some esoteric tricks. I built a 420 MHz counter in XC4000XL four years ago... Peter Alfke, Xilinx Applications ============================== Tom Seim wrote: > We have applications which require high-speed counters. Does anyone > have performance metrics that tabulate counter speed & size for > various FPGA and/or CPLD manufacturers and speed grades? > > BTW: An engineer at Digilent said they have run 8-bit counters on > Spartan II FPGAs at 400 MHz. > > Thx, > > Tom SeimArticle: 45338
In our case the variable phase shift works great but the DCMs sometimes stop running after only a few cycles. The LOCK output remains high but the clock output stops. We have 5 DCMs we'd like to use in this fashion. We also looked at the status bits but they don't seem to tell us much. I've opened a webcase on the issue. There is an interesting answer record #13756 which probably everyone using DCMs should read. --rod. Yanick wrote: > > Austin, > > This is an important issue for us that we need to solve, this is why I > am asking the group looking for similar experiences and a hopefuly, a > solution. > > The PS=14 is by configuration, not obtained using the DCM PS > interface. Though, we have a dcm_controller module that allows us to > change the phase-shift. We probed the DCM PS interface as well as the > lock signal with a logic analyzer and everything looks good, as > expected. > > This is not an early ES device, as indicated by the JTAG code, so that > errata should not apply anyway. > > Regards, > > Yanick > > Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3D3729C9.482754BA@xilinx.com>... > > Yanick, > > > > Please open a case with the hotline. Typical problems we have seen are: > > > > 1) not implementing the correct interface with PSEN, PSINC/DEC, PSCLK > > > > 2) unit stops inc (or dec) due to the ES issue (fixed in susequent masks > > and production) This is easy to see, because PSDONE goes low, and never > > returns to high (indicating the internal state machineis stuck). > > > > Also please contact your FAE, > > > > Austin > > > > Yanick wrote: > > > > > Hi, > > > > > > We've done some tests in the lab on a XC2V6000 and got results that > > > were not the same using fixed versus variable phase-shift. I first > > > measure the clock-to-out for a signal that is FF in the IOB and that > > > is clocked using a DCM with variable phase-shift = 14 at 175 MHz. I > > > then changed the mode to fixed in fpga_editor and tied all the DCM's > > > PS inputs to logic_0 keeping the same PS=14 and got slightly different > > > clock-to-out. > > > > > > The thing is that our circuits work well when fixed but are erratic > > > when in variable mode. > > > > > > Why does PS=14 lead to a different shift ? > > > > > > Best regards, > > > > > > YanickArticle: 45339
Hello folks, Can you give me an idea of what bit-widths you have used for FIR filter coefficients for real FPGA designs please? Is 12 bits about the norm? I know it depends on the spectral requirements of the filter but I would assume that some people here will have traded filter performance for slices at some point! Thanks for your time, KenArticle: 45340
I am trying to implement a subset of the ata/ide spec on a single fpga/cpld, does anyone know which would be better? Or any recommendations on which specific model? My experience is limited to a little dabbling with a Xilinx Virtex. -JArticle: 45341
In order to do that, you need a unique black box for each variation in the
parameters. You can't pass generics/attributes to a black box. Think of
it as a pre-compiled widget that you just plug in a socket. DIfferent
flavor means different 'part number'.
Johan Ditmar wrote:
> Hello,
>
> I am trying to use black box components with parameters in Verilog
> using Synplify. One way of doing this is:
>
> module MyModule(....)
> /* synthesis syn_black_box
> MyParameter = 3
> */;
>
> input ...
> output ...
>
> endmodule
>
> In this case however, the parameters are the same for all instances of
> MyModule, which is not what I want. I was wondering if it is allowed
> to do the following:
>
> module MyModule(....)
> /* synthesis syn_black_box */;
>
> parameter MyParameter = 3;
>
> input ...
> output ...
>
> endmodule
>
> such that the parameter can be defined when instantiating the
> component? Does Synplify still regards the component (including the
> parameter) as a black box?
>
> Any help appreciated,
>
> Regards,
>
> Johan
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45342
Nicholas Weaver wrote:
> Actually, this is probably slightly easier to pirate than the Virtex 2
> approach: since the bits are static, delid and directly probe the
> interconnect and configuration. Nothing is IMPOSSIBLE to pirate, it
> just takes different amounts of work.
Also, EEPROM is often susceptible to attacks where the supply voltage is
modulated in order to bypass the security bit that normally prevents readback. I
believe there are a number of articles at various places on the web that discuss
some of the attack techniques.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45343
Why not go with Actel or Quicklogic antifuse FPGAs?
The chip will not be upgradable, but it should be a lot more secure than
SRAM FPGAs.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 45344
Off topic, but is Bitboys still trying to come out with a 3D
graphics chip?
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 45345I'm looking for a prototype board with an FPGA on it, an PCI interface (silicon or IP core), and lots of fast SDRAM (256MB or more). Thomas Heller ION-TOF GmbHArticle: 45346
Actel also offers FLASH based FPGAs (ProASIC and ProASIC PLUS). http://www.actel.com/appnotes/DesignSecurity.pdf is a document discussing Actel anti-fuse/flash security vs. SRAM security vs. ASIC security. It's worth a look. Tim Sloper Field Apps Engineer "Kevin Brace" <killspam4kevinbraceusenet@killspam4hotmail.com> wrote in message news:ah9f4k$2pg$2@newsreader.mailgate.org... > Why not go with Actel or Quicklogic antifuse FPGAs? > The chip will not be upgradable, but it should be a lot more secure than > SRAM FPGAs. > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.)Article: 45347
Any comment about Ray Andraka comment that EEPROM? > Also, EEPROM is often susceptible to attacks where the supply voltage is > modulated in order to bypass the security bit that normally prevents readback. I > believe there are a number of articles at various places on the web that discuss > some of the attack techniques. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) "Timothy R. Sloper" wrote: > > Actel also offers FLASH based FPGAs (ProASIC and ProASIC PLUS). > http://www.actel.com/appnotes/DesignSecurity.pdf is a document discussing > Actel anti-fuse/flash security vs. SRAM security vs. ASIC security. It's > worth a look. > > Tim Sloper > Field Apps EngineerArticle: 45348
Erik wrote:
>
> yes, your are right.
> Now i have a big problem!
> I can look to the Spartan II and i see this chip is to slow for my project.
> or i can look to the Virtex-E and i see this chip will not do 5V-PCI.
> But i have a littel bit hope :
>
Why do you think Spartan-II is slower than Virtex?
I believe I said a few postings ago that Spartan-II-6 (speed grade -6)'s
4-input LUT is as fast as Virtex-6 (speed grade -6), although I am not
sure about the interconnect speed.
I will guess that the interconnect speed is going to be about the same.
> I think, you are right, second.
>
> The most modern Southbridges are produced in 0.22µm or 0.18µm
> and use the same trick to be 5V-PCI "compliant". This chips can not
> drive a real 5V-output but also this chips drive the max. IO-Voltage
> (e.g. 3.3V) at the output-pins and the most (not all) real 5V-cards
> accept this as high level.
> The controler-chip on the testet 66MHz-networkcard is 5V-PCI-"compliant"
> to and this is the cause the card is running without error on my board.
>
> - theoretical : if i have a PCI-bus w/o real 5V-PCI-devices i can use
> Virtex-E out of danger.
>
> Do you think thats right ?
>
I am not too familiar regarding the electrical aspects of PCI,
but I personally won't try to put in a Virtex-E into a 5V PCI system
even if you think all the devices there are using 5V I/O tolerant
buffers.
> I have bay a board, with all includet in the chipset, spezial for my projekt.
> This board don't have some onboard-PCI-devices (real nothing) and
> the grafic is includet at the northbridge. I have at the moment pluged only
> two peaces : RAM and CPU.
>
> The best at this idea is the Virtex-E is faster (easy for PCI-timings) ,
> cheaper and have LVD-IO's (good for the external interface).
>
> thanx for your design-tips
>
Although you might think Virtex-E is much faster than Virtex or
Spartan-II, at least I don't believe Virtex-E-6 is that faster than
Virtex-6 or Spartan-II-6.
Yes, Virtex-E-6's 4-input LUT is somewhat faster than Virtex-6 or
Spartan-II-6's, but when I ported my PCI IP core to Virtex-E-6, I felt
like Virtex-E-6's interconnect was somewhat slower than Spartan-II-6's.
Of course, Virtex-E-6 is the slowest Virtex-E, and there are faster -7
and -8 Virtex-E parts.
> i have looked at opencores.org in the free PCI-core and i hope i can use
> some ideas of this design.
> My PCI-core must have 3 sections :
> - configuration-space-target, only 8 different dword-registers,
> including decode the BE-Signals at writes
> - target, only know the 2 write commands, ignore the BE-signals,
> write the data into the input buffer and make a target abord if is full (8 dword's)
> - initiator, wait for an full internal buffer (16 dword's) and write it with an
> normal write command into the system-memory, all BE-signals activ.
> i hope it make the development smarler for me.
> and i did't have a delay betwen differend signaldirections on the bus
> (only write commands used)
>
> Gretings,
> Erik
>
> sorry for my terrible englisch, my favorite language is assembler.
Although it is my biased opinion (Because I have done my own PCI
IP core.), the Opencores.org PCI IP core may not be that helpful after
all unless you are going to use it in your project unmodified.
That's because the authors went into handcrafting gates in their design,
and I feel like that will make it very hard to understand or modify the
design.
An easier way will perhaps be using PCI specification's Appendix B's
target and initiator state machines as an example, and do your own PCI
IP core.
Following the 9 suggestions I mentioned a few postings ago will also be
helpful (I sure wish I knew all those caveats when I started doing my
own.).
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 45349
Here is an interesting paper regarding attacks. While this one focuses on
microcontrollers, many of the techniques discussed apply to other devices.
http://www.cl.cam.ac.uk/~mgk25/sc99-tamper.pdf
Presentation slides with more photos:
http://www.cl.cam.ac.uk/~mgk25/sc99-tamper-slides.pdf
It doesn't address the issue I mentioned, and now I can't remember where I saw it.
IIRC, it was a case where you could do something to the supply voltage on a particular
device (I think it was an 8051 variant) that would wind up defeating the security bit.
Kevin Brace wrote:
> Any comment about Ray Andraka comment that EEPROM?
>
> > Also, EEPROM is often susceptible to attacks where the supply voltage is
> > modulated in order to bypass the security bit that normally prevents readback. I
> > believe there are a number of articles at various places on the web that discuss
> > some of the attack techniques.
>
> Kevin Brace (In general, don't respond to me directly, and respond
> within the newsgroup.)
>
> "Timothy R. Sloper" wrote:
> >
> > Actel also offers FLASH based FPGAs (ProASIC and ProASIC PLUS).
> > http://www.actel.com/appnotes/DesignSecurity.pdf is a document discussing
> > Actel anti-fuse/flash security vs. SRAM security vs. ASIC security. It's
> > worth a look.
> >
> > Tim Sloper
> > Field Apps Engineer
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z