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Messages from 45375

Article: 45375
Subject: Re: spiral / waterfall /watersluice : Which are your methods?
From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver)
Date: Sat, 20 Jul 2002 20:04:18 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3D39A9D5.8A03B9E3@yahoo.com>,
rickman  <spamgoeshere4@yahoo.com> wrote:

>bugs.  If we all continued to use Windows 95 and Microsoft continued to
>make patches for bug fixes, I expect we would start seeing a lot more
>hardware problems and eventually see very few software problems.  But
>then Bill would ultimately become very poor.  

The rest makes sense, this is TOTALLY FUCKING BOGUS, because the basic
design of Win95 really doesn't lead itself to robustness.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 45376
Subject: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
From: "Niv" <niv@ntlworld.com>
Date: Sun, 21 Jul 2002 09:37:35 +0100
Links: << >>  << T >>  << A >>
As I understood it, from Xilinx FAE's, the embedded multilplier should be
faster than one built fromCLB's/slices.
Also, if your code implies a 16*16, then the synthesis tool should infer the
VirtexII 18*18 mult.

I could be wrong of course, not used Vtx2, only Vtx which doesn't have
mults.
Niv.

HUA QIAN <qianhua@ece.gatech.edu> wrote in message
news:3D39828F.189F00AB@ece.gatech.edu...
> Hello, all,
>
> I noticed that Xilinx Vertex-II provide 18*18 multipliers, which
> introduce a lot of delays.  Can I generate a more efficient 16*16
> multiplier, which is my target, and give me a shorter delay?
>
> Another question is how to determine the clock speed for the Vertex-II
> embedded multiplier?
>
> Any advice or help is greatly appreciated!
>
> Hua
>



Article: 45377
Subject: Re: I want to buy 4 Xilinx FPGA
From: "Erik" <vikinger@uni.de>
Date: Sun, 21 Jul 2002 14:08:27 +0100
Links: << >>  << T >>  << A >>
Hi Kevin,

>         Why do you think Spartan-II is slower than Virtex?
> I believe I said a few postings ago that Spartan-II-6 (speed grade -6)'s
> 4-input LUT is as fast as Virtex-6 (speed grade -6), although I am not
> sure about the interconnect speed.
> I will guess that the interconnect speed is going to be about the same.

I look at first in the Table, from the Chip-description-pdf,
 "Table 2: Performance for Common Circuit Functions" .
In this Table you can found some differences betwen the FPGA-Families.

I hope this tables are korrect.


> > - theoretical : if i have a PCI-bus w/o real 5V-PCI-devices i can use
> >                      Virtex-E out of danger.
> >
> > Do you think thats right ?
>
>         I am not too familiar regarding the electrical aspects of PCI,
> but I personally won't try to put in a Virtex-E into a 5V PCI system
> even if you think all the devices there are using 5V I/O tolerant
> buffers.

Why not? I will check the real Voltage-levels on the Signallines with an
oscilloscope and if i see the highest level is 3.3V i can use the Virtex-E.


Bye
Erik



Article: 45378
Subject: Re: spiral / waterfall /watersluice : Which are your methods?
From: rickman <spamgoeshere4@yahoo.com>
Date: Sun, 21 Jul 2002 13:36:15 -0400
Links: << >>  << T >>  << A >>
Nicholas Weaver wrote:
> 
> In article <3D39A9D5.8A03B9E3@yahoo.com>,
> rickman  <spamgoeshere4@yahoo.com> wrote:
> 
> >bugs.  If we all continued to use Windows 95 and Microsoft continued to
> >make patches for bug fixes, I expect we would start seeing a lot more
> >hardware problems and eventually see very few software problems.  But
> >then Bill would ultimately become very poor.
> 
> The rest makes sense, this is TOTALLY FUCKING BOGUS, because the basic
> design of Win95 really doesn't lead itself to robustness.
> --
> Nicholas C. Weaver                                 nweaver@cs.berkeley.edu


Don't hold back, tell us how you REALLY feel...  :)

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 45379
Subject: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
From: "Ulf Samuelsson" <ulf@atmel.REMOVE.com>
Date: Sun, 21 Jul 2002 20:34:18 +0200
Links: << >>  << T >>  << A >>
"jetmarc" <jetmarc@hotmail.com> skrev i meddelandet
news:af3f5bb5.0207151541.3188ca0a@posting.google.com...
> Hi.
>
> Is anyone aware of 3rd party place & route tools for Atmels AT40K and
FPSLIC
> series? I know that their own "Figaro IDS" is available on the web site.
I'm
> looking for alternatives.
>
> Marc

It would be interesting to understand why you are looking for alternatives?

--
Best Regards
Ulf at atmel dot com
These comments are intended to be my own opinion and they
may, or may not be shared by my employer, Atmel Sweden.




Article: 45380
Subject: Re: spiral / waterfall /watersluice : Which are your methods?
From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver)
Date: Sun, 21 Jul 2002 18:36:54 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3D3AF10F.78585E1B@yahoo.com>,
rickman  <spamgoeshere4@yahoo.com> wrote:
>> The rest makes sense, this is TOTALLY FUCKING BOGUS, because the basic
>> design of Win95 really doesn't lead itself to robustness.
>
>Don't hold back, tell us how you REALLY feel...  :)

Hehehheheheheh.

I keep meaning to write a rant: "Who's afraid of Address
Translation".  

So many embedded and small systems don't seem to use or understand
just how nice the TLB is for making things more robust.  EG, the
Palm's tendency to freeze up when a single app misbehaves.  The TLB
costs effectively nothing to use, isn't hard to construct the OS to
support, and it makes everyone's life so, SOO much easier.

Just as "Who's afraid of AES", as people STILL keep implementing their
own cyphers for link/bulk encryption, when AES is 500 Mbps on a modern
CPU, and >1.2 Gbps in a $10 FPGA.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 45381
Subject: Re: Spartan II JTAG connection with other devices
From: Ray Andraka <ray@andraka.com>
Date: Sun, 21 Jul 2002 20:17:31 GMT
Links: << >>  << T >>  << A >>
It should be OK with the CPLD and PROM, but I wouldn't put the processor in the
same chain.  Processor emulator/debug tools that use JTAG tend to not meet the
whole JTAG spec, and as a result running the debug tools can inadvertently upset
the FPGA/CPLD configuration....I've seen this happen to several customers.

"Deli Geng (David)" wrote:

> Hi, there,
>
> I was just wondering if SpartanII JTAG can be connected with other JTAG
> device. For example, in my design, there are JTAG devices of  SpartanII
> FPGA, CPLD, PROM and ARM processor. Can I serially connect them together as
> standard way? If yes, will there be any problem when using JTAG to programme
> SpartanII? Is there any reference design available?
>
> Thanks a lot.
>
> David

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 45382
Subject: Re: TMS 1000
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Mon, 22 Jul 2002 09:25:42 +1200
Links: << >>  << T >>  << A >>
Spehro Pefhany wrote:
> 
> The renowned Charlie <railroads@clear.net.nz> wrote:
> > I am still looking for someone who can idvise on extracting program
> > from a TMS1000 and installing on a modern IC with a few minor changes.
> 
> Reverse engineering from the function would probably be cheaper. I don't
> know if the TMS1000 has a back door for getting at the program code, but
> if not you are looking at a fairly large cost. As someone else said, this
> was not much of a micro- 4 bit, no interrupts and 1 or 2K of ROM, but had
> 31 microprogramed custom instructions and 12 hard wired.
> 
> Interstingly, according to one web page, they used a LFSR as the PC, so
> consecutive instructions were all over the place in the memory.

 Wow - and not so silly, when you think more about it :
 The 'linker' can manage code shuffles, and a LFSR is both
silicon frugal and fast. 
 Relative jumps would be out, but long jumps would load instead
of shift, and a skip could 'double clock'.
 Look up tables would need to be in separate space.

 Logically, the opcode size would equal the PC, but the concept of 
scalable compilers is emerging.

 Could have good scope in TinyCore.fpga 'state engine' applications ?

-jg

Article: 45383
Subject: Re: TMS 1000
From: mcginnis@remove_this.ieee.org (Jim McGinnis)
Date: Sun, 21 Jul 2002 23:20:31 GMT
Links: << >>  << T >>  << A >>
On Mon, 22 Jul 2002 09:25:42 +1200, Jim Granville
<jim.granville@designtools.co.nz> wrote:

>Spehro Pefhany wrote:
>> 
>> The renowned Charlie <railroads@clear.net.nz> wrote:
>> > I am still looking for someone who can idvise on extracting program
>> > from a TMS1000 and installing on a modern IC with a few minor changes.
>> 
>> Reverse engineering from the function would probably be cheaper. I don't
>> know if the TMS1000 has a back door for getting at the program code, but
>> if not you are looking at a fairly large cost. As someone else said, this
>> was not much of a micro- 4 bit, no interrupts and 1 or 2K of ROM, but had
>> 31 microprogramed custom instructions and 12 hard wired.
>> 
>> Interstingly, according to one web page, they used a LFSR as the PC, so
>> consecutive instructions were all over the place in the memory.
>
> Wow - and not so silly, when you think more about it :
> The 'linker' can manage code shuffles, and a LFSR is both
>silicon frugal and fast. 
> Relative jumps would be out, but long jumps would load instead
>of shift, and a skip could 'double clock'.
> Look up tables would need to be in separate space.
>
> Logically, the opcode size would equal the PC, but the concept of 
>scalable compilers is emerging.
>
> Could have good scope in TinyCore.fpga 'state engine' applications ?
>
>-jg

It was rumored that the LFSR avoided having to propagate the carry
through the 6 bits of the PC corresponding to a 64 byte page within
the 25 microsecond clock period. The assembler - there wasn't a linker
- invisibly shuffled the code for you, so mostly you weren't bothered
by the LFSR.

The flaw with this scheme was the grief it caused with table lookups.
While it was easy to index into RAM, it was very hard to index into
ROM. IIRC TI provided a special instruction to decrement a regiater
and if the result was zero, load a 4-bit immediate value into another
register (or something like that). You'd execute a series of these
decrement-conditional-load-immediate instructions, and at the end the
proper value would have been loaded. Since instructions were 8 bits,
this method doubled the size of ROM tables.

-jam



Article: 45384
Subject: Clock-gating in Virtex-E parts
From: Jason Crawford <jace@cisco.com>
Date: Mon, 22 Jul 2002 16:55:37 +1000
Links: << >>  << T >>  << A >>
Hi,

Apart from using clock-enables, does anyone know of any
way to use clock-gating in Virtex-E parts? 

We have a design that is partially written for an ASIC 
target and expects to see a gated clock. Rather than have 
to get the designers to pour throught the code and add
clock enables to all flip flops (I can hear teeth gnashing
already) I am hoping against hope that someone has an 
alternate answer to this rather difficult problem.

yours in hope,
Jason.

Article: 45385
Subject: Re: Making my own software
From: "Wolfgang Loewer" <wolfgang.loewer@elca.de>
Date: Mon, 22 Jul 2002 10:31:00 +0200
Links: << >>  << T >>  << A >>
Hi,

*.SOF and *.POF files are proprietary formats and there's no public
information available about these formats. Within QuartusII however you can
convert *.SOF files into *.JBC or *.JAM files. These formats are public and
well documented and you can get C source code or readily compiled so called
JAM players for various platforms and download cables. Just look at
http://www.jamisp.com/ for more information on ISP or ICR using JAM STAPL.

Regards
Wolfgang
http://www.elca.de

"Juha Pajunen" <juha.pajunen@bitboys.com> schrieb im Newsbeitrag
news:4b980638.0207190558.37890b2d@posting.google.com...
> Hi All,
>
> I am planning to do my own stand alome software
> that programs Altera APEX via ByteBlasterMV
> with *.SOF and *.POF (FlexChain and JTAG)
> files, so I do not need Altera QuartusII
> for sending data to device. (Can use my HW design
> w/o huge QuartusII software...)
>
> So, I have been looking all over WWW to find out
> information about how does Quartus do programming
> and how those those signals acts on ByteBlasterMV
> cable.
>
> Can you help me where to find some kind of timing
> waveform / wavediagram where I can start to learn
> ByteBlasterMV "protocol?
>
> Is it possible to do that kind of program...?
>
> If there is existing softwares I am also intrested
> in those *.EXE files.
>
> Thank You vert much and have a nice weekend :-)
>
> Sincerely,
> Juha Pajunen, Hw Engineer



Article: 45386
Subject: Re: black box components with parameters in Synplify
From: johanditmar@hotmail.com (Johan Ditmar)
Date: 22 Jul 2002 01:59:26 -0700
Links: << >>  << T >>  << A >>
Thanks Ray, this is helpful information. However, when you say "you
can't pass generics/attributes to a black box", is this true for black
boxes in general, or only when using Synplify?

I know you can pass parameters to black boxes with Leonardo Spectrum,
see for example:

http://www.altera.com/support/solutions/how_do_i/rd12231998_6350.html

These parameters then appear as properties in the synthesized EDIF.

However, I haven't been able to find such information on Synplify.

Regards,

Johan

Ray Andraka <ray@andraka.com> wrote in message news:<3D383933.70DEAEAE@andraka.com>...
> In order to do that, you need a unique black box for each variation in the
> parameters.  You can't pass generics/attributes to a black box.  Think of
> it as a pre-compiled widget that you just plug in a socket.  DIfferent
> flavor means different 'part number'.
> 
> Johan Ditmar wrote:
> 
> > Hello,
> >
> > I am trying to use black box components with parameters in Verilog
> > using Synplify. One way of doing this is:
> >
> > module MyModule(....)
> > /* synthesis syn_black_box
> >    MyParameter = 3
> > */;
> >
> > input ...
> > output ...
> >
> > endmodule
> >
> > In this case however, the parameters are the same for all instances of
> > MyModule, which is not what I want. I was wondering if it is allowed
> > to do the following:
> >
> > module MyModule(....)
> > /* synthesis syn_black_box */;
> >
> > parameter MyParameter = 3;
> >
> > input ...
> > output ...
> >
> > endmodule
> >
> > such that the parameter can be defined when instantiating the
> > component? Does Synplify still regards the component (including the
> > parameter) as a black box?
> >
> > Any help appreciated,
> >
> > Regards,
> >
> > Johan
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

Article: 45387
Subject: Re: I would like to know how to develop a MCU.
From: "Benjamin Todd" <Benjamin.Todd@cern.ch>
Date: Mon, 22 Jul 2002 11:04:13 +0200
Links: << >>  << T >>  << A >>
i think this is helpful:

http://www.xilinx.com/support/techxclusives/PSM-techX25.htm
http://www.xilinx.com/support/techxclusives/PSM2-techX26.htm
http://www.xilinx.com/support/techxclusives/PSM3-techX27.htm
http://www.xilinx.com/support/techxclusives/PSM4-techX28.htm




"Reala" <manfield.chow@scoreconcept.com> wrote in message
news:ah2n75$sr82@imsp212.netvigator.com...
> Dear all,
>
> I would like to know the procedure of developing a simple MCU.
> Any website talk about this? I would like to develop the chip by verilog
and
> implement by FPGA. Any suggestion for me? which free tools in good for me?
> Thank a lot.
>
> Reala
>
>
>
>



Article: 45388
Subject: Verilog newbie question
From: "BÝrge Strand" <borge.strand.remove.if.not.spamming@sintef.no>
Date: Mon, 22 Jul 2002 13:31:37 +0200
Links: << >>  << T >>  << A >>
Hi, I have a Verilog question that I hope is fairly basic. I'm running
through a tutorial and thought about testing a serial adder. The thing works
just fine, but then I try to reduce the number of registers in my code.

What I want to do is generate a new sum and carry (temp) based on the
current inputs (a and b) and the previous carry (temp[1]). The syntax
checker parses the lines with "dummy" in them, but does not parse the one
performing the addition. Is that right?

Best regards,
BÝrge Strand

Here's my code:

module serialadder (clock, a, b, sum); // sum is the serial addition of a
and b
 input clock, a, b;
 output sum;
 reg [1:0] temp;
 reg dummy;

 assign sum=temp[0]; // syntax checks when sum is not a reg

 initial
  begin
   temp=2'b00; // start with no sum yet calculated
   dummy=0;
  end

 always @(negedge clock)
    begin
   temp = a + b + #5 temp[1]; // new sum is a + b + previous carry  // parse
error in Xilinx WebPack
   dummy = #5 dummy; // parses OK
  end
endmodule





Article: 45389
Subject: Re: Spartan II JTAG connection with other devices
From: Petter Gustad <newsmailcomp3@gustad.com>
Date: Mon, 22 Jul 2002 12:07:55 GMT
Links: << >>  << T >>  << A >>
"Deli Geng (David)" <deli.geng@ncl.ac.uk> writes:

> Hi, there,
> 
> I was just wondering if SpartanII JTAG can be connected with other JTAG
> device. For example, in my design, there are JTAG devices of  SpartanII
> FPGA, CPLD, PROM and ARM processor. Can I serially connect them together as
> standard way? If yes, will there be any problem when using JTAG to programme
> SpartanII? Is there any reference design available?
> 
> Thanks a lot.

I have programmed 18V04's and 95144's which have been in the same
chain as my ASIC's. This worked fine with the impact tool, but I never
managed to get it working with the older jtagprog. For production type
work we are using software from JTAG Technologies BV to program the
95144's as well as some non-JTAG serial proms etc.

You could be conservative and add multiple chains to your board, e.g.
a Xilinx only chain and a chain of all your jtag devices.

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 45390
Subject: Re: Xilinx (spartan 2) - SI even applies to the config pins
From: "jakab tanko" <jtanko@ics-ltd.com>
Date: Mon, 22 Jul 2002 08:16:53 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

------=_NextPart_000_0039_01C23158.23236340
Content-Type: text/plain;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Hello,

Just out of curiosity; which signal integrity simulator
would handle the Virtex2Pro 3.xx gbits/s IO ?
Thanks,

jakab
  Austin Lesea <austin.lesea@xilinx.com> wrote in message =
news:3D32E643.D5BD9172@xilinx.com...
  Jon, 
  This is a classic signal integrity SI) problem. 

  The clock frequency isn't the issue, it is the rise and fall times, =
which are incredibly fast (< 1 ns). 

  Thus with a 10 Gs scope with 3 GHz fet probes, you might be able to =
see what is happening (impedance mis-match).  Seeing it won't help you =
though. 

  I would simulate your PCB and drivers and receivers using IBIS models, =
and the extracted pcb trace impedances and other transmission line =
characteristics using an IBIS simulator (Hyperlynx, Cadence =
SpectraQuest, Mentor, Innoveda, etc).  This way you can layout the =
board, place terminations, adjust the impedances of the lines, etc. 

  The idea is that if you simulate it, you can fix it before you build =
the boards, and save spinning the pcb due to SI issues three to seven =
times (typical of what happens if you don't simulate!). 

  When the boss complains about the price of the simulator, I think the =
idea of no more board spins for SI, and no more wasted time playing with =
unreliable bandaids (ie caps) will win the argument forever.  Innoveda's =
Hyperlynx costs less than spinning the pcb even once. 

  Austin 

  Jon Nicoll wrote: 

    Hello there 
        I'm working on getting some FPGA images into a daisy chain of 
    three Spartan 250s. This is loaded in byte serial mode via the 
    parallel port pins of a Motorola coldfire processor. 
    This is a relatively simple extension of the sort of loading we've 
    done successfully in the past (eg. we've loading two devices, not 
    three), but we've had a _lot_ of trouble getting this running on our =

    new hardware. 

    Our current fix is to put a small cap (22pF) from the CLK line to 
    ground. We cannot see the effect of this cap on the 'scope, but it 
    definitely makes a difference to the loading. 

    Our concern is that even without the cap all the timing constraints 
    for programming the Xilinx parts appear to be being met. the CLK =
line 
    is slew-rate limited to ~10nS, and there appears to be no coupling 
    between the CLK and PROGRAM pins. We believe that we are ensuring =
that 
    the various details mentioned in app notes etc. are being adhered =
to. 

    The board is very well decoupled and we are confident of the DC 
    supplies to the processor and FPGAs. The general purpose pins on the =

    Motorola Parallel port are supposedly well capable of driving these 
    loads, and we're not running at any great speed (CLK about 1usec =
high, 
    4usec low). 

    My question is - is there any 'lore' out there about programming 
    Xilinx parts, or Spartan 2s in particular, that might shed light on 
    this problem? Any pointers very gratefully received! 

        Thanks 
        Jon Nicoll 
        Alembis Ltd.




Article: 45391
Subject: Re: what FIR filter coefficient bit widths do you use?
From: "Ken Mac" <aeu96186@yahoo.co.uk>
Date: Mon, 22 Jul 2002 14:34:22 +0100
Links: << >>  << T >>  << A >>

Thanks for the reply.

I am aware of that program but the point of my post was really to get an
idea of what people in this group have actually implemented.

Thanks,

Ken

> ONEoverT from www.tyder.com will show you the effect of coefficient
> quantization.
> They have a vhdl module which generates RTL VHDL code to produce fir
filters
> for an fpga. There are probably other software out these as well that will
help
> you
> but I just cant think of their names at the moment
>
> Good luck
>
> Many



Article: 45392
Subject: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
From: jetmarc@hotmail.com (jetmarc)
Date: 22 Jul 2002 06:37:27 -0700
Links: << >>  << T >>  << A >>
> It would be interesting to understand why you are looking for alternatives?

Please see my private email.

Article: 45393
Subject: Delays in Leonardo
From: jetmarc@hotmail.com (jetmarc)
Date: 22 Jul 2002 06:51:38 -0700
Links: << >>  << T >>  << A >>
Hi..  

I want to generate a ram write pulse, with combinatoric logic:

                _____________               ______
CLOCK        __/             \_____________/
                  ___________:_______________
reg_WE       ____/           :               \____
                             :
                             :<->: 3ns min
                    _________:___:                 
write_pulse  ______/             \___________/\___
                                             ^^------ glitches here
                                                      don't matter
To accomplish this, I need delayed versions of CLOCK:

             ____               _____________       
CLOCK_inv1       \_____________/             \________

                    _____________               ______
CLOCK_inv2   ______/             \_____________/


"CLOCK_inv2 AND reg_WE" would (in theory) result in the desired write_pulse.

However, Leonardo detects that "invert twice" == "do nothing", and connects
CLOCK directly to the AND gate.

I have set the "preserve_driver" signal attribute of CLOCK_inv1+2 to "true",
but this didn't help.  The double inversion is optimized away.

How can I keep Leonardo from removing this?

Marc

Article: 45394
Subject: Re: Clock-gating in Virtex-E parts
From: Ken McElvain <ken@synplicity.com>
Date: Mon, 22 Jul 2002 14:06:20 GMT
Links: << >>  << T >>  << A >>
You could use Certify SC (an option to Synplify Pro), which
has ASIC conversion features including automatic conversion of gated
clocks to enables.

Jason Crawford wrote:

> Hi,
> 
> Apart from using clock-enables, does anyone know of any
> way to use clock-gating in Virtex-E parts? 
> 
> We have a design that is partially written for an ASIC 
> target and expects to see a gated clock. Rather than have 
> to get the designers to pour throught the code and add
> clock enables to all flip flops (I can hear teeth gnashing
> already) I am hoping against hope that someone has an 
> alternate answer to this rather difficult problem.
> 
> yours in hope,
> Jason.
> 


Article: 45395
Subject: Re: How could I generated an efficient 16*16 multiplier in Vertex-II?
From: "Jakka Bhasker Reddy" <jbreddy@imec.be>
Date: Mon, 22 Jul 2002 16:10:11 +0200
Links: << >>  << T >>  << A >>
In V2 there are built in multipliers (MULT18X18)  and you are correct that
they introduce lot of delay. If you want fast clock speeds you can use other
multipliers category called synchronous multipliers '  MULT18X18S'. But they
introduce one clock cycle delay. You can search in Xilinx data base for
exact time delays for both multipliers.
You can generate 16*16 multiplier with CLB's with the use of Coregen. But I
don't have any idea how it performs (better than embedded ones).

Bhasker
HUA QIAN <qianhua@ece.gatech.edu> wrote in message
news:3D39828F.189F00AB@ece.gatech.edu...
> Hello, all,
>
> I noticed that Xilinx Vertex-II provide 18*18 multipliers, which
> introduce a lot of delays.  Can I generate a more efficient 16*16
> multiplier, which is my target, and give me a shorter delay?
>
> Another question is how to determine the clock speed for the Vertex-II
> embedded multiplier?
>
> Any advice or help is greatly appreciated!
>
> Hua
>
>



Article: 45396
Subject: Re: Delays in Leonardo
From: Laurent Gauch <laurent.gauch@amontec.com>
Date: Mon, 22 Jul 2002 16:39:06 +0200
Links: << >>  << T >>  << A >>
maybe change your way:

do a reg_WE flip-flip on the rising edge of CLOCK and an other one on 
the falling edge of CLOCK, then your combinatoric logic.

you want :

CLK          ____--------_________---------__________-------
reg_we_rise  ______-----------------________________________
reg_we_fall  ______________------------------_______________
after comb:  _______--------________________________________

In VHDL, the 'after comb' will be written :

after_comb <= '1' WHEN (reg_we_rise='1' and reg_we_fall='0') ELSE '0' ;

EASY AND ALL SYNTHESIZER WILL KEEP YOUR LOGIC.

Laurent
for www.amontec.com
 From idea to hardware in a fraction of time.

jetmarc wrote:

> Hi..  
> 
> I want to generate a ram write pulse, with combinatoric logic:
> 
>                 _____________               ______
> CLOCK        __/             \_____________/
>                   ___________:_______________
> reg_WE       ____/           :               \____
>                              :
>                              :<->: 3ns min
>                     _________:___:                 
> write_pulse  ______/             \___________/\___
>                                              ^^------ glitches here
>                                                       don't matter
> To accomplish this, I need delayed versions of CLOCK:
> 
>              ____               _____________       
> CLOCK_inv1       \_____________/             \________
> 
>                     _____________               ______
> CLOCK_inv2   ______/             \_____________/
> 
> 
> "CLOCK_inv2 AND reg_WE" would (in theory) result in the desired write_pulse.
> 
> However, Leonardo detects that "invert twice" == "do nothing", and connects
> CLOCK directly to the AND gate.
> 
> I have set the "preserve_driver" signal attribute of CLOCK_inv1+2 to "true",
> but this didn't help.  The double inversion is optimized away.
> 
> How can I keep Leonardo from removing this?
> 
> Marc
> 


Article: 45397
Subject: Re: black box components with parameters in Synplify
From: Ken McElvain <ken@synplicity.com>
Date: Mon, 22 Jul 2002 14:52:16 GMT
Links: << >>  << T >>  << A >>
Synplify 7.1 supports generics and attributes on a black box.
For different values of generics, Synplify will automatically
create differently named cells to make instantiations of.
In the case of LPM components for Altera, the cell names
don't matter, the lpm_type attribute does, so this works
pretty well.

Johan Ditmar wrote:

> Thanks Ray, this is helpful information. However, when you say "you
> can't pass generics/attributes to a black box", is this true for black
> boxes in general, or only when using Synplify?
> 
> I know you can pass parameters to black boxes with Leonardo Spectrum,
> see for example:
> 
> http://www.altera.com/support/solutions/how_do_i/rd12231998_6350.html
> 
> These parameters then appear as properties in the synthesized EDIF.
> 
> However, I haven't been able to find such information on Synplify.
> 
> Regards,
> 
> Johan
> 
> Ray Andraka <ray@andraka.com> wrote in message news:<3D383933.70DEAEAE@andraka.com>...
> 
>>In order to do that, you need a unique black box for each variation in the
>>parameters.  You can't pass generics/attributes to a black box.  Think of
>>it as a pre-compiled widget that you just plug in a socket.  DIfferent
>>flavor means different 'part number'.
>>
>>Johan Ditmar wrote:
>>
>>
>>>Hello,
>>>
>>>I am trying to use black box components with parameters in Verilog
>>>using Synplify. One way of doing this is:
>>>
>>>module MyModule(....)
>>>/* synthesis syn_black_box
>>>   MyParameter = 3
>>>*/;
>>>
>>>input ...
>>>output ...
>>>
>>>endmodule
>>>
>>>In this case however, the parameters are the same for all instances of
>>>MyModule, which is not what I want. I was wondering if it is allowed
>>>to do the following:
>>>
>>>module MyModule(....)
>>>/* synthesis syn_black_box */;
>>>
>>>parameter MyParameter = 3;
>>>
>>>input ...
>>>output ...
>>>
>>>endmodule
>>>
>>>such that the parameter can be defined when instantiating the
>>>component? Does Synplify still regards the component (including the
>>>parameter) as a black box?
>>>
>>>Any help appreciated,
>>>
>>>Regards,
>>>
>>>Johan
>>>
>>--
>>--Ray Andraka, P.E.
>>President, the Andraka Consulting Group, Inc.
>>401/884-7930     Fax 401/884-7950
>>email ray@andraka.com
>>http://www.andraka.com
>>
>> "They that give up essential liberty to obtain a little
>>  temporary safety deserve neither liberty nor safety."
>>                                          -Benjamin Franklin, 1759
>>


Article: 45398
(removed)


Article: 45399
(removed)




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