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Javier, You can not make the measurement to required degree of accuracy with a scope. We use a Wavecrest Jitter Analyzer, (best), followed by the Tek CSA 8000 digital sampling scope, followed by the LeCroy. The easiest to use is the Wavecrest (because I use it so much), but perhaps the other easiest to use once you learn the menu is the LeCroy. You are right in that you have to sample all clocks, and to do that, a simple shift in time is what people use. Unfortunately, the simple shift in time presumes statistics about the signal which may not be true (a perfect stationary random process -- just a mathematical convenience, seldom a reality). The means by which the shift in time is introduced to trigger a scope leads to more jitter than may be in the signal. This is the reason why a sampling scope is more useful, as it digitizes the signal based on the internal, or external, sampling clock (which also adds jitter). Best is an instrument designed to make the measurement (like the Wavecrest). LeCroy also makes some nice digitizing scopes with special processing for jitter that we use. They have a new instrument that is targeted at jitter (really nice!). It is really a complete DSO, but its front panel, menus, etc. are all targeted at jitter measurements. An example of accuracy: Wavecrest +/- 3 ps (our model, the newer one is 10X better), LeCroy +/- 6 ps (again the one we have), Tek 8000 +/- 5 ps on P-P readings. More important is how long it takes to get a 99.9995% accuracy: Wavecrest less than a minute, LeCroy about 5 minutes, Tek 8000 > 10 minutes. Any other scope is worse in resolution, and accuracy, and may take an hour or more to accumulate at least 200,000 clock periods randomly to analyze. 1,000,000 samples is about right for a really accurate measurement. Most engineers are not patient, so they wait until they lose patience, and take down the reading. Bad practice. With P-P jitter, you have to wait until the reading stops increasing (converges on say changes less than 1% in a one minute interval). Additionally, you need to "tail fit" gaussian curves the right and left edges of the histogram to predict the 'true' P-P value once you have enough data. Thus scopes under report jitter by as much as 20% if you are patient and do everything right, or by 2X or 3X if you are impatient and sloppy. Scopes can also over report if you use the internal delayed trigger (as it adds its own jitter). Of course, none of the above instruments are able to apply a filter before measurement. To measure the RMS jitter in a filtered bandwidth implies that you have phase locked a reference clock to the clock to be measured, mixed the two together, filtered out the upper sideband and passed it thru a bandpass filter that is specified, and measure the resulting power (common in telecom for repeater jitter analysis from T1/E1 upp to OC-192). One can use a spectrum analyzer to see the sidebands to the clock signal (phase noise), but this is a frequency domain measurement, not a time domain measurement, and does not tell you what the P-P jitter is, but does tell you about the spectral content of the energy, and can identify deterministic components. Austin Javier Serrano wrote: > Austin, I've never measured such low jitters either but I always thought it > was my oscilloscope's limitation. Could you specify whether you take that > into account? I would say that if you measure the jitter between a signal > and that same signal delayed by some 1 ns of cable, you should find there > the floor of your measurement device. You could then subtract that straight > (p-p) or quadratically (rms) from whatever you measure afterwards. Is this > correct? > Javier > > "Austin Lesea" <austin.lesea@xilinx.com> wrote in message > news:3D86595C.DA17ACBE@xilinx.com... > > Larry, > > > > Wow. I'd like to see anything with that low a jitter specification. It > is almost > > unbelievable. We have never seen anything with less than 20 ps P-P jitter > in the > > lab, once it was properly measured over a few million samples. Even on > parts that > > had such wildly optomistic specifications. > > > > RMS to P-P is a magic art, and I would suggest that 15X to 20X is more > reasonable > > for +/- 6 sigma which is going to be closer to the actual P-P measure once > we tail > > fit to a guassian curve. that is one reason why clock oscillator people > love > > specifying RMS: it is useless for the application, but it always looks > nice. > > > > Also the band limit makes it look nicer. Unfortunately, digital logic > doesn't care > > about filtered bands, and a bit error is a bit error. So in reality that > > oscillator is probably 35 ps P-P full bandwidth, no better than any other > good xtal > > part....... > > > > Austin > > > > Larry Doolittle wrote: > > > > > On Mon, 16 Sep 2002 10:45:52 -0700, Austin Lesea wrote: > > > >jakab tanko wrote: > > > >> In my oppinion one PLL in a DAC or ADC clock path is one to many.. > > > > > > > >Tests in the lab show it attenuates the jitter from the DCM by 11X to > 15X, > > > >usually down to the noise floor of 35 ps P-P. > > > >PLLs are just fine, you just need to know which ones to use, and when, > and how > > > >to use them. > > > > > > Quoting from the data sheet for an M-tron UVVJ Series LVPECL/LVDS > > > Compatible Low Jitter VCXO, for f0 in the range 20 MHz to 175 MHz: > > > > > > Phase jitter 0.35 typical/1.0 Max ps RMS Integrated 12 kHz - 20 MHz > > > > > > 0.35 ps RMS would, in engineering practice, normally be translated to > > > about 2.8 ps P-P. Many other manufacturers have similar parts/specs. > > > > > > 'nuff said. > > > > > > - Larry > >Article: 47101
I think you should try a visual tool like Viva from starbridgesystems.com. It took me an hour to convert a GCD C program over to Viva. And it will now run on an arbitrary bit length. You can't do that in C without a week of labor. "DJohn" <deepucjohn@yahoo.com> wrote in message news:am6s84$303tn$1@ID-159866.news.dfncis.de... > Hi all VHDL experts, > Is there any tools which can convert a C\C++ source file to VHDL . For > example If I have a C source code for a MP3 decoder , Can any tool can > convert it into VHDL equivalent. There is some facility in FPGA Advantage to > generate a wrapper VHDL for a C File , what exactly is that ? Does that > mean I can synthesize a C\C++ file by creating a VHDL Wrapper. > Please help > > >Article: 47102
Currently using Xilinx ISE4.2 for both the synthesis and Place and route. Is there a visualization tool for XST synthesis output? Thanks Brijesh "Utku Ozcan" <utku.ozcan@netas.com.tr.spam> wrote in message news:3D86C374.20622A07@netas.com.tr.spam... > Brijesh wrote: > > > > hi, > > > > How does one view the internal signals during post route simulation? > > Take a specific case. > > If you have a 16 bit bus and have instantiated hardware primitives > > for each bit ( Ibuf and IOB register), how can one view the registered > > values as a bus? > > Find each bit part of the signal, that is connected to your primitive(s), > in the synthesis output. It is the synthesis tool which modifies the > name of the signal. Synthesis output is normally EDIF, but if your > synthesis tool support visualization of output, it is easier to find > the signal you need. > > > Or some other internal bus, or even state variable (or register). > > The same. Synthesis tools normally change the name of the signal > to indicate optimization occur (by default). You can switch off > optimization on a signal basis, and thus you can "keep" the name > of the signal, so that you can find it in Signals Pane of your > RTL simulator. > > > I can search the particular instance within top entity and then view a > > particular bit, but is there a more easier or general way to do it? > > There is not. You have to do it manually. Some guys might have clever > scripts that match the optimized-out signal names out of the log files > of synthesis/P&R tool. > > > Specifucally for the platform: VHDL, Xilinx Device, Modelsim simulator. > > What is your synthesis tool? > > > Thanks > > Brijesh > > UtkuArticle: 47103
For an internal clock, it may be better to use a clock enable on the master 50MHz clock
rather than the derived clock.
If you're going for the lower power dissipation, you might save on the clock net power
loss if the Spartan has the clock tree selection like the more advanced devices (it's
been too long for me to remember).
The selection between a live 50MHz clock and a derived clock based on that 50MHz input
isn't ideal but is reasonable. If you really wanted close edge placement even in this
case, you could work something with posedge and negedge registers from the 50MHz clock
to derive a "replica" of the 50MHz clock with delays similar to the derived clocks. I
included a commented section to do this. It synthesizes well on Synplify but I haven't
tested the code.
The code should be very readable; the use of a module for the divide by 10 module makes
the division chain a little more obvious. The terminal counts (tc) cascade together so
that all "decade" clocks transition high at the same time.
Some lines may be broken in the post due to outgoing/incoming line wrap settings, but
this will get you a clean implementation.
- John_H
module decades ( clk_50M_in
, sel_external
, clk_external
, sel_internal
, clk_internal
, clken_internal
);
input clk_50M_in;
input sel_external; // 0 -> 50MHz, 1 -> 5kHz
output clk_external;
input [2:0] sel_internal; // 50MHz / 10**sel_internal
output clk_internal;
output clken_internal; // <- alternative form for your code to use:
// always @( posedge clk_50M_in )
wire [6:1] decade; // if( clken_internal )
wire [6:0] tc;
reg clk_div_int; // 1 clock delay for clean mux of live/div clock
reg clken_internal;
assign tc[0] = 1'b1;
divby10 clk_5M ( .div10(decade[1]), .tc(tc[1]), .clk(clk_50M_in), .en(tc[0]) );
divby10 clk_500k ( .div10(decade[2]), .tc(tc[2]), .clk(clk_50M_in), .en(tc[1]) );
divby10 clk_50k ( .div10(decade[3]), .tc(tc[3]), .clk(clk_50M_in), .en(tc[2]) );
divby10 clk_5k ( .div10(decade[4]), .tc(tc[4]), .clk(clk_50M_in), .en(tc[3]) );
divby10 clk_500 ( .div10(decade[5]), .tc(tc[5]), .clk(clk_50M_in), .en(tc[4]) );
divby10 clk_50 ( .div10(decade[6]), .tc(tc[6]), .clk(clk_50M_in), .en(tc[5]) );
always @( posedge clk_50M_in )
clk_div_int <= decade[ sel_internal ];
assign clk_internal = sel_internal==3'h0 ? clk_50M_in : clk_div_int;
assign clk_external = sel_external==1'b0 ? clk_50M_in : decade[4];
// reg tog0,tog1; // Alternative for better clock alignment with good placement
// always @( posedge clk_50M_in ) tog0 <= ~tog0;
// always @( negedge clk_50M_in ) tog1 <= ~tog1;
// assign clk_internal = sel_internal==3'h0 ? tog0 ^ tog1 : clk_div_int;
always @( posedge clk_50M_in )
clken_internal <= tc[ sel_internal ];
endmodule
module divby10 ( div10, tc, clk, en );
output div10, tc; // div10 is 50%, tc is valid 1 of 10 enables
input clk, en;
reg div10, tc_unqual;
reg [3:0] cnt;
always @( posedge clk )
if( en )
begin
cnt <= (tc ? -1 : cnt) + 1;
tc_unqual <= (cnt == 4'h8); // valid during cnt==9
div10 <= (cnt == 4'h9) | (cnt < 4'h4); // 0-4 high, 5-9 low
end
assign tc = tc_unqual & en;
endmodule
Article: 47104I don't think this is the right answer. If you open up a bitstream in a binary editor you can read the readback size by looking for the first type II command. 0x30004000 0x500------- rbsize^^^^^^ It is within the first 20 words (32-bit) Steve "Neil Franklin" <neil@franklin.ch.remove> wrote in message news:6u3csbav6x.fsf@chonsp.franklin.ch... > "Young-Su Kwon" <yskwon@vslab.kaist.ac.kr> writes: > > > Does anybody know the readback size for virtex2 devices? > > Xilinx App note 138 says only about virtex series, but I coudn't > > find any documents about readback of virtex2 devices. > > > > One more question. > > Readback methodology of virtex2 is the same with that of virtex/virtex-E? > > Both are answered, but in less detail, in: > > http://www.xilinx.com/publications/products/v2pro/handbook/ug012_ch3.pdf > > > -- > Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ > Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer > - Make your code truely free: put it into the public domainArticle: 47105
Are there any Virtex 2 pro development boards available yet, which provide Gb ethernet interfaces? Thanks. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 47106
The new Lattice isp5000MX family has on-chip PLLs (as well as a lot of other goodies). Mark On Sun, 01 Sep 2002 14:38:00 +0800, Kenneth <kenneth.lee@terapower.com.hk> wrote: >Hi Falk, > >Thanks for your reply. >I have further checked the datasheet of Coolrunner-II. Actually >they don't have clock doubler. However, it contains DualEDGE >register which allows something like DDR operation inside. As >a result, it allows a clock input which is half of your targeted >operating frequency. > >Regards, >Kenneth > > >Falk Brunner wrote: >> >> "Kenneth" <kenneth.lee@terapower.com.hk> schrieb im Newsbeitrag >> news:3D6F189F.972F1C46@terapower.com.hk... >> > Dear All, >> > >> > Currently I have a design which is quite simple and am planning to >> > implement it in a CPLD. However, the target operating speed is >> > around 300MHz. >> > >> > After searching, I found that some CPLDs from Xilinx and Lattice >> > are claimed to be able to operate at more than 300MHz. However, >> > it seems that there is no PLL/DLL inside their CPLDs. So how can >> > they operate at this high frequency? Does it mean that I need to >> >> AFAIR the new Coolrunner-II have a clock doubler inside. >> >> -- >> MfG >> FalkArticle: 47107
Hi all, Does someone know how to use CVS for revision control with Altera Quartus II? It seems that some TCL scripts are required to wrap CVS commands. Do such scripts already exist? -- SAKAKIHARA KazuyaArticle: 47108
I'm planning on using a Xilinx CoolRunner XPLA3 which requires a 3.3V supply (the datasheet says 3.0-3.6V). Would a 3V battery be okay for this?Article: 47109
I am about to use a Xilinx CoolRunner XPLA3 CPLD, and have read that the JTAG pins must be terminated using 10k pullup resistors. This is probably a silly question, but how exactly would I program the device when the JTAG pins are terminated? Is there some way of only temporarily terminating them (ie. when I'm not programming the device)?Article: 47110
The terminations aren't plugged into where you'd plug the programmer, they're on the board to establish a very weak logic level. When the JTAG programmer is active, it effortlesstly overcomes the sub-milliamps of termination current with standard logic drive capability. The 10k pullups are on board, the JTAG lines are toggling low and hisgh, the chip gets programmed. When you remove the programming cable (or ATE fixture pins) the device has no floating inputs becase the terminations are still there. John wrote: > I am about to use a Xilinx CoolRunner XPLA3 CPLD, and have read that > the JTAG pins must be terminated using 10k pullup resistors. This is > probably a silly question, but how exactly would I program the device > when the JTAG pins are terminated? Is there some way of only > temporarily terminating them (ie. when I'm not programming the > device)?Article: 47111
sounds just like me. ever heard of a lungfish? "Brad" <fpgadesign2002@yahoo.com> wrote in message news:zwah9.283$6P6.11130057@newssvr21.news.prodigy.com... > To Whom It May Concern: > I currently work for a Telecommunications company in the Bay Area doing High > Speed FPGA design. I'm not sure how much longer my company will be around, > so I wanted to see if any company here in the Bay Area could use another > designer. =) I would also be willing to do work in more of a Customer > Engineering roll, I miss interacting with customers. > Please email: fpgadesign2002@yahoo.com if there is interest. > No Visa issues (American Citizen), very good written and communication > skills. > Let's talk more if you're interested! > Thanks, > -- > Brad > > > >Article: 47112
Rick Filipkiewicz wrote: > > Leon Qin wrote: > > > any one knows? > > And if it has are there any "user experiences" yet ? Placer/Router are > worse:same:better than 4.x? I have a pre-release copy. Placer/router is much faster, uses less memory, but doesn't do as good of job, based on one design. Production release might be different. Your design may be as well. Careful types might want to wait for service pack one. -- Phil HaysArticle: 47113
Hi, I'd like to implement adaptive FIR filter with 100 tap in FPGA. To implement this, I need 100 multiplier to multiply weight. How to measure the area(or gate?) to measure this filter so that I can find appropriate chip? Thanks in advance for your response. -Regards donghoArticle: 47115
Normally you have to follow the specification ! On our Chameleon POD (CPLD Development board in a dongle format), we tested and ran the Coolrunner XPLA3 CPLD at 2.8V. All was OK at 2.8V ! ... But, for industrial product, respect the Xilinx specification! Laurent Gauch, Amontec http://www.amontec.com John wrote: > I'm planning on using a Xilinx CoolRunner XPLA3 which requires a 3.3V > supply (the datasheet says 3.0-3.6V). Would a 3V battery be okay for > this? >Article: 47116
I found that MAP/PAR is much more powerful, example 4.x 3hours running time 2 constraints not met versus 5.1 0.5 hours running time, all constraints are met. But: it is difficult to set a 4.x project to 5.1 because you have to recompile all the coregen generated modules. After that it turned out that the design needs 30% more space. We finally used the synthesis of the 4.x with the .ngc file and run the ngdbuild, map, par with a batch routine. I think the projectmanger should allow 'ngc' only projects as it does allow 'edif' projects to deal with older projects. Further I saw a PAR abnormal program termination with the design, when I invert a certain enable signal in the vhdl design and recompile its ok. Anyone has more experience ? Regards AndreasArticle: 47117
Hi, I'm wondering whether Xilinx(or 3rd party) provide an IP linear-log converter function. I'm specifically after a 32-bit linear (input) to 8-bit log (output) converter. Any help appreciated. tks Jason.Article: 47118
On 17 Sep 2002 22:17:39 -0700, dhan@ecel.ufl.edu (Dongho) wrote: >Hi, > > I'd like to implement adaptive FIR filter with 100 tap in FPGA. > To implement this, I need 100 multiplier to multiply weight. > How to measure the area(or gate?) to measure this filter so that I >can find appropriate chip? >Thanks in advance for your response. > >-Regards > >dongho In addition to 100 multipliers in the forward path, you also need a multi-input adder which adds the results of these multiplications. A 100 input adder is probably much larger and slower than any of the multipliers. Also don't forget that you need another 100 multipliers in the feedback path too. For the size of the adaptive filter you seem to want the direct form of FIR implement may not be a good choice. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 47119
Is it true that the last release of the ISE software doesn't work on Windows NT4.0 sp6 ? Thank you Giuseppe -- .Article: 47120
I would avoid using the (combinatorical) output of one devider stage as a clock for the next one, If you do this you have to look at the clock skew of all those clock nets. Your devider counters may not function proper if there is a skew on the clock. The only solution that works worst case is a syncronous design, all running with the highest clock and the devider modules provide a CE for the next stage. The CE should be generated with Look Ahead and a FF. Regards AndreasArticle: 47121
Hi all,
I am designing on XCV600 and I have to use an GCLK input as a standard
input.
On VCV600 we have 4 IBUFG
My design uses 3 GCLK pins for 3 different clocks, these 3 GCLK pins are
directly connected to 3 IBUFG.
I divide one of my 3 Clocks by two via a Flip-flop (I cannot use DLL
part because I have to produce an ASIC of this design and the customer
don't want specific logic). The result of this division is connected to
a IBUFG too.
Now my problem is to connect and to use my last GCLK pin like a standard
input.
Is There a way to use a GCLK pin without passing through an IBUFG. If
yes, which constraint will do that for me.
From Foundation 3.2 I received the following message:
Section 1 - Errors
------------------
ERROR:Pack - Unable to pack the following symbols concurrently into an empty
IOB component:
PAD symbol "TSYNC.PAD" (Pad Signal = TSYNC)
BUF symbol "TSYNC_ibuf" (Output Signal = TSYNC_int)
The symbol TSYNC.PAD has a constraint (LOC=AK16) that specifies an
illegal
physical site for the component. Please correct the constraint value.
The TSYNC signal arrive on AK16 (my last GCLK pin), but I have to use
this signal as a 'enable' signal and not as a clk.
Thanks in advance for all advices
Laurent Gauch, Amontec
http://www.amontec.com
Article: 47122Hi all, I use a Xilinx XC4010XL FPGA. Before programming the FPGA I need to precisely know the state of all its I/O pins. Where can I find this piece of info? I have looked in the relative FPGA datasheet but there is no such info. Please advise. thanks in advance! StamatisArticle: 47123
Hello, for configuration purposes, I have to connect a PC to my FPGA board. It's a Spartan2 device. PC must write, not read. My idea is to connect 8bit data, strobe and busy lines to the FPGA and serve the PC with usual line printer handshaking. This is so fundamental, that I'm quite sure someone did this before. I'm interested in VHDL code or Simulink/SystemGenerator source which either gives me hints or (best case) does the job of handshaking and storing the received data into a memory/buffer/fifo inside the FPGA. Thanks in advance Bernhard -- before sending to the above email-address: replace deadspam.com by foerstergroup.deArticle: 47124
Since I started this suggestion of using ripple clocks, I might as well answer: The clocks are not combinatoril outputs, they are the MSB flip-flop in each decade. Clock skew between nets is not an issue, since this is a ripple design. Every downstream clock is inherently later than the upstream clock, and the delay is irrelevant. The only concern would be that each clock must reach its four flip-flops "simultaneously", i.e. with less skew than the clock-to-out plus set-up. Since the four flip-flops fit naturally in one CLB, this is not an issue. Unconventional? Yes. Unreliable? No. And simple to design and low power. Not good for every application, but good for some. Peter Alfke, Xilinx Applications Andreas Loew wrote: > I would avoid using the (combinatorical) output of one devider stage as a clock for the next one, If you do this you have to look at the clock skew of all those clock nets. Your devider counters may not function proper if there is a skew on the clock. The only solution that works worst case is a syncronous design, all running with the highest clock and the devider modules provide a CE for the next stage. The CE should be generated with Look Ahead and a FF. > Regards > Andreas
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