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"MM" <mbmsv@yahoo.com> wrote in message news:bvr63s$vm2au$1@ID-204311.news.uni-berlin.de... > If you want your emulator to be pluggable into a standard PC, then the most > obvious choice for the interface is PCI. With standard 32 bit 33 MHz PCI you > can theoretically achieve 132 MByte/s. In practice I have achieved over 100 > MByte/s. If this is not enough you can go to 64 bit / 66 MHz PCI, which is > pretty common nowadays too. To achieve high speeds on PCI bus your emulator > would have to be a bus master for both reads and writes. The next step in > performance is PCI-X, but I don't think it is wide spread among PC > motherboards... > > Another way is to make your card look like a memory module. I think this > approach was discussed here in the past. This seems like an interesting > idea, but personally I prefer staying with standard interfaces. > > Then there are all kinds of fast serial buses, but if I were you I wouldn't > go there for this application. Thank you, Mihail. I'm aware about these opportunities and would like to know more. Looking for overviews, tools and step-by-step methodologies.Article: 65676
I would suggest isolating the block and making sure you are able to simulate the VHDL netlist in ModelSim using the automated testbench and script generated by Signal Compiler. You should also submit your design to the technical support group (mysupport.altera.com) in order for us to debug this problem further. -HS hneoh@altera.comArticle: 65677
Yes I allready send a request to the mySupport system at Altera, but now it seems I will have to cancel it, because I had connected the sclrp connection to the block wrong in the Quartus design, just found out last night. I am new to this, so there is many more mistakes to be made yet. Thanks for the advice. /Jacob >>>>> "Hong" == Hong Shan Neoh <hsneoh@netscape.net> writes: Hong> I would suggest isolating the block and making sure you are able Hong> to simulate the VHDL netlist in ModelSim using the automated Hong> testbench and script generated by Signal Compiler. Hong> You should also submit your design to the technical support Hong> group (mysupport.altera.com) in order for us to debug this Hong> problem further. Hong> -HS hneoh@altera.com -- Msg. From Jacob Soerensen jacob@jacob-s.net http://jacob-s.net Nothing in nature is random ... A thing appears random only through the incompleteness of our knowledge. Spinoza, Ethics IArticle: 65678
In the FPL03 international conference a paper was presented that described the Xilinx Partial Reconfiguration Toolkit, this API allowed Virtex II pro embedded applications to perform dynamic partial reconfiguration without requiring external circuit. This appears to be a simple port of JBits API to work in an embedded system. I am trying to find out if this API is going to be released by Xilinx, in a similar form as JBIts, and when this is going to happen. Can anyone help me?Article: 65679
Virtex II and Virtex II Pro allow internal reconfiguration through the ICAP module, the application note XAPP662 as an example that shows how this could be doneArticle: 65680
Hi Fredrik, Are these numbers for a 32-bit Nios with hardware multiply? -- Pete fredrik_he_lang@hotmail.com (Fredrik) wrote in message news:<77a94d51.0402040058.38e476c9@posting.google.com>... > Hi Jim > Jim Granville <no.spam@designtools.co.nz> wrote in message news:<14XTb.20607$ws.2742532@news02.tsnz.net>... > > snip. > > Anyone seen actual numbers or NIOS or NIOS II ? > > > > -jg > I did a quick compile in Quartus2_ver4 with Stratix2 and Stratix same > Nios design only changed parts. Results in ALUT's compared to LE's is > 3202 ALUT (S2) and 4522LE's (S). Push button compile of design no > tweaking no logiclock. > Cheers > FredrikArticle: 65681
Hi Bob, I have been using Nios with great success in a product destined for commercial use. The tools are fairly mature. Nios is instantiated within Altera's SOPC Builder, which automatically builds a interconnect fabric so that Nios can talk to whatever on-chip/off-chip peripherals you like. Nios comes with GNU tools including a GUI debugger. The debugger does all the things you mention. It runs in emulation though and is therefore a little slow on my system. It also has the OCI debug core which I have not used. I do not use an IDE for development, I'm in the dark ages in that respect, writing my programs in Vim, etc. Altera just announced Nios II, which I would consider for future designs. I hear it is coming with a nice IDE. -- Pete "Robert Davis" <rkd0930@comcast.net> wrote in message news:<5HSSb.150064$sv6.835853@attbi_s52>... > Hi All, > > In my work, I develop high speed counting and measuring systems. Our > systems typically use FPGAs for high speed digital logic and a > microcontroller for control and calibration. To reduce costs, power and > space, I have been looking at the idea of implementing the microcontroller > function into the FPGA using either Microblaze or Nios. Does anyone have > experience with these two products? Have you used them in a commercial > product? Are these IP cores and the software to implement them mature > enough to be practical and reliable? How good is the software development > environment for code that runs on the synthesized microcontroller. Do it > include breakpoints, single stepping and examination of register and memory > variables? I would like to hear anyones experience with Microblaze and > Nios. > > Thanks, > Bob DavisArticle: 65682
If you have clock glitch problems, and cannot resolve them by proper attention to board-level signal integrity methods ( which you should! ), then there is always a band-aid method to make the problem vanish. A few years ago, I published a way to suppress clock glitches, which has saved several designs alreay: http://www.xilinx.com/xcell/xl34/xl34_54.pdf Peter Alfke, Xilinx Applications ============================ Pascal Chamberland wrote: > > Your problem reminds me of a problem I had a while ago. The FPGA > locked up just your CPLD was doing. By digging a bit, I found that ISE > had implemented my state machines as one-hot so I thought that somehow > the FSM had gone into an illegal state. Forcing the FSM to binary > encoding reinforced my belief. > > To shorten the story, it turned out the FPGA wasn't really going into > an illegal state: the problem was that there was poor signal integrity > on the clock signal, which occasionally would have a double edge, > causing the bit in the one-hot encoding to be lost. > > You might want to check out the clock after looking at the Vcc.Article: 65683
Hello, > i would like to know that how can i obtain a vendor id in brief > read the value at the base of config space. > > I know that we had to write to CONFIG_ADDRESS register and read > from CONFIG_DATA register... but how to read that The mechanism you describe is the low-level way of turning a memory space or I/O space access from a processor into a configuration cycle on the PCI bus. If you want to know how to do this, you will need to get the documentation on the host bridge chipset you are using. In most PC systems, I am sure these registers always show up at the same address, but you don't mention what system you are working with. You only want to do this if you are writing a BIOS that does the bus enumeration, or if you are writing an operating system from scratch. If you are writing an application, you will want to use existing, higher level services to scan configuration space. EricArticle: 65684
Yes, this is definitely possible using a variety of Xilinx FPGAs. Xilinx uses the term partial reconfiguration for what you're asking for, I think. Please visit the following FAQ as it probably answers most of your questions. http://www.xilinx.com/ise/advanced/partial_reconf_faq.htm --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC "Jelly" <andrew.freeborough@hiscox.com> wrote in message news:d2e8b58e.0402040751.5fa1d46f@posting.google.com... > Hi, Is it possible to reconfigure an FPGA from 'within' the FPGA at > runtime, without any need for an external system to do this? I would > like to make a design that can create/remove 'components' at runtime. > > Do all/any of the mainstream chips support this (Xilinx, Altera)? > > Does anyone have any experience of doing this? What is the > performance like? What impact does it have on the overall system? I > was thinking that a core would remain constant, and pre-defined areas > would be dynamically changed as required. > > Also, is there any available software that will support/simulate this > functionality? Preferably something that I could afford (personal > hobby project) would be good! > > I'm sorry if this is a bit of a newbie question. I have had a good > dig around for answers, but not found anything other than hints that > this can be done. Maybe. I'm looking at doing some GP work with > FPGA's, as I only discovered they even existed a few days ago, and > they seem suited to GP work. > > Any help would be appreciated. Thanks in advance, > > - Jelly. > > "Beware of the Leopard!"Article: 65685
Hi Kelvin, did you ever get that problem fixed, or find out something new about it? I get the same error, and the strange thing is that the signal is definitely WITHIN module boundaries when I look at the corresponding .NCD. Plus, I'm using some generated cores inside this module and hence have no way of changing anything about any of the GLOBAL_LOGIC-signals... > Hi, there: > > I am performing partial reconfiguration tutorial. How do I fix this error in > the final assembly stage? > Starting Guide File Processing. > > Loading device database for application Par from file > "../../pims/iq_gen/iq_gen.ncd". > "sig_gen" is an NCD, version 2.38, device xc2v250, package fg256, > speed -4 > The STEPPING level for this design is 1. > FATAL_ERROR:Guide:basgitaskphyspr.c:255:1.28.20.2:137 - Guide encountered a > Logic0 or Logic1 signal GLOBAL_LOGIC1_32 that does not have a driver or > load within the module boundary.Article: 65686
I have an Atmel AT94K40 FPGA and I need to synthesize (by writing VHDL) a dual clock FIFO (a FIFO with different read and write clock). The problem is that the Atmel macro-generator has the ability to generate only single clock FIFO. Is it possible that Atmel did not think to include the possibility of creating dual clock FIFO's in an efficient way??? Have I to design a FIFO by myself with "glue logic"?? In this way I could not use the "FreeRAM" feature of the FPGA, and the resource use would be critical. Just to simulate my design, now I'm using a dual clock FIFO created with the Altera macro generator, which uses a LPM_FIFO block. Do you think I could try to synthesize this LPM_FIFO block in Atmel FPGA? -- Per rispondermi via email sostituisci il risultato dell'operazione (in lettere) dall'indirizzo -*- To reply via email write the correct sum (in letters) in the email addressArticle: 65687
Hi Robert, Robert Davis wrote: > Thank you Antti. You have given me a lot of useful information. We > currently use the XC2S200, but I am looking at moving to a larger part, > maybe a Spartan 3 when the becomes available. Anyway thanks again. Can any > one else share your experience with Microblaze or NIOS. My experience is solely with microblaze - porting the uClinux kernel (you can read all about it at http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux), so I can't really comment on NIOS. WRT microblaze, it too uses a gcc-based toolchain for software development (including gdb and Insight graphical front end for debugging), and command line tools to assemble the hardware system (processor, buses, peripherals etc). These tools integrate with the standard Xilinx synthesise and implementation tools. There is a GUI/IDE bolted on the front of this, if that's more your style. I do all my development (software and hardware) at the command line, but I find the GUI useful for generating system "templates" which I then specialise according to my needs. Currently the EDK (embedded development kit) only runs on Windows and Solaris, but as of 6.2 (due in a few months), Linux should be supported through the entire flow. Personally I think that microblaze is a very sleek little processor - it is very tightly targeted to the xilinx fpga technology. Running systems at 100 MHz is common, and up to 125MHz is possible under certain conditions and on certain devices. Instruction and data caches (using Xilinx BRAM cells) improve performance dramatically. The instruction set is very RISC, and easy to write. The gcc-based toolchain is complete, and largely bug free (I've found more than a few for them in the last 12 months!). The tools (both h/w and s/w) improve significantly with each successive release. Microblaze has a very cool little feature called FSL - fast simplex links. These are unidirectional, point to point buses (really just data pipes), with built-in FIFOs, that bolt right into the heart of the processor, with direct register access. The hardware interface is also very simple, so these are great for applications that require streaming data, and when you don't want the full weight of a 32 bit address + data bus. FSL is a bit of a sleeper - people haven't really caught on to it yet, but when they do it will have a great impact. I note recently that Antti has posted about his experiences with FSL, and he's caught the bug too! One final comment I will make, and I expect this applies equally to NIOS, is that the tools make a great effort to protect you from what is, underneath it all, a very complicated process. I've learned this recently when trying to do some things off the beaten path. The implication is that if you want to step outside the boundaries of the anticipated development flow, you must be prepared to do the hard yards to get there. I expect that 95% of users are perfectly well served by the pushbutton approach. For the other 5% - well, there's always this newsgroup! Hope this is useful to you. Regards, JohnArticle: 65688
A dual (uncorrelated) clock FIFO is infinitely more complex and tricky than a single clock FIFO, which is just a synchronous state machine. If theFIFO needs to run fast, then you need a dual-port RAM. The problem with two asynchronous clocks is in the reliable detection of FULL and EMPTY under all possible phase relationships of the two clocks. See the Xilinx website for some ideas. Peter Alfke, Xilinx ============== "Fabio G." wrote: > > I have an Atmel AT94K40 FPGA and I need to synthesize (by writing VHDL) > a dual clock FIFO (a FIFO with different read and write clock). > The problem is that the Atmel macro-generator has the ability to > generate only single clock FIFO. > Is it possible that Atmel did not think to include the possibility of > creating dual clock FIFO's in an efficient way??? > Have I to design a FIFO by myself with "glue logic"?? In this way I > could not use the "FreeRAM" feature of the FPGA, and the resource use > would be critical. > Just to simulate my design, now I'm using a dual clock FIFO created with > the Altera macro generator, which uses a LPM_FIFO block. Do you think I > could try to synthesize this LPM_FIFO block in Atmel FPGA? > > -- > Per rispondermi via email sostituisci il risultato > dell'operazione (in lettere) dall'indirizzo > -*- > To reply via email write the correct sum (in letters) > in the email addressArticle: 65689
ytregubov@yahoo.com (Yuri Tregubov) wrote in message news:<9d3de6a0.0402030449.1f0fcf0d@posting.google.com>... > The ByteBlaster works fine with MaxPlus 9.4 / Windows 95 but fails > with MaxPlus 10.2 / Windows 98. > > "Unrecognized device or socket is empty" Isn't this an error message for the MPU programmer? Are you sure you are configured to use a ByteBlaster? (in the Options/Hardware Setup menu) Alan Nishioka alann@accom.comArticle: 65690
"Fabio G." <9+3@supereva.it> skrev i meddelandet news:40216cd1.24157170@powernews.libero.it... > I have an Atmel AT94K40 FPGA and I need to synthesize (by writing VHDL) > a dual clock FIFO (a FIFO with different read and write clock). > The problem is that the Atmel macro-generator has the ability to > generate only single clock FIFO. > Is it possible that Atmel did not think to include the possibility of > creating dual clock FIFO's in an efficient way??? > Have I to design a FIFO by myself with "glue logic"?? In this way I > could not use the "FreeRAM" feature of the FPGA, and the resource use > would be critical. > Just to simulate my design, now I'm using a dual clock FIFO created with > the Altera macro generator, which uses a LPM_FIFO block. Do you think I > could try to synthesize this LPM_FIFO block in Atmel FPGA? > The Leonardo synthesizer is normally smart enough to realize what you want to do if you describe a FIFO in HDL so it will use the FreeRAM which is Dual Port. You can always instantiate the DPRAM and then generate stuff around it. If/When you are stuck, fpslic at atmel dott com provides help -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This is a personal view which may or may not be share by my Employer Atmel Nordic ABArticle: 65691
Hi, What I've done in the past is this. Get your noisy clock into the FPGA, call it CLKA. Feed it through spare unbonded IOBs with the input delay feature turned on to make a delayed version, CLKB. Make the delay longer than the glitch time by using as many IOB delays as necessary. Now make two signals, SET <= CLKA and CLKB; RESET <= not(CLKA) and not(CLKB); Use SET to set a latch and RESET to reset it. The output of the latch is your debounced clock, which you feed to your circuit. Disgusting but effective. Cheers, Syms. Peter Alfke <peter@xilinx.com> wrote in message news:<40214E57.192B79B2@xilinx.com>... > If you have clock glitch problems, and cannot resolve them by proper > attention to board-level signal integrity methods ( which you should! ), > then there is always a band-aid method to make the problem vanish. A few > years ago, I published a way to suppress clock glitches, which has saved > several designs alreay: > > http://www.xilinx.com/xcell/xl34/xl34_54.pdf > > Peter Alfke, Xilinx Applications > ============================Article: 65692
"Paul" <paulw@mmail.ath.cx> wrote in message news:3ba4d769.0402011550.40822b7@posting.google.com... > Hi > > Anyone have "binary file" to "bram" tool (to verilog and constraints files)? > Thanks on www.fpgaarcade.com in the vice-20 / pacman project there is a tool + source for generating VHDL blockrams with init attributes. Might help. /MikeJArticle: 65693
Hi Paul, > Anyone have "binary file" to "bram" tool (to verilog and constraints files)? You'd be looking for the Xilinx tool called data2bram.. :) It comes as part of ISE Here's a very helpful document about it, strangely not linked on the Xilinx website (I found it with google). It's similar to the ISE doco, but has more detail: http://www.xilinx.com/ise/embedded/data2bram.pdf Regards, JohnArticle: 65694
raghurash@rediffmail.com (Raghavendra) wrote in message news:<1776d39.0401290453.3bd7cbe9@posting.google.com>... > Hi All, > How to manually estimate dynamic power consumption of the design in the FPGA? > Thanks in advance, > Raghavendra.S Raghavendra, When using Altera parts, you have a few options: 1. This web page: http://www.altera.com/support/devices/dvs-timing_power.html shows the various online calculators that we have for our devices. These are spreadsheet-based; you enter information about your usage of the device, such as fmax, LE count, IO standard used, and so forth. It reports your power consumption, and also gives some information about whether the package you have chosen can dissipate the heat that will be generated. 2. Quartus II software generates a file based on your design which includes the info needed to populate the spreadsheet. If you have already compiled your design, you do not need to manually enter the info, instead you can just take the file from Quartus II. This procedure is explained in the "Early Power Estimation" chapter of the Quartus II Handbook: http://www.altera.com/literature/hb/qts/qts_qii53006.pdf 3. Quartus II software includes a simulation-based power estimation tool. This takes your simulation vectors into account when estimating power. This tool is described in the "Simulation-based Power Estimation" chapter of the Quartus II handbook: http://www.altera.com/literature/hb/qts/qts_qii53007.pdf Sincerely, Greg Steinke Altera CorporationArticle: 65695
Hi Ken, Stratix II was announced this week. You can find out all about it at www.altera.com/stratix2. To answer your questions: The "equivalent LE" counts are representative of what the typical user will experience moving an existing Stratix design to Stratix II, as measured on a suite of real user designs. The ratio is based on an average, and since the logic architecture has changed significantly, the exact number of Stratix II ALUTs compared to Stratix LEs will vary somewhat from design to design. I'd strongly suggest reading the "Stratix II Performance and Logic Efficiency Analysis" white paper available on our web site (http://www.altera.com/literature/wp/wpstxiiple.pdf). It gives a (real, experimentally determined) histogram of relative logic density between Stratix and Stratix II, plus a lot of useful details on what the ALM can do. I cannot comment on pricing; I'm an engineer and as such I only understand numbers that don't have $ in front of them. As for Cyclone II, Nios II, and MAX II, we have not publicly disclosed much more than cheaper/faster/better, which you could probably tell from the "II" in the names. I don't know what was disclosed at SOPC World -- your Altera rep may be able to fill you in. Please see http://www.altera.com/corporate/overview/roadmap/ovr-product_roadmap.html for a description of our 2004 road-map, and stay tuned for announcements about these exciting products! Regards, Paul Leventis Altera Corp. "Ken Land" <kland1@neuralog1.com> wrote in message news:10227rrepmu5vd0@news.supernews.com... > I wasn't able to attend SOPC World. (really wanted to) > > Can anyone share info from Altera's roadmap for these products? I'm working > on a commercial product with the Cyclone and Nios and look forward to even > more of this amazing technology. > > Also, a question about the pricing of Stratix I vs. II. > > Is the 40% lower price a marketing number or a real number? I mean are they > playing games with equivalent LE's vs. ALUT's or will the roughly equivalent > chips really be 60% of the current price?(what's $200 now will be $120) > > I ask because a 40% discount would bring the SII into the price range for > our products, and I'd love to have the DSP features. Or will the Cyclone II > get some of this? > > TIA, Ken > >Article: 65696
Hi, I want to make a custom PS/2 keyboard. I have a Xilinx SpartanII part on my custom keyboard and I am looking to implement a PS/2 keyboard interface so that I can plug my custom keyboard into a standard PC PS/2 port. Googling for an opencore has so far been fruitless. I've tried opencores.org, but they only have a PS/2 keyboard interface that would be implemented on the host side (not keyboard side). Verilog is my preferred HDL. Thanks for any help, Jason.Article: 65697
On Wed, 4 Feb 2004 08:48:31 +0100, "Giuseppe³" <miaooaim.REMOVETHIS@tiscali.it> wrote: ><CUT> >> >> Get a better news reader. A good one d/l's the message only once, >> keeping tabs on the message id so if you see it in one group it won't >> show in the others unless you tell it you want to. >> >> - YD. >> > >Which kind of NewsReader do you to suggest or you are using? > >Thank you >Giuseppe > I mostly use Forté Agent but I've heard good things about xnews. On Linux/BSD I prefer slrn. Hope this doesn't start a religious war, people tend to be tribal about their readers. - YD. -- Remove HAT if replying by mail.Article: 65698
On Wed, 04 Feb 2004 14:16:29 +0200, valentin tihomirov wrote: > I'm trying to be very specific telling that the target application is > simulations accelerator. The higher speed the better. As converter will be > running on FPGA, this limits number of vectors per second that can be > simulated to about 200MHz. Hence, the desired bandwidth is > number_of_vectors_per_second * vector_width gives about 100Mbps..10Gbps (for > both channels). Channels should not be symmetric (input can be faster than > output or vice versa). I just want to discover existing PC-interfacing > solutions, make a broader view in the field. > > Rather than doing conversion task in SW it is often more desirable to use a > task specific HW. All kinds of FPGA-based accelerators are becoming more and > more popular. I've even seen about universal FPGA-accelerators. Data > converter is a simplest accelerator; its communication scheme includes only > one input and one output stream. The simulator I would like to implement > belogns to data conversion class as well. I have mentioned > compression/encription asking for typical reference design of data > converter. Thanks. 10 Gbps is pretty fast. The only way to get data in or out of a PC at that speed is to use the memory bus. Typical PCI is a little over 1 Gbps (theoretical). If you go 64-bit 66 MHz PCI, that is only 4 times faster at 4 Gbps. Maybe PCI-X is fast enough for you. If you are using an FPGA, why don't you see if the FPGA vendor can fix you up with a 133 MHz PCI-X core? Good luck! MacArticle: 65699
Sean: I saw Kamal Patel sent a message to our inbox. I couldn't get a definitive explanation for that error. I coded many varieties and flavors for my design, finally some of the pool passed without this error (& other errors), however I am not sure whether constants caused this error. I found that at the final assembly stage, when I removed the "Closed" constraint in the Place & Route on the fixed module. And then my design ran without errors. My design was so complicated and had many many top level clock buffers and DCMs...Though I am not sure whether this trick work until the testing is out... Best Regards, Kelvin Sean Durkin <smd@despammed.com> wrote in message news:bvro89$vsg7q$1@uni-berlin.de... > Hi Kelvin, > > did you ever get that problem fixed, or find out something new about it? > > I get the same error, and the strange thing is that the signal is > definitely WITHIN module boundaries when I look at the corresponding > .NCD. Plus, I'm using some generated cores inside this module and hence > have no way of changing anything about any of the GLOBAL_LOGIC-signals... > > > Hi, there: > > > > I am performing partial reconfiguration tutorial. How do I fix this error in > > the final assembly stage? > > > Starting Guide File Processing. > > > > Loading device database for application Par from file > > "../../pims/iq_gen/iq_gen.ncd". > > "sig_gen" is an NCD, version 2.38, device xc2v250, package fg256, > > speed -4 > > The STEPPING level for this design is 1. > > FATAL_ERROR:Guide:basgitaskphyspr.c:255:1.28.20.2:137 - Guide encountered a > > Logic0 or Logic1 signal GLOBAL_LOGIC1_32 that does not have a driver or > > load within the module boundary.
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