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Rene Tschaggelar <none@none.net> writes: > Some pricetags would help too. The license restrictions would Xilinx ISE Foundation http://tinyurl.com/3745h Altera Quartus II http://tinyurl.com/34ctk Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 65576
Most likely, you failed to properly constrain the timing on some path in the
design. It is also possible that there is a problem in your clock domain
crossings (you usually need something along with the memory used for the data
path to tell the other side there is valid data). If you have multi-cycle
constraints in the design, that would be the first place I looked, good chance
that something is getting interpreted for multi-cycle when it shouldn't. You
shouldn't need multi-cycle constraints on a 50 MHz design though. Also, check
with your IP provider to make sure his design is really meeting timing and is
properly constrained.
MM wrote:
> I have a design, which is supposed to work in XC2V2000-5 at 50 MHz. The
> timing analyzer reports the clock period to be below 19ns. However, in
> practice, only one device out of 3 works at this speed. Two others were
> happy when I slowed the clock to 45 MHz (I didn't try any intermediate
> frequencies). The design basically consists of a 3rd party IP core, for
> which I don't have a source (I believe it was designed in schematic), some
> state machines, a bus interface and some Coregen memories. The bus runs at
> slower clock, but it is fully decoupled from the IP core (through the
> memories). The IP core is a fully synchronous design according to its
> author. The clock comes directly from an external crystal oscillator. I
> tried looking at unconstrained paths in the timing analyzer, but couldn't
> see anything suspicious...
>
> Any ideas to where to look?
>
> Thanks,
> /Mikhail
>
> --
> To reply directly:
> matusov at square peg ca
> (join the domain name in one word and add a dot before "ca")
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 65577
Single piece. Check Avnet. Their single piece prices currently range from about $16
to around $40 for the XC2S100 depending on package and speed grade.
Hul Tytus wrote:
> Is that $18.00 per single piece or $18.00 per 250,000 pieces?
>
> Ray Andraka <ray@andraka.com> wrote:
> : Jean, neat website. In your post you should probably have said that the pluto
> : board is your board. I added a link from my links page to your site.
> : The Burch board is also one of the lower cost ones, but is still beyond the $50
> : budget. There is a fairly comprehensive list of boards at www.optimagic.com.
> : Jean, you may want to send them a note with details and a link to your board.
> :
> : The Xilinx spartan2 and altera acex parts can be had for not much more than a
> : song ($10-20 USD), and these have enough gates to do some pretty cool things.
> : For example, I used an $18 spartanII chip to demo a shortwave radio implemented
> : entirely in an FPGA except for the A to D converter and antenna (there is a
> : block diagram on the front page of my website). Unfortunately, it does cost a
> : bit of money to make a board that is going to be robust enough to work under
> : hobbyist conditions and provide all the hooks to make it useful. The insight
> : spartan2 board I used ran a tad over $100 USD, which is more or less the low
> : end. The Burch board, and Jean's Pluto boards are about all that you'll find
> : cheaper.
> :
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 65578
Austin,
"Austin Lesea" <austin@xilinx.com> wrote in message
news:bvmga9$et43@cliff.xsj.xilinx.com...
> MM,
>
> The most likely cause is that your design does not, in fact, meet
> timing. This comes about by many ways, most usually a bug in the
> constraints, or in the design itself.
I agree. However, it is not one of the basic things such as clock not using
global resource. Here are the relevant parts of the PAR report:
+----------------------------+----------+--------+------------+-------------
+
| Clock Net | Resource | Fanout |Max Skew(ns)|Max
Delay(ns)|
+----------------------------+----------+--------+------------+-------------
+
| clk50_bufgp | Global | 2655 | 0.314 | 1.330
|
+----------------------------+----------+--------+------------+-------------
+
| lclk_bufgp | Global | 600 | 0.300 | 1.316
|
+----------------------------+----------+--------+------------+-------------
+
----------------------------------------------------------------------------
----
Constraint | Requested | Actual |
Logic
| | |
Levels
----------------------------------------------------------------------------
----
TS_clk50 = PERIOD TIMEGRP "clk50" 19 nS | 19.000ns | 18.977ns | 16
HIGH 50.000000 % | | |
----------------------------------------------------------------------------
----
TS_lclk = PERIOD TIMEGRP "lclk" 26 nS | 26.000ns | 13.491ns | 6
HIGH 50.000000 % | | |
----------------------------------------------------------------------------
----
PATH "FROM DFFS_GRP TO EFFS_GRP" TIG | | 19.159ns | 6
----------------------------------------------------------------------------
----
* TIMEGRP "LAD" OFFSET = OUT 13 nS AFTER C | 13.000ns | 22.516ns | 7
OMP "lclk" | | |
----------------------------------------------------------------------------
----
TIMEGRP "LAD" OFFSET = IN 16 nS BEFORE C | 16.000ns | 11.499ns | 4
OMP "lclk" | | |
----------------------------------------------------------------------------
----
TIMEGRP "LBUS_CTRL" OFFSET = OUT 13 nS A | 13.000ns | 12.808ns | 1
FTER COMP "lclk" | | |
----------------------------------------------------------------------------
----
TIMEGRP "LBUS_CTRL" OFFSET = IN 16 nS BE | 16.000ns | 10.185ns | 3
FORE COMP "lclk" | | |
----------------------------------------------------------------------------
----
1 constraint not met.
All signals are completely routed.
Total REAL time to par completion: 11 mins 17 secs
Total CPU time to par completion: 11 mins 12 secs
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - 32 errors found.
The one constraint that has not been met is not relevant to the problem.
There are no multi-cycle constraints. I realize that from the information I
am giving it is almost impossible to conclude anything. I guess what I am
looking for is any information on what might be uncovered by the clock
constraint in a supposedly synchronous design. I believe that the problem
happens in the 3rd party IP core, which uses only 50 MHz clock, but without
source code I don't know how to find where. So instead of finding the
problem in the core I would like to be able to constrain it somehow that it
will work...
BTW, I am using ISE5.2.03i...
Thanks,
/Mikhail
--
To reply directly:
matusov at square peg ca
(join the domain name in one word and add a dot before "ca")
Article: 65579Austin Lesea wrote: > Shiraz, > > Idle speculation on the part of over-anxious authors? > > Austin I'm left puzzled as to why they should be anxious ? Maybe over-excited, or over-hyped, but anxious ?! The cited reason for the ASMBL early info release is to 'create interest'. Well, Ok, it's done that...... Now, imagine this : Interest generates questions, and when those questions are given a 'wait and see' reply, that interest changes to annoyance and frustration, and the market droids 'clever idea' morphs into one needing damage control... Still, those looking for hard info on future FPGA directions could, of course, pop over to http://www.altera.com/products/devices/stratix2/st2-index.jsp -jgArticle: 65580
Jim,
anxious -
"1. Uneasy and apprehensive about an uncertain event or matter; worried.
2. Attended with, showing, or causing anxiety: spent an anxious
night waiting for the test results.
3. Usage Problem. Eagerly or earnestly desirous.
[From Latin nxius, from angere, to torment. See angh- in Indo-European
Roots.]anxious·ly adv.
anxious·ness n.
Usage Note: Anxious has a long history of use roughly as a synonym
for eager, but many prefer that anxious be used only when its subject is
worried or uneasy about the anticipated event. In the traditional view,
one may say We are anxious to see the strike settled soon but not We are
anxious to see the new show of British sculpture at the museum.
Fifty-two percent of the Usage Panel rejects anxious in the latter
sentence. But general adoption of anxious to mean “eager” is
understandable, at least in colloquial discourse, since it provides a
means of adding emotional urgency to an assertion. It implies that the
subject so strongly desires a certain outcome that frustration of that
desire will lead to unhappiness. In this way, it resembles the informal
adjective dying in sentences such as I'm dying to see your new baby."
http://dictionary.reference.com/search?q=anxious
Austin
Article: 65581Anyone know the difference between LVDS_25 and BLVDS_25 in Xilinx's Virtex II Pro or point me to a spec. where I can read about the electrical characteristics of these two? Searching through Xilinx.com has yielded zero. [When I set IOSTANDARD=BLVDS_25 for some of my differential (OBUFDS) outputs, I get an Exception during mapping in Xilinx's ISE 6.1.03i. LVDS_25 works fine for all my differential I/O, so I'm wondering whether I can get away with using LVDS_25 instead.] -- ø¤º°`°º¤ø,,,,ø¤º°`°º¤ø,,,,ø¤º°`°º¤ø,,,,ø¤º°`°º¤ø¤º°`°º¤ø,,,,ø¤º eNo ø¤º°`°º¤ø,,,,ø¤º°`°º¤ø,,,,ø¤º°`°º¤ø,,,,ø¤º°`°º¤ø¤º°`°º¤ø,,,,ø¤ºArticle: 65582
Oops, I missed one - in addition to http://www.altera.com/products/devices/stratix2/st2-index.jsp more FPGA direction indicators are also here :- http://www.leopardlogic.com/news/index.php As to anxious, anxiety, or over-anxious etc, perhaps the subject "ASMBL anxiety" says it all... :) -jg Austin Lesea wrote: > Jim, > > anxious - > > "1. Uneasy and apprehensive about an uncertain event or matter; worried. > 2. Attended with, showing, or causing anxiety: spent an anxious night > waiting for the test results. > 3. Usage Problem. Eagerly or earnestly desirous. > > > [From Latin nxius, from angere, to torment. See angh- in Indo-European > Roots.]anxious·ly adv. > anxious·ness n. > > Usage Note: Anxious has a long history of use roughly as a synonym > for eager, but many prefer that anxious be used only when its subject is > worried or uneasy about the anticipated event. In the traditional view, > one may say We are anxious to see the strike settled soon but not We are > anxious to see the new show of British sculpture at the museum. > Fifty-two percent of the Usage Panel rejects anxious in the latter > sentence. But general adoption of anxious to mean “eager” is > understandable, at least in colloquial discourse, since it provides a > means of adding emotional urgency to an assertion. It implies that the > subject so strongly desires a certain outcome that frustration of that > desire will lead to unhappiness. In this way, it resembles the informal > adjective dying in sentences such as I'm dying to see your new baby." > > http://dictionary.reference.com/search?q=anxious > > Austin >Article: 65583
Cool, table updated with the prices.Article: 65584
cool, found it http://www.pragmatic-c.com/gpl-cver/ will add a link soon.Article: 65585
I have a very simple design that should fit in a GAL26V12 with ease,
but I keep getting "Design does NOT fit" What's going on?
ABEL Example:
MODULE Test1
CSN pin;
K4,K2,K0,K6,K1,K5,K3,K7 pin;
K = [K0,K1,K2,K3,K4,K5,K6,K7];
D7,D6,D5,D4,D3,D2,D1,D0 pin;
D = [D0,D1,D2,D3,D4,D5,D6,D7];
Equations
D = K;
K.oe = !CSN;
END
This won't fit. and give me as follows messages.
---Device 'p26cv12'
---Note 4042: Unable to assign D4, need more pins
---like pin 27.
---Note 4042: Unable to assign D5, need more pins
---like pin 27.
---Note 4042: Unable to assign D6, need more pins
---like pin 27.
---Note 4042: Unable to assign D7, need more pins
---like pin 27.
---Note 4042: Unable to assign D4, need more pins
---like pin 23.
---Note 4042: Unable to assign D5, need more pins
---like pin 23.
---Note 4042: Unable to assign D6, need more pins
---like pin 23.
---Note 4042: Unable to assign D7, need more pins
---like pin 23.
---Note 4042: Unable to assign D4, need more pins
---like pin 22.
---Note 4042: Unable to assign D5, need more pins
---like pin 22.
---Note 4042: Unable to assign D6, need more pins
---like pin 22.
---Note 4042: Unable to assign D7, need more pins
---like pin 22.
---Design does NOT fit
---Done: failed with exit code: 0001.
Article: 65587> I have a very simple design that should fit in a GAL26V12 with ease, > but I keep getting "Design does NOT fit" What's going on? > ABEL Example: > MODULE Test1 > CSN pin; > K4,K2,K0,K6,K1,K5,K3,K7 pin; > K = [K0,K1,K2,K3,K4,K5,K6,K7]; > > D7,D6,D5,D4,D3,D2,D1,D0 pin; > D = [D0,D1,D2,D3,D4,D5,D6,D7]; > > Equations > D = K; > K.oe = !CSN; > END > > This won't fit. and give me as follows messages. > > ---Device 'p26cv12' > ---Note 4042: Unable to assign D4, need more pins > ---like pin 27. > ---Note 4042: Unable to assign D5, need more pins > ---like pin 27. > ---Note 4042: Unable to assign D6, need more pins > ---like pin 27. > ---Note 4042: Unable to assign D7, need more pins > ---like pin 27. It looks like it's assigned the I/O pins first, and has assigned them all to the K bus. Thus when it tries to associate the D bus (output) with an output pin it doesn't have any available (all the remaining pins are input only) Perhaps if you just swap the placement of the K and D definitions, so that D is before K the compilation (and placement) will succeed. For what you're using the device for it seems wasteful to use a PLD, why not just use a tristate buffer??Article: 65588
"Bevan Weiss" <kaizen__@NOSPAMhotmail.com> wrote in message news:AzDTb.32269$9k7.679313@news.xtra.co.nz... > > I have a very simple design that should fit in a GAL26V12 with ease, > > but I keep getting "Design does NOT fit" What's going on? > > ABEL Example: > > MODULE Test1 > > CSN pin; > > K4,K2,K0,K6,K1,K5,K3,K7 pin; > > K = [K0,K1,K2,K3,K4,K5,K6,K7]; > > > > D7,D6,D5,D4,D3,D2,D1,D0 pin; > > D = [D0,D1,D2,D3,D4,D5,D6,D7]; > > > > Equations > > D = K; > > K.oe = !CSN; > > END > > > > This won't fit. and give me as follows messages. > > > > ---Device 'p26cv12' > > ---Note 4042: Unable to assign D4, need more pins > > ---like pin 27. > > ---Note 4042: Unable to assign D5, need more pins > > ---like pin 27. > > ---Note 4042: Unable to assign D6, need more pins > > ---like pin 27. > > ---Note 4042: Unable to assign D7, need more pins > > ---like pin 27. > > It looks like it's assigned the I/O pins first, and has assigned them all to > the K bus. Thus when it tries to associate the D bus (output) with an > output pin it doesn't have any available (all the remaining pins are input > only) > Perhaps if you just swap the placement of the K and D definitions, so that D > is before K the compilation (and placement) will succeed. For what you're > using the device for it seems wasteful to use a PLD, why not just use a > tristate buffer?? Hmm something else I didn't pick up on earlier... If K is your input to the buffer, why are you changing it's output enable state?? If you want K to be the output, then your assignment statement should surely read K = D, as opposed to D = K.Article: 65589
Maybe you need 1024MB RAM if you are doing designs with xc2v6000 and above. My experience is, the memory surge to 450MB once P&R started. Kelvin Alex Gibson <me@privacy.net> wrote in message news:bvg547$rnfhm$2@ID-140944.news.uni-berlin.de... > > "Marcus Schaemann" <Marcus.Schaemann_invalid@mez.rub.de> wrote in message > news:bv5vc2$pvr$1@sunu789.rz.ruhr-uni-bochum.de... > > Hello, > > > > I'm supposed to set up a new VHDL/FPGA lab at our university. But I'm > > unsure which operation system and programming solution to use. > > Maybe some of you have experience setting up a lab and can answer some > > questions. > > > > We already have the Xilinx ISE Software 6.1i for PC/Solaris/Linux and > > Synopsys Software for Solaris and Linux through a Europractice license. > > We also have an "old" DLC4 and XC4005, but I guess it's not worth trying > > to make that work. (As far as I could find out, DLC4 is not supported > > anymore even for ISE 4.2.) > > > > So here are my questions: > > > > 1. Which operating system supplies the best performance/environment for > > Xilinx development? > > I read that the supplied ModelSim II XE works only on PCs, not on > > Solaris or Linux. So would you prefer a PC, because of the included > > simulation environment? > > > > 2. If a Solaris/Linux environment is concerned, which simulator is > > available/usable? Is Synopsys' scirocco usable? > > > > 3. Which Download Cable would you recommend? Does the Parallel Cable > > only work with a PC (I read that somewhere)? > > Or would you prefer the Multilinx Cable? (If so, why?) > > > > 4. Regarding the programming of the FPGA, would you recommend a separate > > design/program environment (e.g. Some Solaris Workstations for > > design, and one PC just for programming and testing on a FPGA)? > > > > I hope someone can enlighten me a bit! > > > > Regards, > > > > Marcus > > I tutor and do some lab support . > We are just upgrading from windows nt4 to windows xp. > > What os depends on what hardware you have > and what software is supported and what licenses you get for free. > > Also if students can get themselves copies of the software for use on their > own machines. > > That is why we use xilinx webpack on windows for students > and full ise version in the labs(xilinx university program). > > We are still using version 5 as haven't received 6 yet, > doesn't make much difference as most students > don't use fpgas. > (Xilinx seems rather slow sending things to non-US uni's, > unless its due to the local distributor who is still annoyed at us > for buying cplds direct from xilinx due to them being a good bit cheaper ). > > For introductory digital systems we are still using > schematic entry. > > For advanced digital systems vhdl. > > Linux version of the webpack isn't out > so this isn't an option for the labs yet. > > P3 1GHz (256MB ram min) and below windows 2000 or linux > P3 1GHz 256MB ram and above windows 2000, windows xp or linux > > Which os depends on the software you can get for that os > and how easy it is for students to use. > > Students buy a kit from the uni, then assemble it. > Has experimenter and programmer boards and all components. > Programmer board connects to a pc via parallel port > and programs both cplds and pic microprocessors on the experimenter board. > Using a pic12F675 as a programmable oscillator for the cpld. > > This way the uni doesn't need to look after the hardware > and each student has their own. > > Gives more chance for hands on debugging. > > You can put additional boxed programmer boards in the lab > but we are removing them as they usually get damaged. > (Get some idiot who thinks if the lab programmers or computers don't > work they can get an extension on their assignment, so actively disables the > lab > thats why video surveillance is going in). > > Which download cable ? > Which ever you have.Or get one of the students or support staff > to design a programmer and get the pcbs made. > > We may possibly switch to altera > as a couple of the lecturers prefer the quartus software > with inbuilt simulation. > > Also looks like some time in the next year or so > Advanced digital systems will switch to fpgas. > So we are going to have to come up > with a decent student proof fpga design. > > Thinking about using dip modules for fpga and cplds > on the experimenter board, that way we can still have a common > board design for both subjects. Current programmer board can already program > fpgas. > Also want to switch to a usb based programmer due to > the fast disappearing parallel port situation. > > Alex Gibson > >Article: 65590
> > Thanks, that is great. > > A minor note : AHDL is standing for Altera Highlevel language. > > AFAIK, the free version only supports Megawizard function to > > be output in AHDL. > > > > Some pricetags would help too. The license restrictions would > > also be of interest. > > AFAIK, the Quartus2 free license is 90 or 180 days. > > > > Rene > > Hi, > > This is a correction to Rene's posting. The Quartus II 3.0 Web > Edition license duration is for 180 days, and can be renewed as many > times as needed from the web, i.e. there is no need to upgrade to a > full subscription at the end of the 180 days. The Megawizard Plug IN > Manager in the Quartus II 3.0 Web Edition provides output in VHDL, > Verilog and AHDL. > > - Subroto Datta > Altera Corp. Dear Altera Corp, could you please also confirm is SOPC Builder that is bundled with Altera Quartus II 3.0 Web Edition useable at all or not. so far all our attempts todo something with it have failed: NIOS is supplied (white icon?), after requesting NIOS evaluation license and installing it, nothing changes, the NIOS in SOPC is not enabled. and if there is no Avalon master then the SOPC doesnt do anything at all. SOPC list DF6811 as Avalon master, so obtained eval license for DF6811 (from provider DCD) - unfortunatly there is some problem as per DCD on Altera side so DF6811 is not enabled in SOPC, so no way. No Processor enabled, no avalon master no system can be built :( I dont get it - if SOPC is included in free edition there should be something that can be done with it ??? In previous versions of Altera free software I think the NIOS evaluation was possible, unfortunatly I had very little time then and now this older version probably would not recon the new license. Ok, the long story short - is there any way to evaluate NIOS without paying up front ? Thanks Antti Lukats altera.openchip.orgArticle: 65591
[snip] > > Ok, the long story short - is there any way to evaluate NIOS without paying > > up front ? > > > There at least were NIOS kits, meaning some FPGA, Stratix, or Cyclone hardware > together with a full license upgradeable withing a year to the latest version. > At around 450$ they were a bargain, considering the hardware. > You're never doing your own hardware for that little. > > I wasn't able to run the kit due to configuration problems > and lack of time. So I cannot comment any further yet. Well, yes, I know there are kits at different price tags, but Altera says on the website it is possible to evaluate NIOS without purchase (of NIOS or eval kit). And if some Feature is included in some some software (like SOPC Builder in Quartus Web Edition) then I guess it should be useable. So I am still hoping that I am so stupid and cant figure it out how it can be used. I started to write my own CPU for SOPC, but well it too much trouble just to see if SOPC Builder does something or not. Hope somebody can clear this up. In case SOPC Builder is useable in evaluation mode only with 3rd party processors (not NIOS) would be nice to know which ones are available and working (the first one we tried turned out non-SOPC Builder ready, despite its advertizing) anttiArticle: 65592
Hello! My question is what are the benefits of using IIR filters instead of CIC and FIR filter in digital down converter implemented in FPGA. My collogue has got this idea, and I am not 100% convinced in its theory. I have made some research on the net and I didn't find any piece of information regarding IIR filters used in DDC, has any of you any kind of experience dealing with IIR in FPGA? Thanks, Sasa some info about the design: Device: V2P Fclk = Fs = 108MHz Finput = 27Mhz Decimation = 128Article: 65593
First of all , when you say that you are implementing a counter,
what are you going to count???????
assuming whatever you are going to count is A, then
use this code to increment the count
if A'event and A = '1' -- or A = '0' whatever be the case
count := count + 1;
end if;
or else you might endup counting something else or endup in a
infinite loop as u see to be now.
"Georges Konstantinidis" <georges_konstantinidis@hotmail.com> wrote in message news:<401e8f16$0$322$ba620e4c@news.skynet.be>...
> Thanks for the info.
> "Andy Peters" <Bassman59a@yahoo.com> a écrit dans le message de
> news:9a2c3a75.0402020916.391b9ce6@posting.google.com...
> > "Georges Konstantinidis" <georges_konstantinidis@hotmail.com> wrote in
> message news:<401c1026$0$13244$ba620e4c@news.skynet.be>...
> >
> > > What do you mean by saying "asserted"?
> >
> > "Asserted" means "put into the active state."
> >
> > It's a very common term. It's useful because it nicely ignores the
> > detail of whether the signal is active low or active high.
> >
> > --a
Article: 65594I want to count pulses coming from outside the FPGA (Spartan IIe on the Burched board) and displays the valus on a 7 digits segment. I tried already your code. the synthesis works, but not the implementation design. I created an UCF file to assign the pin, maybe this file creates problem. I do not know at which moment of the process I should assign the pins. Georges. "Sajan" <s_sajan_s@yahoo.com> a écrit dans le message de news:d244d444.0402030029.47146333@posting.google.com... > First of all , when you say that you are implementing a counter, > what are you going to count??????? > > assuming whatever you are going to count is A, then > use this code to increment the count > if A'event and A = '1' -- or A = '0' whatever be the case > count := count + 1; > end if; > > or else you might endup counting something else or endup in a > infinite loop as u see to be now. > > > > > "Georges Konstantinidis" <georges_konstantinidis@hotmail.com> wrote in message news:<401e8f16$0$322$ba620e4c@news.skynet.be>... > > Thanks for the info. > > "Andy Peters" <Bassman59a@yahoo.com> a écrit dans le message de > > news:9a2c3a75.0402020916.391b9ce6@posting.google.com... > > > "Georges Konstantinidis" <georges_konstantinidis@hotmail.com> wrote in > > message news:<401c1026$0$13244$ba620e4c@news.skynet.be>... > > > > > > > What do you mean by saying "asserted"? > > > > > > "Asserted" means "put into the active state." > > > > > > It's a very common term. It's useful because it nicely ignores the > > > detail of whether the signal is active low or active high. > > > > > > --aArticle: 65595
We need to program Altera PLDs on the end of a production line. Using the full IDE involves re-registering the stuff every 3 months, which is impossibly awkward at the factory. Does anyone know if there is a simpler program-only utility which doesn't require continuous re-licensing? TVM DavidArticle: 65596
I would like to accelerate a data conversion task. We just send a stream of data to converter that produses a response stream. Actually, this converter is an emulator of a system we are going to simulate efficiently accelerating simulation task. As the goal is a number of simulations per time unit, the high performance channels are needed to communicate between application running on PC and emulator running on FPGA. The data conversion (encription, compression) should be a known and well-understood toipc; thus, I would like to see any good reference designs. As, I do not have any experiance in high-speed I/O, I would like to discover existing and popular high speed interfaces (DRIVERS, tools, examples, defign flows, methodologies, cores, etc.). Can anybody offer an Internet resource or an exellent book describing the topic? How many time would it take to built a simplest prototype in man-hours (100, 1000, million)? How costly will it be? Many thanks.Article: 65597
I think this boils down to what is considered good design practice. If you want to count the edges of a single input line, then it really should be considered as a clock input, and therefore you should be using a dedicated clock input pin. If you use a standard IO pin, then ISE will grumble about using it to drive clock inputs. If you're stuck with this setup, then you really should be sampling this IO line. If you're expecting a fairly low input frequency, and a long mark and space time (high and low time) then this should be easy enough. In a nutshell. If you where going to do this in good old fashioned 74 series, you'd plug the signal you want to count into the counter clock input. For similar reasons you should connect the same signal into the FPGA clock input. Andy P.S. Chances are someone else knows better. I'm quite willing to be proved wrong!! Georges Konstantinidis wrote: > Hello Andrew, > I was endeed using a "normal I/O port" which is synchronous or asynchronous > according to the datasheets. I should be able to use it. > Or I miss something. > I found also a template in ISE called "debounce circuit" which seems to > work. > In any case I will also try what you said > Thanks everyone for you cooperation, Georges. > > > > "Andrew Greensted" <ajg112@ohm.york.ac.uk> a écrit dans le message de > news:bvlerm$crt$1@pump1.york.ac.uk... > >>Try this: >> >>library ieee; >>use ieee.std_logic_1164.all; >> >>entity counter is >> port( Load: in std_logic; >> Rst: in std_logic; >> LED: out std_logic_vector(0 to 7)); >> >>end counter; >> >>architecture behaviour of counter is >>begin >> >>cnt : process(Rst, Load) >> >> variable count : std_logic_vector(7 downto 0); >> >>begin >> >> if (Rst = '1' then) then >> count := "00000000"; >> else if (Load'event and Load='1') then >> count := count + 1; >> end if; >> >> LED <= count; >> >>end process cnt; >> >>end behaviour; >> >>Now make sure that Load is 'locked' to a clock input on the FPGA, or >>you'll probably get complaints of a logic line driving clock inputs. >>Try using something like: >> >>attribute LOC : string; >>attribute LOC of signal Load : signal is "pin number"; >> >>Every time that a rising edge of Lock occurs, the variable count is >>incremented. LED will be loaded with the value of count each time the >>process 'runs' (I assume this is what you want?). >> >> >>Georges Konstantinidis wrote: >> >>>What do you mean by saying "asserted"? >>>"Andy Peters" <Bassman59a@yahoo.com> a écrit dans le message de >>>news:9a2c3a75.0401301451.70df14a6@posting.google.com... >>> >>> >>>>"Georges Konstantinidis" <georges_konstantinidis@hotmail.com> wrote in >>> >>>message news:<401ab556$0$777$ba620e4c@news.skynet.be>... >>> >>> >>>>>Dear all >>>>>I'm deseprately trying to make an asynchronous counter to count the >>> >>>number >>> >>> >>>>>of inputs I have on a pin. I also want a reset input. >>>>>I copied the last version of my code at this e-mail . >>>>>The synthesis looks good but an error comes at the implementation >>> >>>design. I >>> >>> >>>>>don't kow to to do any more. >>>>>Thank you for fixing my bugs, Georges. >>>>> >>>>> >>>>>library ieee; >>>>>use ieee.std_logic_1164.all; >>>>> >>>>>entity counter is >>>>> port(Load, Rst: in std_logic; >>>>> LED: out std_logic_vector(0 to 7) >>>>>); >>>>>end counter; >>>>> >>>>>architecture behaviour of counter is >>>>> signal Qreg: std_logic_vector(0 to 7); >>>>> >>>>>begin >>>>>process(Rst, Load) >>>>>begin >>>>> if Rst = '1' then -- Async reset >>>>> Qreg <= "00000000"; >>>>> elsif Load='1' then >>>>> Qreg<=Qreg+1; >>>>> end if; >>>>> >>>>>end process; >>>>> >>>>>LED <= Qreg; >>>>> >>>>>end behaviour; >>>> >>>>Why do you want to do an async counter? No clock available? >>>> >>>>What is the implementation error? (Actually, I know what it is -- but >>>>I want to know what you think it is.) >>>> >>>>Think about: >>>> >>>>What happens if neither Rst nor Load are asserted? >>>> >>>>--a >>> >>> >>> > >Article: 65598
David Collier <from_usenet_comp_arch_fpga@dexdyne.com> wrote: : We need to program Altera PLDs on the end of a production line. : Using the full IDE involves re-registering the stuff every 3 months, which : is impossibly awkward at the factory. : Does anyone know if there is a simpler program-only utility which doesn't : require continuous re-licensing? If you only need to programm the parts, not to sythensize, place and route them, then look for jamplayer. Other jtag tools should work too, if your parts are JTAG. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 65599
Dear colleagues, The ByteBlaster works fine with MaxPlus 9.4 / Windows 95 but fails with MaxPlus 10.2 / Windows 98. "Unrecognized device or socket is empty" Any clue ? Nordic regards, Yuri
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