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Hi, Recently, I comes up against a problem about STA by tool PrimeTime. After runing constraints, I check timing by check_timing. And warnings is "There are 19 registers clock pin with no clock"! How can I find those registers with no clock? Help me! Thanks!Article: 65701
Hi there, Is there any way to convert PAD name (package pin name) to (X,Y) RPM coordinate used in Xilinx FPGA editor. TIA HTArticle: 65702
Kelvin @ SG wrote: > Sean: > I found that at the final assembly stage, when I removed the "Closed" > constraint in the Place & Route on the > fixed module. And then my design ran without errors. Which "closed" constraint do you mean? The "MODE = RECONFIG"-constraint? If I remove that, the design flow finishes without a problem, but of course the result is unusable, since lots of nets from the fixed module cross the module boundary to the reconfigurable module. -- Sean Durkin Fraunhofer Institute for Integrated Circuits (IIS) Am Wolfsmantel 33, 91058 Erlangen, Germany http://www.iis.fraunhofer.de mailto:23@iis.42.de ([23 , 42] <=> [durkinsn , fraunhofer])Article: 65703
Dear friends, Could your check and then post your BIOS LPT port settings for me ? Thank you in advance, YuriArticle: 65704
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: : Leon Heller <aqzf13@dsl.pipex.com> wrote: : : Sorry, they *are* available (allegedly), I didn't check all the pages. : Listing 60 or even more then 100 Spartan (nuhorizons) : Device/Package/Speed Options have having only 3/nill on stock looks : strange admitingly... To follow up my own thread: The status on the Avnet page has changes again to "No stock"... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 65705
Hi Pete, petersommerfeld@hotmail.com (Peter Sommerfeld) wrote in message news:<5c4d983.0402041113.563100e4@posting.google.com>... > Hi Fredrik, > > Are these numbers for a 32-bit Nios with hardware multiply? > > -- Pete No hardware multiply (used MSTEP), but 32-bit Nios. Design used was one I used on some Nios traning with DMA and a CRC custom istruction in it. Also some other goodies for trying out the various features of the Nios Stratix board. Cheers Fredrik > > fredrik_he_lang@hotmail.com (Fredrik) wrote in message news:<77a94d51.0402040058.38e476c9@posting.google.com>... > > Hi Jim > > Jim Granville <no.spam@designtools.co.nz> wrote in message news:<14XTb.20607$ws.2742532@news02.tsnz.net>... > > > snip. > > > Anyone seen actual numbers or NIOS or NIOS II ? > > > > > > -jg > > I did a quick compile in Quartus2_ver4 with Stratix2 and Stratix same > > Nios design only changed parts. Results in ALUT's compared to LE's is > > 3202 ALUT (S2) and 4522LE's (S). Push button compile of design no > > tweaking no logiclock. > > Cheers > > FredrikArticle: 65706
On Thu, 5 Feb 2004 05:50:58 -0800, "Antti Lukats" <antti@case2000.com> wrote: >"Jason Crawford" <jace@cisco.com> wrote in message >news:1075949641.602326@sj-nntpcache-3... >> Hi, >> >> I want to make a custom PS/2 keyboard. >> >> I have a Xilinx SpartanII part on my custom keyboard and I am >> looking to implement a PS/2 keyboard interface so that I can >> plug my custom keyboard into a standard PC PS/2 port. >> >> Googling for an opencore has so far been fruitless. > >there is possible no keyboard side core available as it is not a very comman >thing to have :) It's also not commonly done in an FPGA. Most PS/2 keyboards use a mask programmed 8048, although I did once find one (from Fujitsu) that used a mask programmed 6805. If you really must use an FPGA, you could probably write the code in a few minutes, once you find a reference to the protocol ... googling ... http://govschl.ndsu.nodak.edu/~achapwes/PICmicro/PS2/ps2.htm or http://www.networktechinc.com/ps2-prots.html http://www.networktechinc.com/technote.html Regards, Allan.Article: 65707
Yuri Tregubov wrote: > Dear friends, > > Could your check and then post your BIOS LPT port settings for me ? I just dug out my home-made ByteBlaster clone and an old Flex10K10 board of mine and checked that they still worked with MaxPlus 10.2. Configuration with a simple test function worked OK. I'm using WinME with the port configured for EPP operation. Leon -- Leon Heller, G1HSM Email: aqzf13@dsl.pipex.com My low-cost Philips LPC210x ARM development system: http://www.geocities.com/leon_heller/lpc2104.htmlArticle: 65708
> Dear colleagues, > > I need to find out that which verification tool would be better > (overall) for the (Co)-Verification of the SoC/ASIC. We are thinking > of making comparison between Seamless and Quickturn/Cadence product > i.e. Cobalt. > > I know Cobalt has certain benefits such as: faster speed, Higher > capacity. > > But still I need to know the following: > > - complexity in setting-up the environment (Seamless&Specman both) > - User friendly > - Nature of the results (% wrong values in result) > - Effort required to make the environment working for simulation > - Whether valid for synchronous designs only or more > - Debug capability > > > I will really appreciate help from the gurus of the > design/verification community. > > > Best regards, > rajan My type is HES. www.alatek.com Best Regards, GrivaArticle: 65709
Hi, I'm looking for the fastest interface/standard between two FPGAs. Have You got any suggestions? Thnx for answers. -- Best Regards, GrivaArticle: 65710
Hi, Do you have any advice about Intergrated Logic Analizer in FPGA Xilinx? For a new product, I have to provide an on-board logic Analizer. I will use ILA with JTAG port. The question is I don't know which SPARTAN I have to use to do the JOB. We have to up to 130 Mhz acquisition for 64 bit vectors. The fifo data depth is not very important -> 16-32k will be enough. The FPGA will just be used for Logic Analizer JOB, so which FPGA? Any help will be appreciated. Laurent www.amontec.comArticle: 65711
Griva <griva@poczta.onet.pl> wrote: : Hi, : I'm looking for the fastest interface/standard between two FPGAs. : Have You got any suggestions? It depends on reuirements: - Uni/Bidirectional - Distance between chips - Number of connections allowed ... I think that nearly always it is best to get a bigger FPGA and put everything into one package. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 65712
I am compiling a design for the Acex EP1k50 using Quartus II version 3. The FPGA device is about 20% full, but I am finding compilation times are taking longer and longer (Currently 14 minutes) They also seem to be increasing disproportionatley to the amount of extra functions added. For example, compilation was taking 7-8 minutes last week. Since then I have only added very few functions, but compile time has been creeping up on a daily basis to the current 14 minutes. I have tried playing with the compiler settings under mode and fitting (as in "save more files for fast compilation") with little effect One odd thing I noticed is that if I remove a few source modules, compilation time stays at the full 14 minutes. It feels as though the compiler is getting bloated somehow, possibly by accumulating irrelevant data in some files somewhere. Is there anything I can do to alleviate this? I don't think the problem has much to do with the design itself, which is fully synchronous. Compilations for similar projects in the past have only taken 3-4 minutes. Any ideas anybody? tedArticle: 65713
Użytkownik "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> napisał w wiadomości news:bvt49f$k8h$1@news.tu-darmstadt.de... > Griva <griva@poczta.onet.pl> wrote: > : Hi, > > : I'm looking for the fastest interface/standard between two FPGAs. > : Have You got any suggestions? > > It depends on reuirements: > - Uni/Bidirectional > - Distance between chips > - Number of connections allowed > ... > > I think that nearly always it is best to get a bigger FPGA and put > everything into one package. > > Bye > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Reqiurements: - Uni/Bi - for me it doesn't matter, could be this and this - Distance - about 3-5 cm - Number - about 500 - 700 pins The biggest FPGA is too small, I have to use 2 or 3 FPGAs and I want to have the fastest transfer between these chips. Best Regards, GrivaArticle: 65714
Heyho NG, is there a possibility to install the xilinx download tool as a stand alone application for our production line? It is a little bit urgent, because they just put in the XC18V01 without programming them before. So they need a possibility to install just the download-tool. Can anyone help? Thanks, Thomas -- No matter if you are going on-piste or off-piste, just hit the slope and stay healthy! For mail reply replace "nospam" with "kurth" and "net" with "de". The above mentioned adress is valid, but ignored.Article: 65715
Jason Crawford <jace@cisco.com> wrote in message news:<1075949641.602326@sj-nntpcache-3>... > I have a Xilinx SpartanII part on my custom keyboard and I am > looking to implement a PS/2 keyboard interface so that I can > plug my custom keyboard into a standard PC PS/2 port. > > Googling for an opencore has so far been fruitless. > > I've tried opencores.org, but they only have a PS/2 keyboard interface > that would be implemented on the host side (not keyboard side). Build one yourself. To receive the codes is more complicated then sending them and in a lab course I teach it takes my students about four hours to build a PS2 receiver. So a sender should be no problem. The protocol is described here: http://govschl.ndsu.nodak.edu/%7Eachapwes/PICmicro/PS2/ps2.htm The scancodes are here http://govschl.ndsu.nodak.edu/%7Eachapwes/PICmicro/keyboard/scancodes2.html For most keys you just have to shift out one byte when the key is pressed and two bytes when it is released. I expect that interpreting whatever it is that you use for your keys is a lot more complicated then the PS2 part which I estimate at 10 lines VHDL at most. (Plus any FIFOs that you might want to add) Kolja SulimmaArticle: 65716
In the FPL03 international conference a paper was presented that described the Xilinx Partial Reconfiguration Toolkit, this API allowed Virtex II pro embedded applications to perform dynamic partial reconfiguration without requiring external circuit. This appears to be a simple port of JBits API to work in an embedded system. I am trying to find out if this API is going to be released by Xilinx, in a similar form as JBIts, and when this is going to happen. Can anyone help me?Article: 65717
Hi, there: I am using Virtex-2 to do a partially reconfiguratable design. My two reconfigurable modules depend on muxed clock buffers and DCMs located in the area group of a fixed module. During active modules implementation, some of the wires on the BUFGMUXs and DCMs were routed, while the other wires for example the vcc_fake on the Bus Macros were not! Is this the correct behavior? In the two reconfigurable modules implementations, do I expect these routed & unrouted wires to be exactly the same? Besides that, the file size of the bit-streams of two reconfigurable blocks were not the same, is this correct? Does the BitGen for active module implementation ONLY generate bitstream for my AREA_GROUP or the routed wires on BUFGMUXs and DCMs also? Thanks for your answers. Best Regards, KelvinArticle: 65718
CyberFunk wrote:
> Hi there,
> Is there any way to convert PAD name (package pin name) to
> (X,Y) RPM coordinate used in Xilinx FPGA editor.
> TIA
Try running "partgen -v partname"
where partname is, e.g. cx2v1000-fg456-4
then open up the partname.pkg file.
For example, from xc2v1000-fg456-4.pkg: (watch the wrap)
pin PAD1 B4 0 IO_L01N_0 X1Y79 0S
0
pin PAD2 A4 0 IO_L01P_0 X1Y79 0M
0
pin PAD3 C4 0 IO_L02N_0 X1Y79 1S
0
Thus pin B4 is located at slice X1Y79, and so on..
You could look at the part in FPGA editor to confirm.
Regards,
John
Article: 65719Hi everybody, I am experiencing a weird problem with Modelsim 5.7d When i run my .do file with a "add wave" command, the program shuts. I have run it in command mode and I get that the error code is 211. Unfortunately, I have not found much about it on the modelsim website. Can anyone help? Thanks!Article: 65720
Hi, At school we have a project and our subject is to make a simple spectrum analyser. Now I want to know if it would be possible to perform a realtime FFT with an FPGA/CPLD (if possible in Xilinx). And if it is possible, where I can find/download the source and which chip is best to use. Any help will be appreciated. Thanks in advance, Sander OdekerkenArticle: 65721
From a cost standpoint, that is not always true. Also, if you have a
memory intensive application, you get more memory by using two smaller
devices (say XC2V3000's) instead of one larger one (eg XC2V6000). If
you have the luxury of using a chip with the high speed serial i/o,
that will give you rather high bandwidth connections without using up
many pins. Otherwise, you need to refer to the data sheets for each of
the i/o standards supported to see the speeds and what is required to
make it work. Some of the lower voltage swings are faster, but have
special voltage requirements you may not be able to meet. LVDS is
generally faster, at least on longer runs. You may need external
terminators as well, as IIRC, invoking the DCI has a substantial speed
penalty.
Uwe Bonnes wrote:
> Griva <griva@poczta.onet.pl> wrote:
> : Hi,
>
> : I'm looking for the fastest interface/standard between two FPGAs.
> : Have You got any suggestions?
>
> It depends on reuirements:
> - Uni/Bidirectional
> - Distance between chips
> - Number of connections allowed
> ...
>
> I think that nearly always it is best to get a bigger FPGA and put
> everything into one package.
>
> Bye
> --
> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 65722"Jason Crawford" <jace@cisco.com> wrote in message news:1075949641.602326@sj-nntpcache-3... > Hi, > > I want to make a custom PS/2 keyboard. > > I have a Xilinx SpartanII part on my custom keyboard and I am > looking to implement a PS/2 keyboard interface so that I can > plug my custom keyboard into a standard PC PS/2 port. > > Googling for an opencore has so far been fruitless. there is possible no keyboard side core available as it is not a very comman thing to have :) I would personally probably do it a little tweaking, putting a PicoBlaze processor onto the FPGA it takes one Block RAM and about 70 Slices. It does fit into any spartan. So you can use it even in XC2S15. Even though a simple PS2 SIE (serial interface engine) itself is smaller than PicoBlaze then if you add full keyboard control status leds etc.. I think you will end up in similar Slice count or more. anttiArticle: 65723
It is. Real-time is a bit of a loose definition that depends on the
application. A serial implementation might be considered real time for an
audio analyzer, while it would not be for FFT's performed for radar. You need
to define the size of the FFT you wish to perform and the transform time
required before you can determine what approach (and therefore which chip) is
appropriate. You can go from a bit serial iterative FFT in a very small FPGA +
external memory to an FFT that computes all the points in parallel in a much
larger device. We offer an FFT core that is arguably the fastest single
threaded (one point at a time) FFT possible in an FPGA (it does one point per
clock and is limited by the minimum clock pulse width, not by routing delays),
however it is not free. Both Xilinx and Altera offer FFT cores as part of
their core library, but you don't get any insight into the inside of the core,
as they don't make the source code available. IIRC, there is also a free FFT
design on opencores.com which should have source with it. Alternatively, you
can roll your own. The math to do the fft is not difficult to code. What is
difficult is making it an efficient design.
Sander Odekerken wrote:
> Hi,
>
> At school we have a project and our subject is to make a simple spectrum
> analyser. Now I want to know if it would be possible to perform a realtime
> FFT with an FPGA/CPLD (if possible in Xilinx). And if it is possible, where
> I can find/download the source and which chip is best to use.
>
> Any help will be appreciated.
>
> Thanks in advance,
>
> Sander Odekerken
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 65724Ted, If you can do send me the two archives of the design. The one which compiles in the 7-8 minute range and the other one which has the addiitonal logic added, and causes increased compilation time. We would like to analyze the design. Thanks - Subroto Datta Altera Corp. "ted" <edaudio2000@yahoo.co.uk> wrote in message news:c54bf83f.0402050212.74024e17@posting.google.com... > I am compiling a design for the Acex EP1k50 using Quartus II version > 3. The FPGA device is about 20% full, but I am finding compilation > times are taking longer and longer (Currently 14 minutes) > > They also seem to be increasing disproportionatley to the amount of > extra functions added. For example, compilation was taking 7-8 minutes > last week. Since then I have only added very few functions, but > compile time has been creeping up on a daily basis to the current 14 > minutes. > > I have tried playing with the compiler settings under mode and fitting > (as in "save more files for fast compilation") with little effect > > One odd thing I noticed is that if I remove a few source modules, > compilation time stays at the full 14 minutes. > > It feels as though the compiler is getting bloated somehow, possibly > by accumulating irrelevant data in some files somewhere. > > Is there anything I can do to alleviate this? > > I don't think the problem has much to do with the design itself, which > is fully synchronous. Compilations for similar projects in the past > have only taken 3-4 minutes. > > Any ideas anybody? > > ted
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