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Yuri Tregubov wrote: > Dear colleagues, > > The ByteBlaster works fine with MaxPlus 9.4 / Windows 95 but fails > with MaxPlus 10.2 / Windows 98. > > "Unrecognized device or socket is empty" > > Any clue ? > > Nordic regards, > Yuri There is a new driver, the ByteBlaster II, which I found I needed for MaxPlus 10.2 on Windows 2000. I don't know whether Windows 98 is supported or not. It was a royal pain to find the driver, install it, and get it working. There's probably a FAQ somewhere to cover this information step-by-step but I don't know where it is. Charles B. CameronArticle: 65601
If the downconverter is used for digital data, then you'll want a linear phase
characteristic. That is much easier to achieve with an FIR filter. The
feedback required for an IIR filter can make the design challenging (you have
one sample time between the input and the output which has to be available at
the input during the next sample time) because it cannot be pipelined. Finally,
IIR filters are considerably more sensitive to quantization, so you'll likely
need more precision than you would need for an FIR filter. FIR filters also
offer a possibility of using polyphase techniques to reduce the processing
load. About the only advantage an IIR filter has is that it generally takes
fewer coefficients to obtain a given response, but to get that you give up phase
linearity.
Sasa Bremec wrote:
> Hello!
>
> My question is what are the benefits of using IIR filters instead of CIC and
> FIR filter in digital down converter implemented in FPGA. My collogue has
> got this idea, and I am not 100% convinced in its theory. I have made some
> research on the net and I didn't find any piece of information regarding
> IIR filters used in DDC, has any of you any kind of experience dealing with
> IIR in FPGA?
>
> Thanks, Sasa
>
> some info about the design:
>
> Device: V2P
> Fclk = Fs = 108MHz
> Finput = 27Mhz
> Decimation = 128
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 65602Yuri Tregubov wrote: > Dear colleagues, > > The ByteBlaster works fine with MaxPlus 9.4 / Windows 95 but fails > with MaxPlus 10.2 / Windows 98. > > "Unrecognized device or socket is empty" > > Any clue ? I'm sure my home-made version of the Byte Blaster worked OK with Win98 SE. It works OK with WinME. Both with MaxPlus 10.2. Leon -- Leon Heller, G1HSM Email: aqzf13@dsl.pipex.com My low-cost Philips LPC210x ARM development system: http://www.geocities.com/leon_heller/lpc2104.htmlArticle: 65603
from_usenet_comp_arch_fpga@dexdyne.com (David Collier) wrote in message news:<memo.20040203105647.456F@DavidC.zen.co.uk>... > We need to program Altera PLDs on the end of a production line. > > Using the full IDE involves re-registering the stuff every 3 months, which > is impossibly awkward at the factory. > > Does anyone know if there is a simpler program-only utility which doesn't > require continuous re-licensing? JAM Player. Just generate JAM files use them with command line JAM/STAPL Player (it is available free and includes source codes). antti altera.openchip.org :)Article: 65604
Can anyone help me design a 4 bit divisor using flip flops. I want to design a circuit that devides two BCD numbers (for example 8 / 3 = 2 and 2 for rest). Can anyone helps ? Thanks a lot EricArticle: 65605
In article <17f33635.0402030650.2c88316@posting.google.com>, digkpk@yahoo.gr (eric) writes: |> Can anyone help me design a 4 bit divisor using flip flops. I want to |> design a circuit that devides two BCD numbers (for example 8 / 3 = 2 |> and 2 for rest). |> Can anyone helps ? This is a FAQ. Collect together a large number of flip-flops in various colours. Create a pile of (say) pink ones the side of your divisor, and a pile of (say) blue ones the size of your dividend. Keep a pile of (say) yellow ones to hand. Match up each pink one with a blue one, discard the blue ones, and put one yellow one in another pile. Then repeat. When there aren't enough pink ones to match the blue ones, the number of yellow ones you have collected in the target pile is the quotient and the number of blue ones left is the remainder. Simple, isn't it? Regards, Nick Maclaren.Article: 65606
In article <bvnv15$uhbvk$1@ID-212430.news.uni-berlin.de>, valentin_NOSPAM_NOWORMS@abelectron.com says... > I would like to accelerate a data conversion task. We just send a stream > of data to converter that produses a response stream. Actually, this > converter is an emulator of a system we are going to simulate efficiently > accelerating simulation task. As the goal is a number of simulations per > time unit, the high performance channels are needed to communicate between > application running on PC and emulator running on FPGA. The data conversion > (encription, compression) should be a known and well-understood toipc; thus, > I would like to see any good reference designs. > As, I do not have any experiance in high-speed I/O, I would like to > discover existing and popular high speed interfaces (DRIVERS, tools, > examples, defign flows, methodologies, cores, etc.). Can anybody offer an > Internet resource or an exellent book describing the topic? How many time > would it take to built a simplest prototype in man-hours (100, 1000, > million)? How costly will it be? A million oughta cover it. ;-) The various FPGA manufacturers have PCI cores, and such, for their products, but I've found them expensive in terms of up-front $$ and FPGA space. I decided to go with a PLX PCI-9054 (kinda long in the tooth now) as a PCI bridge. Drivers were readily available for it. See: http://www.plxtech.com/ You'll have to register to get the detailed specs (why, I haven't a clue). For more general information, try: http://www.opencores.org/ <== "open hardware" cores http://www.optimagic.com/ <== programmable logic jump station -- KeithArticle: 65607
Here are a couple of things to try - [1] Take a look at the the -u report ... keep adding contraints until unconstrained paths drop to zero. [2] Take gate level netlist into simulator, and see if there are problems with simulation. [3] Make an effort to ensure that all I/O connecting to core are registered. Observations - [1] Trace does a terrific job with synchronous paths, and (answering your original question), part problems are typically more design problems (but it sounds like you already accept this .... just looking for some ideas). [2] On the marginal boards, hit with shot of cold spray to see if chips start to opperate at 50 Mhz. [3] The symptom that one board works, but two don't is a little of a puzzler. That indicates problem may not be in time domain crossings but rather in synchronous paths which do not meet timing, where device specific process variations take have an effect. Or it could also mean there is something marginal at the PWB level .... GND scheme, decoupling, marginal voltages that push two units under threshold. (Check VCC levels ...sorry to state obvious) [4] Key might be to isolate block that is really failing. Is it really core? Something like a "signature" analysis on outputs of a block for periods that result in identical processing are helpful. ie... Do outputs of block 1 across an identical data set differ among the "good chip" vs the "bad" devices. [5] If you can over constrain your clock frequency for the entire design, or just the core, then try place-and-route with modular aproach, that might give you margin on your synchronous paths. Anyway .... good luck. Regards, John Retta Owner and Designer Retta Technical Consulting Inc. 303-926-0068 email : jretta@rtc-inc.com web : www.rtc-inc.com "MM" <mbmsv@yahoo.com> wrote in message news:bvmaua$u760t$1@ID-204311.news.uni-berlin.de... > I have a design, which is supposed to work in XC2V2000-5 at 50 MHz. The > timing analyzer reports the clock period to be below 19ns. However, in > practice, only one device out of 3 works at this speed. Two others were > happy when I slowed the clock to 45 MHz (I didn't try any intermediate > frequencies). The design basically consists of a 3rd party IP core, for > which I don't have a source (I believe it was designed in schematic), some > state machines, a bus interface and some Coregen memories. The bus runs at > slower clock, but it is fully decoupled from the IP core (through the > memories). The IP core is a fully synchronous design according to its > author. The clock comes directly from an external crystal oscillator. I > tried looking at unconstrained paths in the timing analyzer, but couldn't > see anything suspicious... > > Any ideas to where to look? > > Thanks, > /Mikhail > > -- > To reply directly: > matusov at square peg ca > (join the domain name in one word and add a dot before "ca") > >Article: 65608
"Anjan" <anjanr@yahoo.com> skrev i melding news:5a5faf7b.0401222006.2ad19b2b@posting.google.com... > Hi Steve, > I have a question about spartan 3. We are xilinx customers and have > ordered spartan 3 device long back. Also we have ordered engineering > samples. But the distributor can't answer when the order comes to us. > Can you please tell me whether spartan 3 1.5m devices are being > shipped(engineering samples)? > Anjan We have the same problem here.. Prototyping boards are ready and we have been promised devices for a quite long time. I hear xilinx has problems in production, wich is boring for us having quite a few boards ready :/ We were also promised a few samples with 2.5v max io, but they showed up either. From now on , we will be VERY careful to go for future devices. However, I hope they will appear in the near future.Article: 65609
Jim, * *.......I have been admonished for commenting on competitors in this forum. That will have to be left up to others like yourself. A careful review of all of the features of St2 will have to be left to others. Perhaps Ray Andraka can comment on their new ALM architecture? Advantages, disadvantages? Austin Jim Granville wrote: > Oops, I missed one - in addition to > http://www.altera.com/products/devices/stratix2/st2-index.jsp > > more FPGA direction indicators are also here :- > > http://www.leopardlogic.com/news/index.php > > As to anxious, anxiety, or over-anxious etc, perhaps the > subject "ASMBL anxiety" says it all... :) > > -jg > > Austin Lesea wrote: > >> Jim, >> >> anxious - >> >> "1. Uneasy and apprehensive about an uncertain event or matter; >> worried. >> 2. Attended with, showing, or causing anxiety: spent an anxious >> night waiting for the test results. >> 3. Usage Problem. Eagerly or earnestly desirous. >> >> >> [From Latin nxius, from angere, to torment. See angh- in Indo-European >> Roots.]anxious·ly adv. >> anxious·ness n. >> >> Usage Note: Anxious has a long history of use roughly as a synonym >> for eager, but many prefer that anxious be used only when its subject >> is worried or uneasy about the anticipated event. In the traditional >> view, one may say We are anxious to see the strike settled soon but >> not We are anxious to see the new show of British sculpture at the >> museum. Fifty-two percent of the Usage Panel rejects anxious in the >> latter sentence. But general adoption of anxious to mean “eager” is >> understandable, at least in colloquial discourse, since it provides a >> means of adding emotional urgency to an assertion. It implies that the >> subject so strongly desires a certain outcome that frustration of that >> desire will lead to unhappiness. In this way, it resembles the >> informal adjective dying in sentences such as I'm dying to see your >> new baby." >> >> http://dictionary.reference.com/search?q=anxious >> >> Austin >> >Article: 65610
eNo, LVDS is a standard differential interface covered by ANSI/IEEE. "Bus LVDS" is a non-standard for a multi-drop differential interface. It is accomplished in the IOBs by using a tristate-able standard LVCMOS IO, and its complement, and two external resistors whose value is chosen by the number of transmitters and receivers on the bus. It is covered in the User's Guide, under the IOs. Austin eNo wrote: > Anyone know the difference between LVDS_25 and BLVDS_25 in Xilinx's Virtex > II Pro or point me to a spec. where I can read about the electrical > characteristics of these two? Searching through Xilinx.com has yielded zero. > [When I set IOSTANDARD=BLVDS_25 for some of my differential (OBUFDS) > outputs, I get an Exception during mapping in Xilinx's ISE 6.1.03i. LVDS_25 > works fine for all my differential I/O, so I'm wondering whether I can get > away with using LVDS_25 instead.] > > -- > ø¤º°`°º¤ø,,,,ø¤º°`°º¤ø,,,,ø¤º°`°º¤ø,,,,ø¤º°`°º¤ø¤º°`°º¤ø,,,,ø¤º > eNo > ø¤º°`°º¤ø,,,,ø¤º°`°º¤ø,,,,ø¤º°`°º¤ø,,,,ø¤º°`°º¤ø¤º°`°º¤ø,,,,ø¤º > >Article: 65611
Hello,
I use the Sapartan-IIE from Xilinx.
In my application I'm writing with an µC to the dual port block RAM of
the FPGA.
If I'm writing only once to the dual port RAM, I succeed.
If I write several times to the RAM it get's confusing. The error is not
the same all the time. It differs.
I attempt to write 32 bit values to the dual port RAM.
To see the result, I read out data from the second port. I use a 7
segment LED the display the results. The addresses of
the second port are input be DIP switches. The second port is only read
(enable pin active all the time; read/write line permanently set to
READ).
And that's my test software:
The first value is written to adress 0x0 of the dual port RAM. The
second value to adress 0x1 (and so on...)
The first port, I use for the interface with the µC, is actually
configured as a 32 Bit port (generated by the
CoreGenerator from Xilinx ISE 6.1.01i)
And that's the result:
Sometimes the first write cycle of the µC seems o write data to
address 0x1 of the block RAM and with the
second write cycle data seems to be written to address 0x0. Data seems
to get interchanged.
Sometimes it seems that in address 0x0 there are no reasonable
values at all (Nothing that could have been
written by the first or second write cycle of the µC; but data at
address 0x1 is correct).
Writing 4 times to the dual port RAM can result in various errors.
Sometimes the values seem to be shifted through.
This means: data values that are written to adress 0x0 are found at
adress 0x1; data written to adress 0x1 is found
at adress 0x2. Data written to adress 0x2 is found at address 0x3. And
data written to address 0x3 is found in 0x0.
There seems to be a kind of shifting in the dual port RAM.
How can this be?
Is there something wrong.
I attach the code I use for the write process for the FPGA.
Is it possible, that the problem comes from "if rising_edge ..."?
Should it be "if IOSTRB_DSP='0' " ?
But then the process is not synchron anymore. Isn't it.
WRITE_DSP : process(IOSTRB_DSP) -- Daten
schreiben ins RAM (data -> ram)
begin
if rising_edge(IOSTRB_DSP) then
if CS_DSP = '0' and IORW_DSP = '0' then --
IORW=0: WRITE; CS and EN are active low
dinb <= data_DSP;
else
dinb <= (others=>'Z'); -- synthetisiert Tristate buffer;
end if;
end if;
end process;
It would be nice, if someone could give me an good advice.
Something I haven't yet cinsidered.
Greating, Tobias.
Article: 65612In comp.arch.fpga Nick Maclaren <nmm1@cus.cam.ac.uk> wrote: > > In article <17f33635.0402030650.2c88316@posting.google.com>, > digkpk@yahoo.gr (eric) writes: > |> Can anyone help me design a 4 bit divisor using flip flops. I want to > |> design a circuit that devides two BCD numbers (for example 8 / 3 = 2 > |> and 2 for rest). > |> Can anyone helps ? > > This is a FAQ. Collect together a large number of flip-flops in > various colours. Create a pile of (say) pink ones the side of > your divisor, and a pile of (say) blue ones the size of your > dividend. Keep a pile of (say) yellow ones to hand. > > Match up each pink one with a blue one, discard the blue ones, > and put one yellow one in another pile. Then repeat. When there > aren't enough pink ones to match the blue ones, the number of > yellow ones you have collected in the target pile is the quotient > and the number of blue ones left is the remainder. > > Simple, isn't it? > > > Regards, > Nick Maclaren. Seriously speaking this is not too far from the truth. I won't actually design one for you but I can give you some pointers on how to get started. From the basics. 1. Consider the process of division, and I mean REALLY consider it. Look at how the process of long division works. 2. Look at the stages of division and divide them up to the point where you are only doing one operation( think FSMs) also consider points where decisions are made and also look at ending conditions(think in terms of programming and algorithms). 3. Take to pencil and paper and sit down to a big cup of coffee and work out a state diagram. 4. From there go through the usual steps to reduce it to equations. If this all seems too much for you just try a bit of googling, I'm sure someone out there should have a ready made solution. Alternatively Just shove it into a vhdl sim and then examine the eqns. P.S. if this sounds a lot like a load of BS, it prolly is. It 12:30 am here and I'm just a little sleepy. -- Wing Wong. Webpage: http://wing.ucc.asn.auArticle: 65613
Nick Maclaren wrote: > In article <17f33635.0402030650.2c88316@posting.google.com>, > digkpk@yahoo.gr (eric) writes: > |> Can anyone help me design a 4 bit divisor using flip flops. I want to > |> design a circuit that devides two BCD numbers (for example 8 / 3 = 2 > |> and 2 for rest). > |> Can anyone helps ? > > This is a FAQ. Collect together a large number of flip-flops in > various colours. Create a pile of (say) pink ones the side of > your divisor, and a pile of (say) blue ones the size of your > dividend. Keep a pile of (say) yellow ones to hand. > > Match up each pink one with a blue one, discard the blue ones, > and put one yellow one in another pile. Then repeat. When there > aren't enough pink ones to match the blue ones, the number of > yellow ones you have collected in the target pile is the quotient > and the number of blue ones left is the remainder. > > Simple, isn't it? > > > Regards, > Nick Maclaren. I'm afraid I must disagree. Mixing pink, blue and yellow would just lead to metastability issues. I would go for green, red, and purple. And don't forget to clock yourself, it's always a good idea to have a fully synchronous design. -- Pierre-Olivier -- to email me directly, remove all _N0SP4M_ from my address --Article: 65614
"eric" <digkpk@yahoo.gr> ha scritto nel messaggio news:17f33635.0402030650.2c88316@posting.google.com... > Can anyone help me design a 4 bit divisor using flip flops. I want to > design a circuit that devides two BCD numbers (for example 8 / 3 = 2 > and 2 for rest). > Can anyone helps ? > > Thanks a lot > Can you evitate the crosspost ? It's not in netiquette and I'm very angry to download the same message a lot of time. Thank you GiuseppeArticle: 65615
from_usenet_comp_arch_fpga@dexdyne.com (David Collier) wrote in message news:<memo.20040203105647.456F@DavidC.zen.co.uk>... > We need to program Altera PLDs on the end of a production line. > > Using the full IDE involves re-registering the stuff every 3 months, which > is impossibly awkward at the factory. > > Does anyone know if there is a simpler program-only utility which doesn't > require continuous re-licensing? > > TVM > > David Hi David, You can use the standalone programmer available from https://www.altera.com/support/software/download/programming/asap2/dnl-asap2.jsp This does not require a license, and has a much smaller footprint. - Subroto Datta Altera Corp.Article: 65616
On Tue, 3 Feb 2004 17:44:18 +0100, the renowned miaooaim.REMOVETHIS@tiscali.it> wrote: > >"eric" <digkpk@yahoo.gr> ha scritto nel messaggio >news:17f33635.0402030650.2c88316@posting.google.com... >> Can anyone help me design a 4 bit divisor using flip flops. I want to >> design a circuit that devides two BCD numbers (for example 8 / 3 = 2 >> and 2 for rest). >> Can anyone helps ? >> >> Thanks a lot >> >Can you evitate the crosspost ? "Evitate" is listed as "obs. rare" in my two-volume supercondensed OED w/magnifier. It's not in most dictionaries (neither is the word "gullible", for some reason). Please evitate the use of such obscure words. >It's not in netiquette and I'm very angry to download the same message a lot >of time. Crossposting isn't necesarily a problem- in this case, the groups appear to all be relevant. Perhaps if you had a "real" newsreader, instead of ADD-addled OE it could remember whether you'd seen a given message between different newsgroups? It is far, FAR preferable to multiple posting. Multiple posting is EVIL, cross posting only has the potential. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.comArticle: 65617
On Tue, 03 Feb 2004 16:40:48 GMT, PO Laprise wrote: > Nick Maclaren wrote: >> In article <17f33635.0402030650.2c88316@posting.google.com>, >> digkpk@yahoo.gr (eric) writes: >>|> Can anyone help me design a 4 bit divisor using flip flops. I want to >>|> design a circuit that devides two BCD numbers (for example 8 / 3 = 2 >>|> and 2 for rest). >>|> Can anyone helps ? >> >> This is a FAQ. Collect together a large number of flip-flops in >> various colours. Create a pile of (say) pink ones the side of >> your divisor, and a pile of (say) blue ones the size of your >> dividend. Keep a pile of (say) yellow ones to hand. >> >> Match up each pink one with a blue one, discard the blue ones, >> and put one yellow one in another pile. Then repeat. When there >> aren't enough pink ones to match the blue ones, the number of >> yellow ones you have collected in the target pile is the quotient >> and the number of blue ones left is the remainder. >> >> Simple, isn't it? >> >> >> Regards, >> Nick Maclaren. > > I'm afraid I must disagree. Mixing pink, blue and yellow would just > lead to metastability issues. I would go for green, red, and purple. > And don't forget to clock yourself, it's always a good idea to have a > fully synchronous design. I don't *Think* so. Synchronous clocking of green flip-flops will almost certainly lead to ground bounce. BobArticle: 65618
On Tue, 3 Feb 2004 17:44:18 +0100, Giuseppe³ wrote: > "eric" <digkpk@yahoo.gr> ha scritto nel messaggio > news:17f33635.0402030650.2c88316@posting.google.com... >> Can anyone help me design a 4 bit divisor using flip flops. I want to >> design a circuit that devides two BCD numbers (for example 8 / 3 = 2 >> and 2 for rest). >> Can anyone helps ? >> >> Thanks a lot >> > Can you evitate the crosspost ? > It's not in netiquette and I'm very angry to download the same message a lot > of time. > > Thank you > Giuseppe Eschew obfuscation! BobArticle: 65619
Just for anyone who searches in the future. It seems that TDI and TMS are usually pulled high within target devices, however externally pulling them high (4.7k) is probably a good idea. TCK and TDO can be left floating. This may help: http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=11433 Andrew Greensted wrote: > Hi All, > I'm building a JTAG chain demultiplexer so I can control 30 identical > JTAG chains from a single point. > Can anyone confirm the quiescent (not doing anything) states of the JTAG > pins; so I know what to hold the pin levels at when a chain is not being > used. > I see that TMS, TCK & TDI have internal pull-ups, so would I place a > logical 1 on these when they're not in use? TDO is easy enough to sort > out as it just goes high Z. > > Many Thanks > Andy > -- Andrew Greensted Department of Electronics Bio-Inspired Engineering University of York, UK Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk Fax: +44(0)1904 433224 Web: www.bioinspired.comArticle: 65620
MM, Just a thought, did you check the decoupling of the 1.5V supply? Those MLCCs all look the same, if the board got fitted with 10pF rather than 10nF, it might affect the performance! You could also try reducing the 19ns constraint, but I'd still be worried about the thing failing when the timing says it should pass. Good luck, please let us know how you get on! Syms. "MM" <mbmsv@yahoo.com> wrote in message news:<bvmdfc$t21ft$1@ID-204311.news.uni-berlin.de>... > Brannon, > > "Brannon King" <bking@starbridgesystems.com> wrote in message > news:bvmcge$q3l@dispatch.concentric.net... > > up. As for running below specs, as far as I understand that should only > > happen when the incoming power or temperature are out of spec. > > That doesn't seem to be the case. The temperature is room or slightly > higher, and the core voltage I measured at 1.506V... > > /MikhailArticle: 65621
On Mon, 02 Feb 2004 15:15:06 -0500, MM wrote: > I have a design, which is supposed to work in XC2V2000-5 at 50 MHz. The > timing analyzer reports the clock period to be below 19ns. However, in > practice, only one device out of 3 works at this speed. Two others were > happy when I slowed the clock to 45 MHz (I didn't try any intermediate > frequencies). The design basically consists of a 3rd party IP core, for > which I don't have a source (I believe it was designed in schematic), some > state machines, a bus interface and some Coregen memories. The bus runs at > slower clock, but it is fully decoupled from the IP core (through the > memories). The IP core is a fully synchronous design according to its > author. The clock comes directly from an external crystal oscillator. I > tried looking at unconstrained paths in the timing analyzer, but couldn't > see anything suspicious... > > Any ideas to where to look? > > Thanks, > /Mikhail It could be a reset path, the timing analyzer doesn't check them unless you add the following to your UCF file ENABLE= reg_sr_q;Article: 65622
Hi. You can use a DALLAS IC "DS1075-100" There is already an FPGA board that use it and it works at 100Mhz. Take a look at http://www.xess.com/ Hernán Sánchez "chuk" <charlesg77@yahoo.com> escribió en el mensaje news:faa526d6.0402010819.3001985b@posting.google.com... > Can anyone recommend a suitable clocking circuitry, crystal or clock > component for clocking an fpga at 100MHz. Thanks > chazzArticle: 65623
"B. Joshua Rosen" <bjrosen@polybus.com> wrote in message news:pan.2004.02.03.17.56.55.882187@polybus.com... > On Mon, 02 Feb 2004 15:15:06 -0500, MM wrote: > > It could be a reset path, the timing analyzer doesn't check them unless > you add the following to your UCF file > > ENABLE= reg_sr_q; I don't think there are any async resets in the core but I will try it... Thanks. /Mikhail -- To reply directly: matusov at square peg ca (join the domain name in one word and add a dot before "ca")Article: 65624
This sounds like a spartan2 deja-vu, no?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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