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> Well I get messages that > it (OCI?) can not get the com1 port but the debugger window pops up. No > green bar in the > source code which indicates that communications is down. I have yet to get > this setup, Stratix board and > debugger to work on anything other than the tutorials. While in the SDk > shell I did move to my project > dir. Jerry, I haven't seen this myself, but the biggest clue here is that GDB is trying to connect to the debug target via COM1 -- recall that the OCI comm/debug core talks through JTAG only! Older releases of Nios had an additional GUI option allowing you to select a debug communication UART (this was before OCI), so I am wondering if this is a case of versionitis. The short of it is: Make sure OCI is enabled in the CPU wizard, generate the system, compile your code using "nb" (nios-build), and then run "nd" (nios-debug) on the object file -- if this still fails feel free to email me your system's .ptf file and the commands you're using to get this going. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 61176
Petter Gustad wrote: > "Martin Euredjian" <0_0_0_0_@pacbell.net> writes: > > >>Is there a way to have more than one computer work on compiling a >>design? > > > The Solaris version of par (Xilinx place and route tool) can do > multiple iterations on multiple hosts (using the -m option to par). Hey, the Linux versionhas that too. I can use that to make an extra process on the local machine in order to put a dual processor to use? -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 61177
Hi All,
Im trying to get audio playback from an XSA-50 and XST2 using the
example code from the Xess website
("Audio project for the XSV Board (Univ. of Queensland)")
The only problem is, that particular example project uses an
Xess board that has SRAM (The XSA-50 has SDRAM).
No problem... just substitute the SDRAM controller example (also from the
Xess website) and incorporate it into the design, right?
Wrong!!!! At least for me.
Im new to all this, so I try as I may, I cant get it to synthesize.
If anyone thinks they might be able to see whats wrong, I can email
you the modified "audiotop.vhd, player.vhd, recorder.vhd,
sdramcntl.vhd" files.
Has anyone done this before? Modifying the audio playback example
for use with an sdram based board?
Thanks!
Erich
p.s. Just so you dont think Im a complete dope (just a partial one),
I did run the sdram memory tester example and also the simple
audio loopback example (it doesnt use memory) and they each work fine!
Article: 61178Hi all, Does anyone know if Altera Quartus II (3.0+) will let me use a parallel port to USB adapter? I just got a new machine, in part so I could upgrade to 3.0 from 2.2 (and in part so everything would go faster), but it doesn't have a parallel port! I basically have three options: waste the only PCI slot in the machine for a parallel port card, use a USB adapter, or special-order a manufacturer-special parallel port interface for the machine with unknown lead time. The question is basically: does Quartus II rely on it being a serial port interface with the traditional I/O ports, or does it handle anything that can drive a printer? Shelling out $300 for the yet-not-in-existence USB-Blaster cable is not realistic, nor is $500 for MasterBlaster which doesn't even handle the active serial configuration devices. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 61179
Does anybody have any experience using many channels of 840 Mbps LVDS data using the Altera Stratix FPGA family? Any pitfalls to avoid or advice? NateArticle: 61180
Thanks for the inputs. I will try these Tuesday at work. I'm pretty sure I checked the box OCI debug box. Doesn't hurt to triple check things. I'm sure its me, and not the board or software. Just would be nice to have an app note titled "Rolling your own system with NIOS and OCI" The tutorials already have everything set up for you. Regards Jerry "Jerry" <nospam@nowhere.com> wrote in message news:vn70f8iodqolc4@corp.supernews.com... > This is from memory since work doesn't have access to newsgroups so here > goes. > > We have a Stratrix development board with the NIOS software package. Along > with that > is FS2 debugger. I have worked through the enclosed tutorials both the HW > and SW. > All was well and the debugger worked fine. I then wanted to add my own > hardware into the > PGA. I created a new project popped open Quartus 3.0 and SOPC builder > creating a NIOS > based system pretty much if not identical to the one in the tutorials. I > used the germs_monitor.c. > Popped open two SDK shells, one for nr -t -r and the other to compile and > down load the > C code. nd -d hello_nios.c and nb hello_nios.out following the tutorial. > Well I get messages that > it (OCI?) can not get the com1 port but the debugger window pops up. No > green bar in the > source code which indicates that communications is down. I have yet to get > this setup, Stratix board and > debugger to work on anything other than the tutorials. While in the SDk > shell I did move to my project > dir. > > Anybody out there have similar experiences? > > Thanks > Jerry > >Article: 61181
I believe there is a way to configure Eudora to pull in just the headers and then filter the spam before pulling in bodies or attachements. I have never taken the time to dig into how to configure this, but if you get that much spam, it might be worth your while in exploring this. There are a number of web sites that explain how to configure Eudora. Ray Andraka wrote: > > Same with v6 of Eudora. It still isn't perfect, and it depends on > you having enough connect bandwidth to pull the crap in before > shunting it off to the junk bin. I wish the ISPs would give an > option of putting it on their servers, or at least run a virus > filter (mine supposedly does, but I see no evidence to support > it). > > Mike Treseler wrote: > > > Robert Sefton wrote: > > > > > I'm curious how other people are avoiding, filtering out, or > > > fighting back against this crap. > > > > The latest version of netscape (and mozilla) has > > a most excellent junk mail router. It does a > > good job right out of the box and you can train it > > further by example rather than by keyword. > > > > -- Mike Treseler > > > > -- mike.treseler@flukenetworks.com > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61182
Hi Andres, You should take a look at the lpm_ram component provided as part of Quartus. There is a good explanation of it provided in the Quartus Help file. LPM_RAM provides you with a parameterized memory; you should be able to make your own wrapper around it if you wish. Quartus will automatically map your RAM into the correct set of M4K memories on Cyclone. If you target Stratix, Quartus will automatically select the best memory type (M512, M4K, MegaRAM) to implement your memory. Regards, Paul Leventis Altera Corp. "Vazquez" <andres.vazquez@gmx.de> wrote in message news:eee19a7a.0309290552.72b03494@posting.google.com... > Hello, > >>>> >>>> Big quote deleted by Archive Owner >>>>Article: 61183
Robert, I just got back from a week long trip, and my computer is STILL crunching away -- there is a good reason I don't use my Altera email address here. Ever some kids in a class I TAed decided to post my email to a couple of porn mailing lists, this email address has been "dirty" if you excuse the pun :-) You can stop AntiVirus from notifying you for every email virus. Do the following: (1) Double click your AntiVirus icon in the system tray (2) Click "Options" (3) Under the Internet tab, click on "EMail" (4) Click the "Repair then silently delete if unsuccessful". Bye-bye irritating message. I'd also suggest disabling "Display tray icon" and "Dispaly progress indicator when sending email" as these two things are slow, and seem to chew up system resources. As for filtering your spam, there are many options floating around, most of which have been covered by previous posters. Good luck, Paul Leventis Altera Corp. "Robert Sefton" <rsefton@nextstate.com> wrote in message news:qBXdb.26560$5z.12269@twister.socal.rr.com... > Thanks for the info, everybody. I have a spam filter that steers > about half of the normal junk into my delete folder. I've become > inured to this stuff. It's the MS emails with virus attachments > that force me to click on a Norton warning box for each one that > has put me over the edge. It takes me at least 15 minutes each > morning now to manually wade through it all. I'm going to abandon > this address today. It's beyond salvaging. > > RJS > > "Robert Sefton" <rsefton@nextstate.com> wrote in message > news:YVsdb.12231$T46.6679@twister.socal.rr.com... > > I've had the same email address for almost eight years now, and > > I've never tried very hard to hide it, meaning that when I post > to > > public forums like this I use my real email addr. I'm now > > receiving on the order of 300-400 (brutally repetitive) spam > > emails per 24hr period, and in the last couple of weeks I've > been > > getting about 100-200 bogus > > Microsoft-security-patch-with-virus-attachment emails per day on > > top of that (Norton Antivirus pops up a warning box for each one > > it detects and I have to manually step through them). I've been > > patiently waiting for the Microsoft patch garbage to die off, > but > > it hasn't. > > > > I'm a consultant and have my own domain name (nextstate.com), > but > > I've finally decided to abandon it and start using a roadrunner > > email address. I won't bore you with my rage and frustration, > but > > I'm curious how other people are avoiding, filtering out, or > > fighting back against this crap. Shouldn't the ISPs be attacking > > this problem with a little bit more enthusiasm? > > > > Very pissed off in San Diego, > > > > RJS > > > > > >Article: 61184
Is there any way to estimate the bit error rate of a data bus that passes through a Xilinx FPGA? I have input gates, the block RAM, and output gates involved in the system, and I would like to predict the error rate of data passing through. KevinArticle: 61185
Hi SneakerNet (probably not the name your parents gave you ;-)),
In addition to the aforementioned PLL megacore user's guide, I'd also
suggest you take a peak at Chapter 6 of the Cyclone data book. You can find
it here:
http://www.altera.com/literature/lit-cyc.html
This Chapter discusses the 1 or 2 PLLs present in Cyclone. They are
identical to the Fast PLLs present in the Stratix family. Each PLL provides
you with three clocks that are generated off of one reference clock. There
are two internal clocks (C0 and C1) and one external clock (E) that is fed
to pin for use on your board. The three outputs share a common clock
pre-scale (N) and divider (M). Each output can be independently post-scaled
(G0/G1/E counters), and can be phase shifted relative to a reference clock
(usually a fed back clock from the core).
The relationship of the clock frequencies is as follows:
f(C0) = f(In) * M/N/G0
f(C1) = f(In) * M/N/G1
f(E) = f(In) * M/N/E
But this is detail. I believe all you need to do is use the PLL MegaWizard
and tell it the frequencies you'd like the PLL to generate and it will pick
the appropriate M, N, G0, G1, and E values for you.
Regards,
Paul Leventis
Altera Corp.
"SneakerNet" <nospam@nospam.org> wrote in message
news:eaIdb.161813$JA5.3986469@news.xtra.co.nz...
> "Kenneth Land" <kland1@neuralog1.com> wrote in message
>>>>
>>>> Big quote deleted by Archive Owner
>>>>
>
Article: 61186Hi Prashant, Even without seeing your code, it is possible for us to give you some hint of what's happened. You could, for example, include the report file from the two runs. I'd suggest opening up an issue with mysupport.altera.com and an AE will be happy to help you out. Don't let all the two's in Quartus II 2.2 fool you -- our goal is *not* to double the number of LEs in your design :-) Regards, Paul Leventis Altera Corp. "Prashant" <prashantj@usa.net> wrote in message news:ea62e09.0309270932.418551e@posting.google.com... > > > > Are you absolutely sure you implemented the exact same code? > > > > =-a > > > Yes, I am. Just copied the files from one directory to another. I > can't send the code to Altera because its proprietary. Wanted to check > if anyone else has seen a similar problem and has managed to solve it. > > Thanks, > PrashantArticle: 61187
Hi Paul, Yeah haha on the name bit LOL Anyway yeah i got the pll to work though the megawizard . However thanks for the indepth explanation, as I like to understand whats going on (and was getting confused regarding C0, C1, and E0). I 'll take a peak at the link you have given me. Thanks Paul. "Paul Leventis" <paul.leventis@utoronto.ca> wrote in message news:3e6eb.161794$Lnr1.86972@news01.bloor.is.net.cable.rogers.com... > Hi SneakerNet (probably not the name your parents gave you ;-)), > >>>> >>>> Big quote deleted by Archive Owner >>>>Article: 61188
>Is there any way to estimate the bit error rate of a data bus that >passes through a Xilinx FPGA? I have input gates, the block RAM, and >output gates involved in the system, and I would like to predict the >error rate of data passing through. I'm missing something. What kind of errors are you interested in? If your design is clean, the error rate from everything short of cosmic rays should be 0. Or at least low enough so that it is very very hard to measure. Note that "clean" includes the logic and power supply and SI on the input and output sides. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 61189
Hi SneakerNet, I just noticed we have VERY handy application note for you -- AN307 (available on www.altera.com) describes how to migrate from a Xilinx design to an Altera design. There is a section dedicated to DLL to PLL conversion that should be able to help you out. Below is my attempt at explaining things before I found this app note. In Altera's FPGAs, we've got PLLs, which provide a superset of the CLKDLL function you're trying to use. You'd want to setup your PLL to use CLKIN as its input inclk0, hook up the C0 port to GCLK signal and C1 port to CLK signal, don't apply any phase shift, and use the C0 port to compensate the PLL output. Connect RST to the areset port, and LOCKED to the locked port. You'll want to setup your C1 port to have a 2x frequency multiplier on it. The Lock and Reset signals have some sort of equivalent that I can't recall. You can do this all through the allpll megafunction. The BUFGs are not necessary in Altera parts. In Xilinx parts, these buffers are needed to explicitly indicate that you want a signal to be driven onto the global clock network. Quartus allows you to make "global" assignments to nets, but it automatically promotes anything it finds that looks like a clock net, as well as high-fanout or asynchronous signals if there are enough global clocks available. The PLL output nets will be automatically promoted to global clock nets for you, and the PLL input will be assigned to the associated input clock pin. Also, I should point out that there are four USB cores listed on our Intellectual Property page (www.altera.com) under Interfaces & Peripherals under USB. All are available for free trial under our OpenCore evaluation program. Regards, Paul Leventis Altera Corp. "SneakerNet" <nospam@nospam.org> wrote in message news:h9ocb.158045$JA5.3882825@news.xtra.co.nz... > Hi Antti >>>> >>>> Big quote deleted by Archive Owner >>>>Article: 61190
Hi Jon, > Well, he's certainly using the right (read ONLY) architecture that will > do it. > I got started with Xilinx on a project where I needed 72 flip-flops on a > board, all essentially asynchronous from any other. (This was a timing and > logic controller for nuclear detector applications). Xilinx was the ONLY > architecture that could handle lots of acynchronous clocks at the time. It > may still be. There certainly can be complications with things like this. I'm curious -- why do you believe that "ONLY" Xilinx architectures will work for "asynchronous" clocks? I know the Stratix/Cyclone families of Altera very well, and cannot see why they cannot handle such designs. I am also hard-pressed to figure out where the defficiency is in APEX/FLEX too, though I am less familiar with them. One thing I'd like to point out is that Stratix (when I compare to Virtex-II) has significantly more global clocking available. There are 16 global clocks (8 to each quadrant) in Virtex II, while Stratix has 16 truely global clocks, plus 16 quadrant clocks (4 per quadrant) and 2 quadrant/octant fast clocks. In a 1S80 device, this means there are a total of 48 independent clocks available to you. What does this mean? You're less likely to have to rely on locally routed clocks or other such things that make getting a design right that much harder. Regards, Paul Leventis Altera Corp.Article: 61191
Hi Sebastian, Prof. Steve Wilton's group at the University of British Columbia is doing work on a Programmable Sytem-on-a-Chip. They generate HDL for an arbitrary sized FPGA core, and implement it in Standard Cells on a ASIC. The tool also spits out a compiler for the core (p & r + bitstream generator). They published a paper at CICC on it, and have some other publications. Take a peak at http://www.ece.ubc.ca/~stevew/soc.html. Regards, Paul Leventis Altera Corp. "Sebastian Lange" <Sebastian_Lange@gmx.de> wrote in message news:6877ff81.0309220526.2f5b7d3e@posting.google.com... > This post may seem a bit awkward, but has anyone ever come across a > VHDL or > Verilog implementation of an FPGA? It would be very instructional to > have a > look at it. IMHO, it should be at any rate possible to implement a > small FPGA as a bit file sitting on top of another FPGA. Our group is > currently working on some ideas for minimizing the reconfiguration > data in dynamically reconfigurable FPGA applications. > It would be very kind if anyone could point me to any resources... > Thank you so much in advance... > > SebastianArticle: 61192
Hello again Paul ;o) LOL, tell you what, I already cracked it. I found that document sometime back now *grins*. And I also cracked that the CLKDLL is just a pll *grins again* and thus I had posted another msg (which you have already replied before) but once again I beat you to it. I cracked it before you replied ;o). Anyway thanks for taking time in explaning the Xilinx components. Regarding the free USB Cores from Altera website. Service I would give umm 10% *no offence*. I had to log into that page and request the core nearly 10 times before someone contacted me from Altera. Then after 2-3 days they told me that USB 2.0 core is not functional so i asked for usb 1.1 core. Then they asked me hundreds of questions of why/what for/how long etc etc. When I finally got it, it was only licenced for a month (which passes by just like that as I'm working on this USB project part time. Anyway I found a site that had the full VHDL USB core free of cost (without any need for any hardware). I'm stuck at the windows driver now. Rest is all ready to go.. Any help on how to install a generic usb driver? Thanks for your response Paul. Bye "Paul Leventis" <paul.leventis@utoronto.ca> wrote in message news:IK6eb.162179$Lnr1.32740@news01.bloor.is.net.cable.rogers.com... > Hi SneakerNet, >>>> >>>> Big quote deleted by Archive Owner >>>>Article: 61193
Here is a perfect example of what is wrong with Marketing in engineering companies. I recently asked Xilinx for a "Spartan-3 Resource CD". It has been a couple of weeks since I requested it, so I don't remember if I expected it to contain something especially useful (like a copy of Webpack) or if I thought it would contain only data sheets. In any event, it came today. It does not contain Webpack. It only uses less than 100 MB of the available 650 MB to provide a few data sheets, app notes and the Acrobat reader. What's more, when it autostarted on loading the CD, it opened a window for Flash player. But this Flash player does not seem to work correctly and I can't use it to view anything past the second level of menu. I can read any of the data sheets on the CD without the viewer. But what is the point of spending a lot of time on this silly viewer only to have it not work on an otherwise functional machine? Also, what is the point of sending out this sort of marketing drivel for free and yet charging to send out "free" software which is much harder to download intact from the web site? I can download data sheets and app notes easily even over my slow modem connection. IIRC, the Webpack is about 180 MB for the newest release. Why does this necessitate a charge to get a copy on CD when CDs are clearly considered a minor expense? In volumes of 1000's CDs only cost around a dollar to make and mail including US postage. In general, I find marketing at most companies to work against their best interests. But then they do make for good copy in the Dilbert column. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61194
I have just installed Webpack 6.1 on an XP system from the full 188MB installation and applied the service pack 1. Installation went smooth, but the help doesn't work. When I click on "ISE Help Contents" IE opens but with its left pane empty, so I can't browse. It seems that something is wrong with Java and the Xilinx knowledge base in fact points to this issue, however I have the Sun Java Runtime Environment installed as recommended. That's not all however. The Online documentation (pdf) doesn't open at all! I compared this installation with ISE5.2 and it seems that pdf files are completely missing! Same thing can be said about the tutorials. They are missing too! Does anyone know what is going on here? Is it supposed to be this way? Thanks, /MikhailArticle: 61195
Hi, Well, serves me right for going away... all my posts are for naught :-) One small correction: DLLs are *not* PLLs -- though their first-order behaviour seems similar. They are fundamentally different approaches to solving the same problem. DLLs pass an input clock through a programmable delay chain, and adjusts delay until the edges of the output clock and input clock align. PLLs synthesize a clock via a VCO and phase shift the resulting clock relative to the input clock. This means high-frequency jitter on the input is filtered out in a PLL, but transmitted in a DLL. PLLs usually have better clock frequency synthesis options, as they can include multiply/divide counters in their feedback loop; DLLs can provide some such capabilities via digital hardware, but it is very limited. There are other differences between the two in how they respond to low- and high-frequency jitter/drift, their noise susceptibility, range of operation in input/output frequencies, granularity of phase/frequency adjustment, response to temperature/voltage variation, and numerous other areas that I can't recall precisely. Which is better depends on your application, though generally speaking PLLs provide a more versatile solution. Obviously we at Altera feel that PLLs are the better choice for our users, as this is what we have chosen to build on all of our devices since APEX. Stratix includes up to 12 PLLs of various flavours. I can't help you on the device driver front. I'll pass on your comes re: usb core availability and your experience with the web to the appropriate groups. Regards, Paul Leventis Altera Corp. "SneakerNet" <nospam@nospam.org> wrote in message news:_x7eb.163252$JA5.4024668@news.xtra.co.nz... > Hello again Paul ;o) > >>>> >>>> Big quote deleted by Archive Owner >>>>Article: 61196
On Tue, 30 Sep 2003 03:13:34 -0000, hmurray@suespammers.org (Hal Murray) wrote: >>Is there any way to estimate the bit error rate of a data bus that >>passes through a Xilinx FPGA? I have input gates, the block RAM, and >>output gates involved in the system, and I would like to predict the >>error rate of data passing through. <snip> >If your design is clean, the error rate from everything short of >cosmic rays should be 0. Or at least low enough so that it >is very very hard to measure. > >Note that "clean" includes the logic and power supply and SI >on the input and output sides. Then why do DRAM memory systems include a CRC or parity bit? Certainly there is some non-zero probability that a latch will miss or a gate will experience a random noise spike? If what you say is true, the BER of a disk drive will be entirely the fault of a noisy head, and not the deserializer, cache or bus drivers? KevinArticle: 61197
Hi Nate, Haven't done it personally, but I know we've got many customers doing it. I'd recommend reading "Using High-Speed Differential I/O Interfaces in Stratix Devices". That's a good starting point. http://www.altera.com/literature/hb/stx/ch_5_vol_2.pdf If you require further assistance after reading this resource, I would suggest contacting your Altera rep or opening an issue with mysupport.altera.com. Regards, Paul Leventis Altera Corp. "Nate Goldshlag" <nateg@remove_me_first_pobox.com> wrote in message news:290920032137110056%nateg@remove_me_first_pobox.com... > Does anybody have any experience using many channels of 840 Mbps LVDS > data using the Altera Stratix FPGA family? Any pitfalls to avoid or > advice? > > NateArticle: 61198
Hi Kevin, > >If your design is clean, the error rate from everything short of > >cosmic rays should be 0. Or at least low enough so that it > >is very very hard to measure. > > Then why do DRAM memory systems include a CRC or parity bit? > Certainly there is some non-zero probability that a latch will miss or > a gate will experience a random noise spike? > > If what you say is true, the BER of a disk drive will be entirely the > fault of a noisy head, and not the deserializer, cache or bus drivers? DRAMs include CRC to protect against bit flips in their RAM cells. The thing they worry about are alpha particle and neutron strikes. When the strike occurs, it can create a momentary current that flips the state of the RAM cell -- it's a function of the number of RAM cells and the resilience of each cell. The bigger the cap of the cell, the harder it is to flip the value. The more there are, the higher the chance that a strike will affect a given chip. There are some people who are starting to worry about particle induced glitches in logic/routing, but the consensus is that isn't a problem yet. For those people who are very paranoid, there are techniques such as triple modular redundancy (think of it as a circuit in triplicate that takes a best two-out-of-three result) that essentially reduce the chance of logic faults to zero. A far more common cause of logic faults is poor design -- if your design is sensitive to momentary glitches (i.e. asynchronous) you are much more likely to have a problem if some event causes a glitch. Most often, this is due to cross-talk or other such down-to-earth electrical issues. We design the routing in our FPGAs so that they will not glitch even with worst-case attackers. BTW, if I recall correctly, the biggest cause of BER in a hard disk is due to the tinyness of the bits they read & write -- they ain't 1's and 0's at that point, more like best guesses :-) You also get bit errors in the communication medium (cheap ribbon cable) connecting the hard disk to the HDD controller. Regards, Paul Leventis Altera Corp.Article: 61199
On Tue, 30 Sep 2003 04:49:44 GMT, Kevin Kilzer <kkilzer.remove.this@mindspring.com> wrote: >On Tue, 30 Sep 2003 03:13:34 -0000, hmurray@suespammers.org (Hal >Murray) wrote: > >>>Is there any way to estimate the bit error rate of a data bus that >>>passes through a Xilinx FPGA? I have input gates, the block RAM, and >>>output gates involved in the system, and I would like to predict the >>>error rate of data passing through. ><snip> >>If your design is clean, the error rate from everything short of >>cosmic rays should be 0. Or at least low enough so that it >>is very very hard to measure. >> >>Note that "clean" includes the logic and power supply and SI >>on the input and output sides. > >Then why do DRAM memory systems include a CRC or parity bit? >Certainly there is some non-zero probability that a latch will miss or >a gate will experience a random noise spike? > >If what you say is true, the BER of a disk drive will be entirely the >fault of a noisy head, and not the deserializer, cache or bus drivers? The issue with DRAM is that they occupy such a large portion of the die and that they are optimized for size to hold the minimum charge necessary to keep a bit till the next refresh cycle. This makes them particularly vulnerable to various forms of radiation. If you notice, there are very few designs where the error probability of random logic is controlled against errors caused by radiation. In terms of disk drives, the main problem is the uncertainty in the bit lengths on the media and the clock/data recovery after data is captured by the head in addition to the noise added by the head. Again errors caused by radiation is not a major concern in the data path and even in cache as the cache is most probably static memory which is more resistant to such errors. With a well tested (with external scan or BIST etc) logic, the probability of radiation induced errors are completely negligible in almost all of the designs, unless they involve large quantities of DRAM or used in space or life critical applications. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations
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