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Hi people, I was using an Altera FPGA for my WLAN MAC validation, In that one kind of the primitive memory components are named as 'altqpram'. If I need to use this memroy with different configurations (Ex:- different data bus widths) I can genrate one altqpram template using the Mega Wizard (GUI utility), and for my other memory cofigurations I can change the para- meter settings manually, by changing the file generated by megawizard. Now, I am needing to migrate to Xilinx Virtex-II, I am using Xilinx - ISE on WIndows. When I use coregen to generate a primitive (memory), coregen creates several files. Among these are the netlist files for the core generated. Now, if I need a different memory component (Say, with bus width changed) I have to regenerate the component with a differnet name. I have not been able to find a way to get this configuration by manually altering the files generated by coregen (This doesn't look straight forward, atleast!). Has somebody figured out a way of doing this?Article: 61276
Hi Andres, The problem isn't your "writing" signal -- it is the asynchronous clearing of the memory. Memories are not clearable -- if you want to clear your memory, you must do so by iterating through it and writing 0s. Regards, Paul Leventis Altera Corp. "Vazquez" <andres.vazquez@gmx.de> wrote in message news:eee19a7a.0310010044.249af36e@posting.google.com... > Dear Mr Leventis, >>>> >>>> Big quote deleted by Archive Owner >>>>Article: 61277
Hi Ray,
If you don't need to receive email that your name is only in the bcc
box, you can put a filter "delete all email from server if my name is not in
the to or cc box" (99% of spam use the bcc box).
regards
fe
"Ray Andraka" <ray@andraka.com> wrote in message
news:3F788635.431A955@andraka.com...
> 300-400/day isn't that bad. I've been getting that in under 2 hours.
> My ISP has been next to useless on resolving it. I did change to the
> latest paid version of Eudora, which has a spam filter built in. That
> has done a pretty good job of culling out the junk. I also had to set
> the virus sw to automatically delete virus files rather than prompt me
> to do away with the annoying dialog boxes that were popping up every
> couple of seconds. It is still not an ideal solution, as I can't go
> off-line without having the mailbox at the ISP overflow within a few
> hours, and I still have to cull the junk mail box to recover the
> occasional false positive. It has cut down the time involved
> however. In my case it has been two major sources this month: the
> microsoft patch virus, and viruses embedded in "failed delivery"
> "returned" emails.
>
> I too am a consultant, and I depend on having my email address in the
> clear to get the traffic into me. This whole spam thing is an
> irritant that was not at the debilitating level until this summer.
>
> Robert Sefton wrote:
>
> > I've had the same email address for almost eight years now, and
> > I've never tried very hard to hide it, meaning that when I post to
> > public forums like this I use my real email addr. I'm now
> > receiving on the order of 300-400 (brutally repetitive) spam
> > emails per 24hr period, and in the last couple of weeks I've been
> > getting about 100-200 bogus
> > Microsoft-security-patch-with-virus-attachment emails per day on
> > top of that (Norton Antivirus pops up a warning box for each one
> > it detects and I have to manually step through them). I've been
> > patiently waiting for the Microsoft patch garbage to die off, but
> > it hasn't.
> >
> > I'm a consultant and have my own domain name (nextstate.com), but
> > I've finally decided to abandon it and start using a roadrunner
> > email address. I won't bore you with my rage and frustration, but
> > I'm curious how other people are avoiding, filtering out, or
> > fighting back against this crap. Shouldn't the ISPs be attacking
> > this problem with a little bit more enthusiasm?
> >
> > Very pissed off in San Diego,
> >
> > RJS
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
> "They that give up essential liberty to obtain a little
> temporary safety deserve neither liberty nor safety."
> -Benjamin Franklin, 1759
>
>
Article: 61278OK, I tried the Xilinx web installer again. It didn't fail this time, but I got exactly the same result as with the two previous installations: pdf files are not installed at all and the HTML/Java help still doesn't work This is starting to drive me crazy... /MikhailArticle: 61279
Peter,
I asked the experts at Altera, and they verified that using a parallel
port to USB adapter will not work.
- Subroto Datta
Altera Corp.
"H. Peter Anvin" <hpa@zytor.com> wrote in message
news:blakq0$nm$1@cesium.transmeta.com...
> Hi all,
>
> Does anyone know if Altera Quartus II (3.0+) will let me use a
> parallel port to USB adapter? I just got a new machine, in part so I
> could upgrade to 3.0 from 2.2 (and in part so everything would go
> faster), but it doesn't have a parallel port! I basically have three
> options: waste the only PCI slot in the machine for a parallel port
> card, use a USB adapter, or special-order a manufacturer-special
> parallel port interface for the machine with unknown lead time.
>
> The question is basically: does Quartus II rely on it being a serial
> port interface with the traditional I/O ports, or does it handle
> anything that can drive a printer?
>
> Shelling out $300 for the yet-not-in-existence USB-Blaster cable is
> not realistic, nor is $500 for MasterBlaster which doesn't even handle
> the active serial configuration devices.
>
> -hpa
>
> --
> <hpa@transmeta.com> at work, <hpa@zytor.com> in private!
> If you send me mail in HTML format I will assume it's spam.
> "Unix gives you enough rope to shoot yourself in the foot."
> Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64
Article: 61280On Wed, 01 Oct 2003 06:21:04 -0700, Amontec Team, Laurent Gauch wrote: > Hi all, > > Sorry to ask about analog question, but it 's relative to FPGA too. > > Do you know a schematic to do 'Automatic I/O voltage sensing' as XILINX > does with the ParallelCable IV. > > I am designing a new JTAG interface (USB), and I want to be able to > drive correctly the target JTAG signals (3.3V, 2.5V, 1.8V, 1.2V). > > Are there any lvttl level shifter device to do this work? > > Thanks for your advice. > > Laurent Gauch > www.amontec.com On the recieve side, probably the best thing is to use a LVDS pair with one side for your input (maybe divided by 2 with low value resistors to be able to get the 3.3V range) and the other side biased with a PWM generated voltage to set the input threshold. The common mode range and speed of the Xilinx LVDS inputs is impressive... Peter Wallace Peter WallaceArticle: 61281
Robert, How do think that you can send two differents addresses at the same ram and output 2 differents values at the same time? It's impossible. So your synthesiser is bright and did the job for you by infering 2 ram (same write address and different read address). regards fe "RobertP" <rpudlik@poczta.onet.pl> wrote in message news:ble3kl$884$1@news.onet.pl... > OK, I found answer to problem 1). > At the start of simulation some signals were not initialized. > Also in the test bench I was assigning 'Z' to adrress input (this RAM is > part of a bigger design, and Address bus is bidirectional). > > The result was as I described - I could read/write proper values from/to > the RAM. > > I still don't have answer to question 2). > > -- > Robert Pudlik >Article: 61282
Hi All, My design has many multipliers of different input/output widths. I need to implement it on Xilinx Virtex II XC2V6000 FPGA. I tried using CoreGen to generate the multipliers but looks like for each set of input/output widths I need to generate a separate multiplier. This is very difficult to manage. Is there any way to parameterize the CoreGen multiplier so that by using one generic wrapper, the same code can be reused for all the multipliers needed in the design? I am using Verilog HDL. Sorry if this question has already been asked. I tried searching but could not get any answers. Regards, Kiran.Article: 61283
Kiran <kirandev@msn.com> wrote: : Hi All, : My design has many multipliers of different input/output widths. I : need to implement it on Xilinx Virtex II XC2V6000 FPGA. I tried using : CoreGen to generate the multipliers but looks like for each set of : input/output widths I need to generate a separate multiplier. This is : very difficult to manage. Is there any way to parameterize the : CoreGen multiplier so that by using one generic wrapper, the same code : can be reused for all the multipliers needed in the design? I am : using Verilog HDL. : Sorry if this question has already been asked. I tried searching but : could not get any answers. Using Ise 5.1 and verilog, wire [18:0] a,b; wire [35:0] c; assign c = a*b; invoked a multipler. On Spartan 2 it was built from LUTs, and Spartan 3 the Multiplier blocks were used. Why then use coregen? Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 61284
I might be wrong but distributed RAMs don't support the dual-port operation you're using (one R/W and one R port). Block RAMs don't support async read (as the warning suggests). So the synthesizer is pretty much hosed. What it can do is to use two sets of distributed RAMs, write them simultaneously and read them independently as you've specified. Quite neat it did so though, I didn't know XST can be that claver... Regards, Andras Tantos "RobertP" <rpudlik@poczta.onet.pl> wrote in message news:ble3kl$884$1@news.onet.pl... > OK, I found answer to problem 1). > At the start of simulation some signals were not initialized. > Also in the test bench I was assigning 'Z' to adrress input (this RAM is > part of a bigger design, and Address bus is bidirectional). > > The result was as I described - I could read/write proper values from/to > the RAM. > > I still don't have answer to question 2). > > -- > Robert Pudlik >Article: 61285
Tim, Since this is an input, there is no current going into/out of it (unless you go to the clamp diode limit). So assuming that the diodes are not clamping, it is purely a voltage issue. No ignorance here at all, the effect that is actually seen (with tests at > 4.5V) result in increased leakage, but no functional failure of the IOB (it still works, but does not meet the < 10uA IO pin spec). This is the subject of research and PhD thesis material among the technology communities. Austin Tim wrote: > Austin Lesea wrote: > > > Failure mode is simple: the stress on the pmos output device when > > the IO pin is used as an input shall not exceed that stated in the > > abs max spec (4.05V for example on Virtex II Pro and Spartan 3, > > +3.75V abs max Vcco, and -0.3V abs max Vio on the io pin). If this > > stress is exceeded, it will eventually cause the IO to become leaky > > (ie > 10uA IOB leakage current spec will be violated). This increase > > in leakage may, or may not affect your system. > > If you go outside the limits with Vio and are current limited > to 10uA will there be a problem? How about 100uA? 1mA? > > Please excuse my ignorance on this stuff....Article: 61286
Paul, You forgot that we also have dedicated clocks to deal with the clock domains from high-speed IOs, which are localized around the IOs and the dedicated serialization / deserialization hardware we have for high-speed LVDS. There are 16 extra dedicated clocking resources around the IOs for this, giving a total of 64 independent clocks on dedicated resources in a 1S80. Vaughn "Paul Leventis" <paul.leventis@utoronto.ca> wrote in message news:<oR6eb.162258$Lnr1.141133@news01.bloor.is.net.cable.rogers.com>... > Hi Jon, > > I'm curious -- why do you believe that "ONLY" Xilinx architectures will work > for "asynchronous" clocks? I know the Stratix/Cyclone families of Altera > very well, and cannot see why they cannot handle such designs. I am also > hard-pressed to figure out where the defficiency is in APEX/FLEX too, though > I am less familiar with them. > > One thing I'd like to point out is that Stratix (when I compare to > Virtex-II) has significantly more global clocking available. There are 16 > global clocks (8 to each quadrant) in Virtex II, while Stratix has 16 truely > global clocks, plus 16 quadrant clocks (4 per quadrant) and 2 > quadrant/octant fast clocks. In a 1S80 device, this means there are a total > of 48 independent clocks available to you. What does this mean? You're > less likely to have to rely on locally routed clocks or other such things > that make getting a design right that much harder. > > Regards, > > Paul Leventis > Altera Corp.Article: 61287
> Can I specify a name for the clock net somewhere in the VHDL code? No need to reply, I found it out by experiments. The tools recognize the signal when put manually into the .ucf, although it doesn't show up in the gui constraints editor: NET "iclk" TNM_NET = "iclk"; TIMESPEC "TS_iclk" = PERIOD "iclk" 25 MHz HIGH 50 %; MarcArticle: 61288
I'm looking at doing a design with Apex-II parts and will probably need to use the Verilog synthesizer that comes with Quartus. My last experience (multiple years ago) was very unpleasant - lots of synthesis bugs. Has this gotten better? My experience with XST synthesis recently has been pretty good, so I'm debating about sticking with Xilinx for this next project or jumping to Altera since their Apex-II parts seem to fit my application a bit better. Any goog/bad stories? Thanks! John ProvidenzaArticle: 61289
I had tried the program on my computer at work which I don't have anymore. I had tried it back in January. I saw your posting and thought I'd point a finger in that direction for you to look at. Something isn't totally right with the way that windows handles USB devices. I have a new Compaq scanner with a new Compaq computer. They didn't even have the driver preinstalled. I had to use the scanner CD to install the drivers. Now, whenever I plug in another USB device (new or already installed) windows scrambles the scanner driver. Then windows tells me how it found "new hardware" and installs a do-nothing unknown device driver. Installing the scanner drivers from the CD doesn't work. I finally went to the windows answer database and found that I have to uninstall ALL USB devices, including the motherboard USB controllers, reboot and let windows find everything, then install the scanner driver, then plug in the scanner. Everytime the power goes out I have to do this procedure all over again. I had to get a big UPS to put all my equipment on. Microsoft engineers should be fixing the functionality of the operating system instead of plugging the back-door holes THEY left for hackers to get in. Maybe when the government locks up one of those childish hackers they should also lock up the Microsoft engineer that left the door open in the first place. Sorry about all the venting. Regards, Colin "SneakerNet" <nospam@nospam.org> wrote in message news:cFpeb.164194$JA5.4050546@news.xtra.co.nz... > Hi Again Colin >>>> >>>> Big quote deleted by Archive Owner >>>>Article: 61290
"Vinh Pham" <a@a.a> wrote in message news:<R_qeb.18681$Ak3.11446@twister.socal.rr.com>... > > Marketing is full of engineers who couldn't design their way out of a > paper > > bag. > > Ever seen three design engineers standing around, trying to figure out how > to work a Xerox machine? That's not a design-engineering problem -- that's a user interface problem. The design engineer did NOT spec how the UI interacts with the human user. The design engineers were given a task: "Put ten buttons and a display on this board. Here's what should happen in response to keypresses." It's up to the company's usability people (if such people exist) to determine what sort of front panel is needed and to ensure that whatever they come up with makes sense. Besides, if an engineer designed the interface, it'd be all hex :) -aArticle: 61291
John Providenza wrote: > I'm looking at doing a design with Apex-II parts and will > probably need to use the Verilog synthesizer that comes with > Quartus. My last experience (multiple years ago) was very > unpleasant - lots of synthesis bugs. Yes, synthesis used to be unusable. > Has this gotten better? Yes, it seems to work quite well now. I'm still using leo for production work until I spend some time qualifying it. > My experience with XST synthesis recently has been pretty good, > so I'm debating about sticking with Xilinx for this next project > or jumping to Altera since their Apex-II parts seem to fit my > application a bit better. That's a tough call. If you want to reuse code Xilinx-only code I would stay. If it's mostly new code, I would go. -- Mike TreselerArticle: 61292
There used to be some preliminary information on the V2Pro-X (10-Gb transceivers) on the Xilinx website. Anyone know what happened to those pages/where they dissapeared to? Also, does anyone else notice that the Xilinx website seems very laggy about initiating connections? And has anyone started playing with the RocketPhy or other 10-Gig transceivers, especially for 10-GigE? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 61293
lecroy wrote: > > Look at the IBIS simulation at the output pin to see what the voltage excursions are, an be sure they stay > > within the specifications sheet and user's guide. > > Well, not like Mr. Pease, I have always been a big user of simulation > as one tool. Certainly, not the last tool and I don't see it > replacing the VNA any time soon as a way to get the 'real' picture of > what is going on. But the question I always have when some one throws > out the simulation card is how good is your model. When Xilinx > released the IBIS models for the S3, how much data was it based upon? > Have they continued to update the model as parts are being tested? > How much do you trust it? That is a *very* important question. We have seen the timing files go through iteration after iteration of refinement. At what point can be believe that the IBIS models will be stable? > > If you have a specific waveform, you may email it to me directly, and I will get the "final word" from the > > designers and technology groups. > > Do I have a specific waveform, no. I am asking a general question > about the S3. Just how sensitive it really is and what precautions do > I need to take to make it work. Because each layout is different, the > loading can be anything if you consider all of the failure modes. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61294
Austin Lesea wrote: > > lecroy, > > See below, > > Austin > > lecroy wrote: > > > I have been away, but was glad to see people are starting to talk > > about this possible issue with the S3. > > > > > The confusion is (to many) that the question is what does the reflection back to the driver do to the driver, > > right? This is a fairly obscure distinction, so I would not expect every one of the 200+ hotline CAEs to get > > it perfectly right on the first try. > > > Did you submit multiple cases? Or call some folks you know? (IE how did you get multiple answers...) It > > would help if you worked this thru the hotline, as they need to learn from their mistakes, and improve their > > service sometimes. If you are talking about it here, then we are not closing the loop! > > > > Well, like I had stated early on, I had spent about two months working > > the channels at Xilinx trying to get an answer, starting with the > > person who made the original comment about it being a problem. I > > never opened a case with the hotline. I have never found them to be > > useful and it seems their only goal to it to close as many calls as > > possible, not help the customers. That's for a different topic. > > Unfortunate. If you don't ask, you don't get an answer. Try it. If it doesn't work, let us (me) know. You > must prefer doing everything the hardest way possible. We also do not appreciate the slamming of our hotline > staff. I don't understand why you feel the need to shoot the messenger. The hotline staff of most companies is just as Lecroy described, eager to end the call as that is how they are evaluated. Xilinx is no exception and this has been noted here on more than one occasion. This newsgroup is a place of all of us to share our experiences and opinions and I, for one, don't appreciate your criticism of Lecroy's post. If you feel his experience is not typical, then feel free to say so, but certainly you have no expectation that he should not express his experience or opinion. > Theya re all dedicated to helping our customers succeed, as that is what sells parts, not "closed > cases." If a hotline engineer can not resolve the problem within a fixed amount of time, it is escalated. Once > escalated, it then goes up the ladder til it reaches someone who can resolve the issue. That is your opinion of how the process works. Many people have had different experiences. Often it is not escalated until the customer requests. Overall the experience can be so frustrating that the customer doesn't push very hard to get a real answer and gives up after a few conversations. Anyone can be in denial about a problem with their company. But that does not make the problem go away. The problem is also not eliminated by comparing yourself to your competition and saying "we are better than they are". It can still be a problem. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61295
I can't say I really understand your problem statement. I also don't
see how your code is solving the problem. Can you give a better
explanation of the problem? What do you mean "from the byte
boundaries"? Are you counting only the bit sets of {0..8}, {8..16},
{16..24}...? If so, this seems like an easy problem to implement.
John_H wrote:
>
> Greetings,
>
> I need to detect runs. I want to look at 65 bits and show when there are 9
> consecutive 1s or 0s from the byte boundaries resulting in 8 values per
> clock. This should be comfortably done in two logic levels (I need clean
> logic delays).
>
> The idea is simple but the implementation is tough. I'm working with
> Verilog in Synplify, targeting a Xilinx Spartan-3. I have to resort to
> design violence to get the results that I believe are "best."
>
> Any thoughts on how to do this "better?" (the following code likes fixed
> fonts)
>
> - John_H
> =====================================
> module testRun ( input clk
> , input [64:0] bytePlus1
> , output reg [ 7:0] runByte /* synthesis xc_props = "INIT=R"
> */
> ); // INIT included to force register as FD primitive - bleah
>
> reg [23:0] runBits; // I wanted the syn_keep on this combinatorial "reg"
> wire [23:0] runBits_ /* synthesis syn_keep = 1 */ = runBits; // - bleah
> reg [ 7:0] runByte_;
> integer i,j,k;
>
> always @(*)
> begin
> runBits = -24'h1;
> runByte_ = -8'h1;
> k = 0; // overlapping aaa aaaa
> for( i=0; i<64; i=i+j ) // consecutive aaaa
> begin // bit regions 876543210
> for( j=0; (i%8+j<8) && (j<3); j=j+1 )
> runBits[k] = runBits[k] & (bytePlus1[i+j]==bytePlus1[i+j+1]);
> runByte_[i/8] = runByte_[i/8] & runBits_[k];
> k = k + 1;
> end
> end
> always @(posedge clk) runByte = runByte_;
>
> endmodule
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 61296Rick, Here is my 5th try to respond. Maybe I will send it. See below. Austin rickman wrote: <snip> > > > Unfortunate. If you don't ask, you don't get an answer. Try it. If it doesn't > work, let us (me) know. You > must prefer doing everything the hardest way > possible. We also do not appreciate the slamming of our hotline > staff. > > I don't understand why you feel the need to shoot the messenger. I did not shoot him. I merely mentioned that he should try to get support through the normal channels. And if that did not work, to contact the folks who are watching the watchers. And not slam a service that he did not use. > The hotline staff of most companies is just as Lecroy described, eager to > end the call as that is how they are evaluated. Xilinx is no exception > and this has been noted here on more than one occasion. Perhaps in your mind, but to us it is deadly serious, and we deny that your comments are accurate, or truthful. Sure, one can get a bad answer, or a wrong answer, and occasionally an answer that did not meet your timeline; but if that case is closed before you say you are happy, it is cause for dismissal. > > This newsgroup is a place of all of us to share our experiences and > opinions and I, for one, don't appreciate your criticism of Lecroy's > post. OK. Like you said, all opinions are welcome. > If you feel his experience is not typical, then feel free to say > so, I did. > but certainly you have no expectation that he should not express his > experience or opinion. He is free to say anything he wants, as are you. > > > Theya re all dedicated to helping our customers succeed, as that is what sells > parts, not "closed cases." If > a hotline engineer can not resolve the problem > within a fixed amount of time, it is escalated. Once > escalated, it then goes up > the ladder til it reaches someone who can resolve the issue. > That is your opinion of how the process works. No, that is the way it does work. I helped re-write it. And audit it. > Many people have had different experiences. Then let Peter and I know: I want dates, case numbers and names. I want to know of any unhappy customers anywhere. And yes, I would prefer it sent directly, not the newsgroup, so we can research it properly, and get it resolved ASAP. > Often it is not escalated until the customer requests. Uh, that is how it works, the proceedure is that the customer has to say how urgent the matter is AND the time limits have to start getting exceeded. > Overall the experience can be so frustrating that the > customer doesn't push very hard to get a real answer and gives up after > a few conversations. Haven't met any like that. Perhaps there are those who are so timid they can't use a hotline? The customers that I meet are not shy at all about demanding the best service. And right now, if they don't get the answer, they are likely to be part of the next layoff, so it is hard for me to see how a customer would not make every effort to get their problem resolved.Article: 61297
> 2. We read Users Manuals as a last resort. If the user interace is designed Heh yeah, we've stood around the machine while the manual was right there, begging to be read, making a tech writer somewhere pull their hair out. > well, we shouldn't need one. If it isn't designed well, it pisses us off > and we don't want to use the thing :-) Hahaha, it reminds me of the fax machine scenes from the movie Office Space. The one where they beat the crap out of it still cracks me up. > 3. If we figured it out, everyone else would expect us to help them with it > :-) How tired are you of telling friends you work in computers and they > immediately expect you to fix their problems with Word on their PC for them. (cringe) And don't forget about repairing TVs. It seems electrical engineer = electrician :_( > As for marketing being full of engineers who couldn't design their way out > of a paper bag, the key is whether they realize they couldn't design their > way out of a paper bag or not ... Wise words. As long as they stick to what they do well, and leave me to do what I do well. Watchout otherwise.Article: 61298
> It's up to the company's usability people (if such people exist) to > determine what sort of front panel is needed and to ensure that > whatever they come up with makes sense. Yup, usability isn't given much thought these days. And when it's done well, no one notices. > Besides, if an engineer designed the interface, it'd be all hex :) LOL. I had a boss who could multiply two digit hex numbers faster than you could use a calculator. Scary.Article: 61299
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F7B2060.A4FA04B@yahoo.com...
> I can't say I really understand your problem statement. I also don't
> see how your code is solving the problem. Can you give a better
> explanation of the problem? What do you mean "from the byte
> boundaries"? Are you counting only the bit sets of {0..8}, {8..16},
> {16..24}...? If so, this seems like an easy problem to implement.
You have it right - 8:0, 16:8, 24:16.... In the 41 bits illustrated below I
want to note when the sequence across [16:8] (illustrated by the 9 1s below
the count) in result[1].
11010101000101010111101111111111110010101 pattern
09876543210987654321098765432109876543210 count
00000000000000000000000011111111100000000 (reference)
The trouble is that while it seems easy to implement, getting the logic to
come out clean in the implementation - the "pushing the rope" problem -
doesn't comes easily. If one does a loop looking for 8 adjacent equals or
the 8-wide AND of 8 XNORs, the realization takes up 3 levels of logic with
FDR primitives resulting in 2x-3x the resources and about twice the delay.
The code with the two nested for loops breaks up the 9-bit compare into two
4-bit and one 3-bit compare to verify all the 9 bits are equal to each other
and to break the implementation into 2 levels of logic rather than 3+ (the +
being from the flop's reset input taking some extra routing delay).
I'd love a cleaner approach that doesn't come off so complex and gets
realized in the resources it "should" use. It's tough to get it where I
want by pushing on the rope.
> John_H wrote:
> >
> > Greetings,
> >
> > I need to detect runs. I want to look at 65 bits and show when there
are 9
> > consecutive 1s or 0s from the byte boundaries resulting in 8 values per
> > clock. This should be comfortably done in two logic levels (I need
clean
> > logic delays).
> >
> > The idea is simple but the implementation is tough. I'm working with
> > Verilog in Synplify, targeting a Xilinx Spartan-3. I have to resort to
> > design violence to get the results that I believe are "best."
> >
> > Any thoughts on how to do this "better?" (the following code likes
fixed
> > fonts)
> >
> > - John_H
> > =====================================
> > module testRun ( input clk
> > , input [64:0] bytePlus1
> > , output reg [ 7:0] runByte /* synthesis xc_props =
"INIT=R"
> > */
> > ); // INIT included to force register as FD primitive -
bleah
> >
> > reg [23:0] runBits; // I wanted the syn_keep on this combinatorial
"reg"
> > wire [23:0] runBits_ /* synthesis syn_keep = 1 */ = runBits; // - bleah
> > reg [ 7:0] runByte_;
> > integer i,j,k;
> >
> > always @(*)
> > begin
> > runBits = -24'h1;
> > runByte_ = -8'h1;
> > k = 0; // overlapping aaa aaaa
> > for( i=0; i<64; i=i+j ) // consecutive aaaa
> > begin // bit regions 876543210
> > for( j=0; (i%8+j<8) && (j<3); j=j+1 )
> > runBits[k] = runBits[k] & (bytePlus1[i+j]==bytePlus1[i+j+1]);
> > runByte_[i/8] = runByte_[i/8] & runBits_[k];
> > k = k + 1;
> > end
> > end
> > always @(posedge clk) runByte = runByte_;
> >
> > endmodule
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