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Aart van Beuzekom wrote: > > Aart van Beuzekom wrote: > > > Hi, > > > > Can anybody tell me a practical way (in VHDL) to count the number of > > ones in a bit pattern? Counting should be done with combinatorial logic, > > which means that a for-to loop cannot be used here (but being quite new > > to FPGA and VHDL, I'm not even sure). The number of bits to be counted > > is about 30, so a single look-up table is not the solution, using only a > > Spartan II. > > > > Any suggestions? Purpose is amongst others pattern matching, where I > > count how many bits differ from the expected result. > > > > Thanks, > > > > Aart > > > I forgot to mention that the for-to loop cannot be used because I do not > want the system to use any clock cycles - the result just has to be there. There is nothing inherent in a for loop that uses "clock cycles". As long as you don't use a wait statement on a clock edge, you will not have a FF (which is what you are referring to as using clock cycles). Rather than to think of a VHDL solution from the problem statement, I prefer to think in terms of what hardware I would design to solve the problem and then use VHDL to describe the hardware. In your case you need a simple bank of adders to add in succession. You can optimize this for speed or logic which will depend on your means of implementing the design. This will be different in an FPGA with 4 input LUTs vs. a gate oriented array. Once you have decided on an architecture to solve the addition problem, you can then code it in VHDL easily. Very possibly a for loop can be used without creating FFs. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 61151
Hi Bob,
Thanks for your reply! My thoughts were that the common mode
range of the diff amps is quite good so any mismatch in the resistor
values wouldn't matter too much. However, the spec range doesn't work
beyond the rails, so I didn't want to use the diodes to limit the
common mode swing.
I'm fairly sure that it's just the software that stops you
turning the pullup/pulldowns on in diff input mode, a shame because
this would be useful in AC coupled apps. (I'd turn on all four
resistors on the two input pins) I guess it could be a bummer to
charactarise so Xilinx won't support this. Maybe I'll raise a webcase.
thanks again mate, Syms.
"Bob" <nimby1_not_spmmm@earthlink.net> wrote in message news:<zqldb.6531$NX3.2641@newsread3.news.pas.earthlink.net>...
> Symon,
>
> The problem with using the pullup/pulldown idea (if it's even possible) is
> that the values of the pullups and pulldowns are not tightly controlled. The
> common-mode point would thus not be in the middle of your 3.3V supply.
>
> What might work is:
>
> If you're able to enable the pullups, then the intrinsic diodes of the IOB's
> will keep the positive peaks of the signal clamped to one diode drop above
> 3.3V (assuming it's cap coupled from your source). The negative peaks should
> be well below the 3.3V supply. Also, the diode current will be small.
>
> You should check with Xilinx to see if this approach will work, because the
> signal swing may not be within their diffamp's input range.
>
> Bob
>
>
> "Symon" <symon_brewer@hotmail.com> wrote in message
> news:a28bc07f.0309261442.131ae253@posting.google.com...
> > Dear All,
> > Problem.
> > I've just been let down by a oscillator manufacturer. They
> > can only make the ordered 3.3V differential LVPECL oscillator parts
> > work at 5V. Some excuse about their quartz supplier. So, I can't stick
> > 5V PECL into my 3.3V Virtex-E differential input, it's outside the
> > common mode range. So, I could AC couple it with a couple of caps
> > after the PECL driver's emitter resistors. I then need to bias the
> > signal into the common mode range of the VirtexE diff input.
> > Question.
> > Anybody know if I could somehow activate the internal
> > pullup resistor on one input and the pulldown on the other to bias the
> > signal in the middle of the supply? There's already a 100 ohm
> > termination resistor between the pins. Or, any better ideas?
> > cheers all, Syms.
> >
> > p.s. I know I could use more resistors to do this biasing, but the
> > board layout makes this awkward. The VirtexE is, of course, a BGA.
Article: 61152hi everyone, i'm working on my diploma work right now. i have to develop an fpga - circuit. the development-environment has to be linux redhat. does anyone know fpga-developmenttools to write compile and link fpga circuit under linux.Article: 61153
bakito wrote: > does anyone know fpga-developmenttools to write compile and link fpga > circuit under linux. The Quartus CD (synthesis/place+route) has installs for linux, solaris and hp-ux. Quartus inludes modelsim_oem (simulation), but only for windows, solaris and hp-ux Mentor modelsim SE has a linux distribution. -- Mike TreselerArticle: 61154
Latest ISE 6.1i tools from Xilinx support Linux. --Neeraj "bakito" <bakito@gmx.ch> wrote in message news:cf5c43a9.0309290901.770c102c@posting.google.com... > hi everyone, > > i'm working on my diploma work right now. i have to develop an fpga - > circuit. the development-environment has to be linux redhat. > > does anyone know fpga-developmenttools to write compile and link fpga > circuit under linux.Article: 61155
prashantj@usa.net (Prashant) wrote in message news:<ea62e09.0309271630.62d832fe@posting.google.com>... > Hi, > > I'm trying to implement a bidirectional bus in my code. (VHDL, > APEX20K1500E). But I'm having some trouble which brought me to ask the > question : > > How do I specify the direction signal while using a bidirectional bus > ? I dont find myself setting any enable signals when using the > bidirectional bus. I would appreciate it if someone could explain how > this works. > > Thanks, > Prashant Hi Prashant, Try the following piece of code (taken from the VHDL template in the Quartus Text Editor, with a modification) -- Quartus VHDL Template -- Tri-State Buffer (Modified to make __tri_output_name a INOUT) -- Replace the __variable_anme with your variable name -- As the port direction is INOUT __tri_output_name can be used on the right -- hand side of an assignment. -- The __oe_input_name should be set to drive out to 0 so that __tri_output_name can then drive into the chip. LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY __entity_name IS PORT ( __oe_input_name : IN STD_LOGIC; __data_input_name : IN STD_LOGIC; __tri_output_name : INOUT STD_LOGIC ); END __entity_name; ARCHITECTURE a OF __entity_name IS BEGIN PROCESS (__oe_input_name, __data_input_name) BEGIN IF __oe_input_name = '0' THEN __tri_output_name <= 'Z'; ELSE __tri_output_name <= __data_input_name; END IF; END PROCESS; END a; - Subroto Datta Altera Corp.Article: 61157
Don't do it. Clock gating is an ugly and error-prone design methodology. In 99% of all cases there are better ways to design. What are yiou really trying to do? Peter Alfke ====== jose wrote: > I try to do gating clock. > > What I can do?Article: 61158
300-400/day isn't that bad. I've been getting that in under 2 hours.
My ISP has been next to useless on resolving it. I did change to the
latest paid version of Eudora, which has a spam filter built in. That
has done a pretty good job of culling out the junk. I also had to set
the virus sw to automatically delete virus files rather than prompt me
to do away with the annoying dialog boxes that were popping up every
couple of seconds. It is still not an ideal solution, as I can't go
off-line without having the mailbox at the ISP overflow within a few
hours, and I still have to cull the junk mail box to recover the
occasional false positive. It has cut down the time involved
however. In my case it has been two major sources this month: the
microsoft patch virus, and viruses embedded in "failed delivery"
"returned" emails.
I too am a consultant, and I depend on having my email address in the
clear to get the traffic into me. This whole spam thing is an
irritant that was not at the debilitating level until this summer.
Robert Sefton wrote:
> I've had the same email address for almost eight years now, and
> I've never tried very hard to hide it, meaning that when I post to
> public forums like this I use my real email addr. I'm now
> receiving on the order of 300-400 (brutally repetitive) spam
> emails per 24hr period, and in the last couple of weeks I've been
> getting about 100-200 bogus
> Microsoft-security-patch-with-virus-attachment emails per day on
> top of that (Norton Antivirus pops up a warning box for each one
> it detects and I have to manually step through them). I've been
> patiently waiting for the Microsoft patch garbage to die off, but
> it hasn't.
>
> I'm a consultant and have my own domain name (nextstate.com), but
> I've finally decided to abandon it and start using a roadrunner
> email address. I won't bore you with my rage and frustration, but
> I'm curious how other people are avoiding, filtering out, or
> fighting back against this crap. Shouldn't the ISPs be attacking
> this problem with a little bit more enthusiasm?
>
> Very pissed off in San Diego,
>
> RJS
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61159
Same with v6 of Eudora. It still isn't perfect, and it depends on
you having enough connect bandwidth to pull the crap in before
shunting it off to the junk bin. I wish the ISPs would give an
option of putting it on their servers, or at least run a virus
filter (mine supposedly does, but I see no evidence to support
it).
Mike Treseler wrote:
> Robert Sefton wrote:
>
> > I'm curious how other people are avoiding, filtering out, or
> > fighting back against this crap.
>
> The latest version of netscape (and mozilla) has
> a most excellent junk mail router. It does a
> good job right out of the box and you can train it
> further by example rather than by keyword.
>
> -- Mike Treseler
>
> -- mike.treseler@flukenetworks.com
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61160bakito@gmx.ch (bakito) writes: > i'm working on my diploma work right now. i have to develop an fpga - > circuit. the development-environment has to be linux redhat. > > does anyone know fpga-developmenttools to write compile and link fpga > circuit under linux. Quartus II has been available for Linux for quite a while now. SOPC Builder is also available under Linux. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 61161
Ray Andraka <ray@andraka.com> writes:
> 300-400/day isn't that bad. I've been getting that in under 2 hours.
> My ISP has been next to useless on resolving it. I did change to the
> latest paid version of Eudora, which has a spam filter built in. [...]
> It is still not an ideal solution, as I can't go
> off-line without having the mailbox at the ISP overflow within a few
> hours,
I would insist that my ISP do two things:
1) Install SpamAssassin at their end, and configure it to sort the
spam into a separate mailbox.
2) Increase the quota so that the spam doesn't overflow the mailbox.
If your ISP won't do that, you need a better ISP, or to run your own
mail server so that you're not dependent on the whims of the ISP. I use
a box in a colocation facility running Red Hat Linux 9, Qmail, and
Spamassassin. It seems to be very low-maintenance, so it's a net win
as compared to trying to fight an ISP to get things done.
Article: 61162
JHDL is a set of FPGA CAD tools developed at Brigham Young
University's Configurable Computing Laboratory that allows the user to
design the structure and layout of a circuit, debug the circuit in
simulation, netlist and interface for bit-stream synthesis, and so forth. It
is an exploratory attempt to identify the key features and functionality of
good FPGA tools.
http://www.jhdl.org/
From what I gather, it's rather mature, though lacking for the more recent
variants of FPGAs (e.g., Xilinx's Spartan-3).
Oh, by the way, these tools are free for the download. Open source, you
know!
D. Hart...
"Petter Gustad" <newsmailcomp6@gustad.com> wrote in message
news:871xtztlvt.fsf@zener.home.gustad.com...
> bakito@gmx.ch (bakito) writes:
>
> > i'm working on my diploma work right now. i have to develop an fpga -
> > circuit. the development-environment has to be linux redhat.
> >
> > does anyone know fpga-developmenttools to write compile and link fpga
> > circuit under linux.
>
> Quartus II has been available for Linux for quite a while now. SOPC
> Builder is also available under Linux.
>
> Petter
> --
> A: Because it messes up the order in which people normally read text.
> Q: Why is top-posting such a bad thing?
> A: Top-posting.
> Q: What is the most annoying thing on usenet and in e-mail?
Article: 61163Looking for useful books, articles, and development kits for FPGA development, and perhaps some war stories about coming up to speed on these. TIA Regards, Bob MonsenArticle: 61164
How fast do you need to sample the ADCs, and how precise do they need to
be? If simple enough, you could do a delta-sigma ADC with the FPGA,
although you still need an analog comparator. You might be able to bias
an LVDS input to act as the comparator, although I have not tried it. The
rest can be accomplished within an FPGA, although if power or cost are
considerations it may require more FPGA than you are willing to support.
I think a two chip solution, one being an FM receiver chip and the other a
microprocessor may be more appropriate.
Tom Hawkins wrote:
> I need a single chip solution for a control system and DSP
> application.
> The primary consideration is board area. The second, cost.
> Here's what I'm looking for:
> - 5V supply and I/O.
> - Embedded ADC (at least 1, preferably 8). Slow rate (50 Hz).
> - Small FPGA fabric. About the size of a small spartan.
> - Embedded block ram (4 KBytes).
> - Flash FPGA. Would like not to have separate config prom.
> - Low I/O count. I only need about 30 pins.
>
> Does anything like this exist? If 5V I/O is not possible, what's
> needed to translate about 12 pins from 3.3/1.2 to 5V?
>
> Also, what's envolved for FPGA based software defined radio? I'd like
> to build an RC (as in radio control airplane) receiver. Most FM
> radios hop between 2 frequencies to encode pulse widths which in turn
> drive the RC servos. So nothing digital. It just needs to extract
> the pulse train from the FM. I would consider trading an FM receiver
> chip for an external high-speed ADC and a larger FPGA if it buys
> enough flexibility.
>
> Regards,
> Tom
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 61165
Not yet, anyway.
ykagarwal wrote:
> there exists one ultimate natural machine,
> design of which can't even be copied :)
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
Article: 61166On a sunny day (Mon, 29 Sep 2003 09:59:02 -0400) it happened rickman <spamgoeshere4@yahoo.com> wrote in <3F783AA5.21FAAA7D@yahoo.com>: >Let me tell you one downside of having your own domain. Unless you only >use a few addresses, the spammers will make up addresses that don't >exist. If you receive every possible address at that domain, you will >start getting email to all sorts of silly, made up addresses. To >prevent this you will need to either track the made up addresses and >toss them at the server, or you will need to toss everything by default >and just forward the addresses you are using. Also don't plan to keep >using the one address you are forwarding to from domainsbyproxy.com. > >BTW, what is the point of printing cards at all if you have to change >your email address from time to time? Last first, the www.panteltje.com is on the card:-) The email link is on the webpage (transparent for the user) and is changed to a new random one if spam gets in. Then the email at proxy... is filtered so practically anything and everything is shredded. So this fixes 2 problems. 1 my cards are no made and need no change. 2 no more spam seen since the weekend. 3 my emails outgoing have the random address as Reply-To problem solved. Now who did it? :-) Greetings JPArticle: 61167
Hi Rick,
Here are things that I agree completely with you on. "No amount
of simulation will correct a problem if you don't understand what is
going on." and "I can do a few simple calculations to get worst case
numbers for ringing on a 6" trace.". Without first understanding
what's going on, the simulator can be a dangerous thing. Garbage in,
garbage out! I think it's absolutely vital to know what's going on or
how will you be able to sanity check the results the simulator gives?
cheers, Syms.
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F751429.40DB59C3@yahoo.com>...
>
> Ringing is not the cause of crosstalk. Crosstalk is coupling of the
> primary wavefront coupling to adjacent traces due to proximity over
> excessively long lengths. No amount of simulation will correct a problem
> if you don't understand what is going on.
>
>
> I can do a few simple calculations to get worst
> case numbers for ringing on a 6" trace. I don't need to use expensive
> software that does the same calulation with a few extra variables thrown
> in that simply fine tune the calcs.
>
> The other reason that I can't simulate the signals up front is because
> the Spartan 3 in this design will be driving signals to multiple
> daughter boards that are not designed or even planned yet. Obviously
> this will have to be dealt with at the design level when the time
> comes.
>
Article: 61168Hi Guys I know someone of you have helped me in my replies regarding USB Implementation before. I downloaded the USB Core (referred to as the Japanese version). The beauty of this core is that no hardware is required. Just need to connect the D+ and D- of the USB cable to pins of the FPGA. The facts.. I changed the code around so that it has a altera pll running and producing a 48Mhz clock for the usb. I connected some of the output pins to the leds to see what's going on. I uploaded the program and connected the usb cable to the pins and to the PC (and added some circuitry like 3 extra resistors). and Behold, the program on the FPGA actually does something. I know it's working because when i connect/disconnect the usb calbe, the lights on fpga change their pattern for a small amount of time.. However I can't test the actual communication. The reason being, when I connect the usb cable to the PC, the PC recognizes a new USB device is attached (as win2k shows in the system try all the usb devices.), however is unrcognised as VALID drivers are not installed. What I need is some help/tips on how i can install a driver for this product. The fpga has been configured so that it recognises a vendor ID of C91 and product ID of 2001. I have tried playing around with .inf files, but win2k rejects all of them and uses the standard c:\winnt\inf\usb.inf file. I'm so close to getting this thing to work. Pls help/advice RegardsArticle: 61169
"Ian Poole" <ian.poole@doulos.delete-this-bit.com> wrote in message news:bl9ica$hqk$1$8300dec7@news.demon.co.uk... > There is an excellent example of a combinational ones counter in the course > notes on our Comprehensive VHDL course ;-) Check out my employers website > for more details... > > Our example does use a for loop - I'm not sure why you feel a for-loop > cannot be used for combinational logic, unless you are putting wait > statements inside the for loop, and in that case it probably won't > synthesise (unless you have a behavoral compiler). To work out what a loop > will do, simply replicate the contents of the loop once for each iteration > of the loop, replacing the loop parameter with a constant. eg If you think in terms of traditional programming languages, for loop implies iteration, though as you say that isn't required. The PL/I preprocessor, with the %DO statement, would be an example of where it didn't. There are people who would like to use C as a source language for synthesis, which I still don't believe in. Maybe asking for a combinatorial, instead of iterative design, would have been better. -- glenArticle: 61170
Hi Aart- In the Xilinx FPGAs, a LUT RAM block can conveniently be 32x1. You could use three of these, with five identical inputs to provide a look-up sum of five bits. Then, take the results of these sums (five inputs at a time) into an adder tree. For example, if A, B, C, D, E, F are the sets of 5-bits of a 30-bit input, then you'd sum A+B, C+D, E+F. Two more levels and you'd have a complete sum. I'm not sure if this is what the group decided on as the most efficient method, but it's the first one that comes to mind. You could use BRAMs if you'd like for a larger lookup (10-bits at a time to a 4-bit result if you use RAMB4_S4_S4, for example). Jake Aart van Beuzekom <aart@westcontrol.dontspamme.com> wrote in message news:<bl8u9v$1v5$1@news.netpower.no>... > Hi, > > Can anybody tell me a practical way (in VHDL) to count the number of > ones in a bit pattern? Counting should be done with combinatorial logic, > which means that a for-to loop cannot be used here (but being quite new > to FPGA and VHDL, I'm not even sure). The number of bits to be counted > is about 30, so a single look-up table is not the solution, using only a > Spartan II. > > Any suggestions? Purpose is amongst others pattern matching, where I > count how many bits differ from the expected result. > > Thanks, > > AartArticle: 61171
Petter Gustad <newsmailcomp6@gustad.com> wrote in message news:<87n0cot0b8.fsf@zener.home.gustad.com>... > What window library does Xilinx use for ISE under Linux? Are they > using MainWin? If so Xilinx would have to pay a license fee for every > Linux version they sell or give away. If this is the case I would not > expect a Linux Webpack since they would loose money on each download. Yeah, but one would imagine that they would _make back that money when the customer buys chips!_ Isn't that the reason the software exists????? =-aArticle: 61172
On Tue, 30 Sep 2003 10:52:19 +1200, "SneakerNet" <nospam@nospam.org> wrote: >Hi Guys > >I know someone of you have helped me in my replies regarding USB >Implementation before. >I downloaded the USB Core (referred to as the Japanese version). would you please post a url so others can look at it ?Article: 61173
Can you explain a bit more? Are you planning on looking to replace the Celoxica boards with something else, or do you want to mate the Celoxica boards to some optical or wireless transmission system? If so, how would you want to transfer data to/from the optical or wireless interface boards? "Patrick Twomey" <patrickt@rennes.ucc.ie> wrote in message news:1d183274.0309290336.5aa14a7c@posting.google.com... > I am trying to connect two FPGA development boards together. The boards in > question are two Celoxica RC100 development boards. Video in is from an analog > camera. The video data is converted to digital and stored on > SRAM. There is an expansion header for inter-connectivity. On the other board > video out to a monitor occurs after reading data from the SRAM on this board. > Have connected to two boards via a ribbon cable connected to the expansion > headers. Want to replace this cable with wireless or optical transmission. Is > there any development boards available for this. The pixel clock is 10 MHz and > there are at least 16 bits per pixel (32 aftere error correction encoding). > Access to a 80 MHz on board clock is > available. Any help would be much appreciated.Article: 61174
"cb" <charleybrant@hotmail.com> wrote in message news:3f78c417.3131270@news.compuserve.com... > On Tue, 30 Sep 2003 10:52:19 +1200, "SneakerNet" <nospam@nospam.org> > wrote: > > >Hi Guys > > > >I know someone of you have helped me in my replies regarding USB > >Implementation before. > >I downloaded the USB Core (referred to as the Japanese version). > > would you please post a url so others can look at it ? > I didn't post the link as I got the link from this newsgroup so didn't think anyone would need it. Anyway here is the link http://member.nifty.ne.jp/fpga/freeip/usb/ It's in Japenese. Goto Altavista.com and translate it from japense to english. Pls reply back if you get it work. Have fun Regards
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