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Hi! Thanks to the forum for satisfactory replies to my previous queries. I have one other query regarding FPGA configuration. I am planning to use Atmel's ATLV256 EPROM to configure my spartan 2 XC2s150[Its in DIP package so easy to program from my universal programmer]. The RESET/OE(bar) pin of ATLV256 can be programmed to RESET(bar)/OE[i.e. active LO RESET which the spartan 2 requires]. My question is that does the ISE5.1 support this feature to program ATLV256's pin? If not then whats the work around? Regards RiderArticle: 60451
Hi Srikanth, Have a look at the Leon Processor (www.gaisler.com) and leox (www.leox.org), the linux kernal that runs on it. Regards Ben Srikanth Anumalla wrote: > Hi, > > I am quite new in this field. I was wondering if we can run a linux mini > kernel on fpga with full networking support. I went to the site > www.uclinux.org, but could not find any port for fpga. I might be wrong, > may be I could not recognize it. Any info on this is greatly appreciated. > > Thanks > Srikanth >Article: 60452
My university task involves use of reconfigurable logic. I need to automate re-configuration and organize data transfers between PC and FPGA. The netlist to be downloaded into FPGA is described in EDIF file (I can have it as VHDL or Verilog as well). I was recommended to use WebPack and TCL scripting for automatic compilation. However, I want not to restrict my system with the compiler/Xilinx FPGAs. I want my system to be as universal as possible. I want to let user to choose any off-the-shelf FPGA depending on its requirements and financial opportunities. This also means that I want to use existing HW(pci, isa, rs232, etc.) and SW (driver) interfaces. Are there any existing re-configurable industry standards (cards, HW/SW interfaces) I can relay on? An alternative would be to create a level of abstraction from the board.Article: 60453
My system has netlist in EDIF while some of technology elements used in the netlist are described in a separate VHDL file at logic level. WebPack supports only pure EDIF, schematic, Verilog or VHDL design flows. Is ther a way to compile a mixed design? That is, I first elaborate VHDL and then load EDIF netlist which uses VHDL components. May be ISE Foundation supports this?Article: 60454
"Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:<bXf8b.419911$YN5.284114@sccrnsc01>... > "ykagarwal" <yog_aga@yahoo.co.in> wrote in message > news:4d05e2c6.0309112255.3dbc30e4@posting.google.com... > > soar2morrow@yahoo.com (Tom Seim) wrote in message > news:<6c71b322.0309111000.5458aeee@posting.google.com>... > > > Check these IEEE references: > > > > > > Efficient designs of unified 2's complement division and square root > > > algorithm and architecture > > > Sau-Gee Chen; Chieh-Chih Li; > > > TENCON '94. IEEE Region 10's Ninth Annual International Conference. > > > Theme: 'Frontiers of Computer Technology'. Proceedings of 1994 , 22-26 > > > Aug. 1994 > > > Page(s): 943 -947 vol.2 > > > > > > A new pipelined divider with a small lookup table > > > Jong-Chul Jeong; Woong Jeong; Hyun-Jae Woo; Seung-Ho Kwak; Woo-Chan > > > Park; Moon-Key Lee; Tak-don Han; > > > ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on , 6-8 > > > Aug. 2002 > > > Page(s): 33 -36 > > > > > > > > > Efficient semisystolic architectures for finite-field arithmetic > > > Jain, S.K.; Song, L.; Parhi, K.K.; > > > Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , > > > Volume: 6 Issue: 1 , March 1998 > > > Page(s): 101 -113 > > > > thanks for the pointers .. i have found some of them. looking into the > > NR and its variants .. whether it's possible to fit it into some 3000 > slices > > in virtex-ii .. may be i'll have to increase no of iteration per div step > .. > > The 360/91 was built from transistors glued onto ceramic substrates, and > wired together. It did double precision floating point divide in 18 clock > cycles, though. I think it is three clock cycles per iteration, so six > iterations. > > I do wonder how many Virtex devices it would take to implement a 360/91. > > -- glen hello, just curious how much hardware did ur implementation take ? thinking now of 3rd/4th order NR with 14/11 bit lut approximation with unrolled loop (not independent sqr cubing units) .. giving a fully pipelined thing with some tolerable latency don't know whether it will fit.Article: 60455
Hi, Can anyone point me at a vhdl design for a DDC, Digital Down Convertor, in an FPGA. Preferably free. It should be a wideband design with up to 10MHz and as low as 100KHz bandwidth. Resolution of adc is 14bits. Also it should be possible to synthesise it with the Xilinx Webpack. Thanks for any help JanArticle: 60456
I think you need to get ALDEC tools to convert all your schmetics to VHDL. Arnaldo Oliveira wrote: > Hi! > > Is it possible to convert a Xilinx Foundation 3.1i project (including > schematic diagrams) to Xilinx ISE 4.1/5.1/5.2 ? > Thank You > Arnaldo. > >Article: 60457
"Alex Gibson" <alxx@ihug.com.au> wrote in message news:<bjv3de$qh2$1@lust.ihug.co.nz>... > "Tom Hawkins" <tom1@launchbird.com> wrote in message > news:833030c0.0309100656.72bb2da8@posting.google.com... > > I need a single chip solution for a control system and DSP > > application. > > The primary consideration is board area. The second, cost. > > Here's what I'm looking for: > > - 5V supply and I/O. > > - Embedded ADC (at least 1, preferably 8). Slow rate (50 Hz). > > - Small FPGA fabric. About the size of a small spartan. > > - Embedded block ram (4 KBytes). > > - Flash FPGA. Would like not to have separate config prom. > > - Low I/O count. I only need about 30 pins. [***] > looked at the atmel fpslic devices? > big cost is the license after the one in the dev kit runs out(4 months). > > basically an avr + small fpga > > http://www.atmel.com/products/FPSLIC/ > http://www.atmel.com/dyn/products/devices.asp?family id=627 > http://www.atmel.com/dyn/products/tools.asp?family id=627 > http://www.atmel.com/dyn/products/tools card.asp?tool id=2752 FPSLIC seemed like a dream when I first tried to use it, but the tools are really bad (maybe they are a little better now) Atmel claims the pricing starts from 7$ but only the 94K40 devices are available (from digikey 45$) smaller devices digikey pricing is $14 but non stock, and no idea where to get in small quantity and the software licensing is really a killer, I spend 2 weeks troubleshooting the license (involved phone calls to us support) and then it times out all the time. So I dropped FPSLIC at least temporarly from my desk. A Spartan that can hold AVR core and same amount of logic as AT94K40 costs less than AT94K40, so why bother with FPSLIC? anttiArticle: 60458
Antti Lukats wrote: > > "Alex Gibson" <alxx@ihug.com.au> wrote in message news:<bjv3de$qh2$1@lust.ihug.co.nz>... > > "Tom Hawkins" <tom1@launchbird.com> wrote in message > > news:833030c0.0309100656.72bb2da8@posting.google.com... > > > I need a single chip solution for a control system and DSP > > > application. > > > The primary consideration is board area. The second, cost. > > > Here's what I'm looking for: > > > - 5V supply and I/O. > > > - Embedded ADC (at least 1, preferably 8). Slow rate (50 Hz). > > > - Small FPGA fabric. About the size of a small spartan. > > > - Embedded block ram (4 KBytes). > > > - Flash FPGA. Would like not to have separate config prom. > > > - Low I/O count. I only need about 30 pins. > [***] > > looked at the atmel fpslic devices? > > big cost is the license after the one in the dev kit runs out(4 months). > > > > basically an avr + small fpga > > > > http://www.atmel.com/products/FPSLIC/ > > http://www.atmel.com/dyn/products/devices.asp?family id=627 > > http://www.atmel.com/dyn/products/tools.asp?family id=627 > > http://www.atmel.com/dyn/products/tools card.asp?tool id=2752 > > FPSLIC seemed like a dream when I first tried to use it, but > the tools are really bad (maybe they are a little better now) > Atmel claims the pricing starts from 7$ but only the 94K40 devices > are available (from digikey 45$) smaller devices digikey pricing > is $14 but non stock, and no idea where to get in small quantity > > and the software licensing is really a killer, I spend 2 weeks > troubleshooting the license (involved phone calls to us support) > and then it times out all the time. So I dropped FPSLIC at least > temporarly from my desk. > > A Spartan that can hold AVR core and same amount of logic as AT94K40 > costs less than AT94K40, so why bother with FPSLIC? Actually, neither Xilinx nor Atmel make a device that will fit all the requirements since neither provide any mixed signal capability. The Xilinx parts also do not support 5 volt tolerance unless you use a Coolrunner CPLD. The Cypress PSOC is the only device which provides all the required functions, but I don't know if it is 5 volt tolerant or not. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60459
Matt, Thanks for the info. I looked at the Xilinx web site and what they are now calling Foundation is not what they had called Foundation previously. Previously, ISE started and Foundation ended with version 4.x (which used Aldec technology). What they are now calling Foundation is something completely different than what I was refering to. I stand corrected. Marc Matt wrote: > Marc, > > Xilinx has four versions of their ISE software. They are: > > 1) Webpack > 2) BaseX > 3) Foundation > 4) Alliance > > 1 and 2 are subsets of Foundation which has the XST synthesis tool. The > differentiator is that #3 has the full toolset with support for all Xilinx > devices. Numbers 1 and 2 have XST but only support the low to mid range > devices. Alliance is the third party flow which does not include XST. > It should be noted that XST does not support devices based on the 4000 > architecture. i.e. 4000 family, Spartan/Spartan XL. All other families are > supported. If you need support for the 4000 stuff you need to go third > party. > > Hope this helps... > > > Matt > > "Marc Guardiani" <marc@guardiani.com> wrote in message > news:R_u8b.758$U41.369@nwrdny01.gnilink.net... > >>Are you going to be using ISE or Foundation? They are two completely >>different software packages. ISE is very similar to the Webpack (another >>reply you received describes the differences). Foundation is no longer >>supported by Xilinx and is based on third party software. Also >>Foundation will not do the newer FPGAs and ISE will not do the older > > FPGAs. > >>Dave wrote: >> >>>I am just about to go through a 115 page introduction tutorial on the > > XCESS > >>>website for using the Xilinx Webpack 4.x edition. However I will be > > using > >>>the ISE Foundation 4.x edition and want to know if I am wasting my time >>>reading the entire Webpack tutorial to learn how to use the ISE > > Foundation > >>>edition. I am assuming its all the same, with Webpack just having less >>>features. Anyone who is familiar with both editions that can let me know > > to > >>>go ahead with this or STOP - and find a tutorial at Xilinx instead (I > > need > >>>to install the software for their tutes I think) would be much > > appreciated. > >>>Initial stages will be purely schematic entry. VHDL will come later. >>> >>>Regards >>>Dave >>> >>> >> > >Article: 60460
Xilinx what is correct in ISE 5.1 schematics editor the ICAP primitive doesnt show, but if looking at XDL output then ICAP primitive does exist ?! I was very disappointed to see that Spartan 3 doesnt have ICAP (i.e. self reconfig) but it seems it is there? anttiArticle: 60461
shabana_rizvi@yahoo.com (rider) wrote in message news:<ca3a68c8.0309130017.560b304d@posting.google.com>... > Hi! > > Thanks to the forum for satisfactory replies to my previous queries. I > have one other query regarding FPGA configuration. I am planning to > use Atmel's ATLV256 EPROM to configure my spartan 2 XC2s150[Its in DIP > package so easy to program from my universal programmer]. The > RESET/OE(bar) pin of ATLV256 can be programmed to RESET(bar)/OE[i.e. > active LO RESET which the spartan 2 requires]. My question is that > does the ISE5.1 support this feature to program ATLV256's pin? If not > then whats the work around? you can use ise/impact to generate bitstreams and prom files, but no 3rd party config devices are directly supported. you need to use Atmel CPS software to program the ATLV anttiArticle: 60462
Aurelian Lazarut <aurash@xilinx.com> wrote in message news:<3F61E0FA.3164C1F1@xilinx.com>... > Antti, > > XPS is using Impact (in batch mode) but if you are having trouble with XPS > let me know so I can help you > Cheers, > Aurash I use everyday 4 different xilinx boards and 3 different cables. there are problems all around. I know XPS uses impact, but when XPS doesnt download impact still may. if impact doesnt download then ChipScope will. as example download to ML300 using Xilinx cable IV has failure rate 80% with impact and work all OK with Chipscope. I just have lost trust, so I am trying to use whatever works, changing cables and software until something works. and then use the know good combination of cable and software. what makes me real sad is that there is no way todo boundary scan with xilinx Parallel cable IV - the last board I designed I needed todo boundary scan (to verify the board) and could not do it as Cable IV is the only one (from those I have) that works with that board. anttiArticle: 60463
"Valentin Tihomirov" <valentin@abelectron.com> wrote in message news:<3f631f00$1_1@news.estpak.ee>... > My university task involves use of reconfigurable logic. I need to automate > re-configuration > and organize data transfers between PC and FPGA. The netlist to be > downloaded into FPGA is described in EDIF file (I can have it as VHDL or > Verilog as well). I was recommended to use WebPack and TCL scripting for > automatic compilation. However, I want not to restrict my system with the > compiler/Xilinx FPGAs. I want my system to be as universal as possible. > > I want to let user to choose any off-the-shelf FPGA depending on its > requirements and financial opportunities. This also means that I want to use > existing HW(pci, isa, rs232, etc.) and SW (driver) interfaces. Are there any > existing re-configurable industry standards (cards, HW/SW interfaces) I can > relay on? An alternative would be to create a level of abstraction from the > board. no cross-vendor standards. most (but not all) vendors provide some shell /scripting for automation. anttiArticle: 60464
I am looking for a (open source?) VHDL model for one of the following Atmel dataflash memory chips: AT45DB161B AT45DB321B AT45DB642B Thanks in Advance, ScottArticle: 60465
> OK, How 'bout SuSE 8? Or better yet, SLES8 for AMD64? I don't know, but I guess any glibc-2.3-based distribution would need a similar trick. I wouldn't mind having one of the latter boxes :-). Incidentally, there's a problem with using LD_LIBRARY_PATH: Xilinx unaccountably includes a libstdc++ in their library directory---this will cause apps to use it rather than the system library if they search it first. This interferes with, among other things, Icarus Verilog. So best to either prepend the system library directories to LD_LIBRARY_PATH, or add the Xilinx library directory to /etc/ld.so.conf (I believe ld.so/ldconfig will keep the order). Cheers, Peter MontaArticle: 60466
Hi Folks I have a maintenance need to recover a compilable source fronm the jedec fusemap file for a lattice ispmach96/48 device. Can anyone suggest a tool for the job.. or am I to resort to a dumb manual method? Thanks -- John jwb@rosery.netArticle: 60467
Srikanth Anumalla wrote: > Hi, > > I am quite new in this field. I was wondering if we can run a linux mini > kernel on fpga with full networking support. I went to the site > www.uclinux.org, but could not find any port for fpga. I might be wrong, > may be I could not recognize it. Any info on this is greatly appreciated. > Xilinx Microblaze and ucLinux http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/ /RogerL -- Roger Larsson Skellefteċ SwedenArticle: 60468
jed2abl - get it from xilinx free Andrew jb wrote: >Hi Folks > >I have a maintenance need to recover a compilable source fronm the jedec >fusemap file for a lattice ispmach96/48 device. > >Can anyone suggest a tool for the job.. or am I to resort to a dumb >manual method? > >Thanks > > > >Article: 60469
There is a free DDC Xilinx core that comes with the ISE tools (not sure about Webpack). It is not a VHDL design though... /Mikhail "Jan" <jan_marijnisse@hotmail.com> wrote in message news:bjvdln$nsb$1@news3.tilbu1.nb.home.nl... > Hi, > > Can anyone point me at a vhdl design for a DDC, Digital Down Convertor, > in an FPGA. Preferably free. > It should be a wideband design with up to 10MHz and as low as 100KHz > bandwidth. Resolution of adc is 14bits. > Also it should be possible to synthesise it with the Xilinx Webpack. > > Thanks for any help > > Jan > >Article: 60470
In message <3mP8b.824$TJ.103957@news.uswest.net>
Andrew Paule <lsboogy@qwest.net> wrote:
Hi
> jed2abl - get it from xilinx free
any chance of a URL.. its not obvious on th xilinx site..
Thanks
John
>
> Andrew
>
> jb wrote:
>
> >Hi Folks
> >
> >I have a maintenance need to recover a compilable source fronm the jedec
> >fusemap file for a lattice ispmach96/48 device.
> >
> >Can anyone suggest a tool for the job.. or am I to resort to a dumb
> >manual method?
> >
> >Thanks
> >
> >
> >
> >
>
--
John Ballance
jwb@rosery.net
Article: 60471rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F63658E.A7BEFFF8@yahoo.com>... > Antti Lukats wrote: > > > The Cypress PSOC is the only device which provides all the required > functions, but I don't know if it is 5 volt tolerant or not. > Rick "rickman" Collins PSoC does not have real configurable logic, it has digital and analog blocks and some configuration, but you can not create any custom logic, only selected from exisiting configurations. So there is no PLD on chip, only some reconfig bits. PSoC was first marketed as having programmable logic onchip, but actually it isnt there. anttiArticle: 60472
Hello, I am implementing a 128 point real Radix-2 fft, data and coefficient widths are 16 bit. I am synthezising it for use in an FPGA. However, it is taking a very long time to synthesize. (approx 3 days using Leonardo on a 2 GHz machine with 512 MByte RAM) I am using a 20K1000 Altera FPGA. The ram required by the fft will be internal to the FPGA Will this design take up all the space on the device. From past experience, can someone give me an indication of what area of the device the fft will occupy. Surely if it takes up most of the device, then it will be too big, as I have other features to implement in the FPGA also !! Thank you PJArticle: 60473
I just did a little experiment with the webpack software, instantiating a fifo in the block ram.... and the software black boxes it because it doesn't know how to hook it up. The .edn file from the core generator is missing, and as such XST does not know how to configure the block ram. This is consistent with information I received from the Xilinx Apps guy. /\/\/\/ Sorry for my confusion on Webpack vs. Foundation. Clyde Nial Stewart wrote: > Clyde R. Shappee <clydes@the_world.com> wrote in message > news:3F6118EE.96AB3E46@the_world.com... > > I have used Webpack 4.2 something and I believe the ISE foundation of > about the > > same edition. > > > > I have found that they are essentially identical, with the following > > differences: > > > > Webpack does not have the core generator. You cannot use the block rams > and > > other on chip resources. > > That's not true Clyde, you've just got to know what they're called > and instantiate them directly. > > See the Picoblaze and 'VirtexII picoblaze (more instruction memory) > on a SpartanII' projects on the Downloads page of my web site below. > > Both done with web-pack and both instantiate blockrams. > > Nial Stewart > > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > www.nialstewartdevelopments.co.ukArticle: 60474
>The returning 3.3V wave wants to pull the pin to 6.6 V, but the >transmission line impedanec is roughly 50 Ohm, and the chip pull-up >impedance is roughly 10 Ohm, so you have a voltage divider that raises >the output pin voltage by only 1/6 of the 3.3 V swing = 550 mV. The >resulting theoretical 3.85 voltage is really a bit lower since the >reflection is not perfect, and there are losses on the line. >Also, this spike will only last a few nanoseconds. >I would say that this poses no problem. But I have copied Steve Knapp, >who handles Spartan applications. He may add his opinion to this. There is nothing special about Spartan or FPGAs in this area. Right? Is there a general rule in output pad design that the pad must be rugged enough so that it can't shoot itself in the foot with its own reflections? (I don't remember seeing any warnings about this in data sheets.) What about busses, like PCI, where the driver might be in the middle so the effective line impedance is half of the nominal 50 ohms. (Can it get even lower than that due to capicative loading?) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
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Compare FPGA features and resources
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