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rickman wrote: > John Williams wrote: > >>Hi Rick, >> >>rickman wrote: >> >>>Looks like I have not done my homework on this. I had done some >>>research on modular configuration which was what I required. The >>>Spartan lines seem to be supported for this although they don't yet list >>>the Spartan3 chips. But I was under the impression that partial >>>configuration was the down load technique to support this in the >>>devices. I see that only Virtex and Virtex-II are supported by partial >>>configuration. This is not good. >> >>Don't panic! the S3 still supports partial reconfiguration - the ICAP >>primitive that Antti and I were talking about is a block that allows the >>partial reconfigruration to be controlled from within the device itself >>ie. self-reconfiguration. >> >>All the Virtex's and S3 can be partially reconfigured from *outside* the >>device, via SelectMap or slave serial or whatever, either partial or >>total reconfiguration. >> >> >>>So why the disconnect on partial configuration Xilinx? Why not support >>>Spartan-3 devices? >> >>As I said, it's just the ICAP (internal configuration access port), not >>the partial reconfig capability itself. >> >>Regards, >> >>John > > > I am still in panic mode. I started digging and found that the Spartan > 3 devices are not suitable for modular configuration. Seems the tbuf is > one of the features in the V2 devices that has been taken out for > "optimization" in the S3. The tbuf is required for signals that > traverse modules. Given your observation, plus the info provided by Steve Knapp from Xilinx in an earlier post (cell behaviour during partial reconfig) it seems that partial reconfig in S3 devices is not encouraged. > I have exchanged a couple of emails with Xilinx on this and am waiting > for the final word. But it is looking like the Sparan 3 devices will > not be able to do what I need in any defined timeframe. So it seems. Regards, JohnArticle: 60526
Has anyone tried 6.1i yet? I took a Spartan IIE design and compiled it under 6.1i (from 5.2i, previously). It failed timing by about 20% where it previously passed. Anyone have similar "luck" ? JakeArticle: 60527
Ray Andraka wrote: > > Peter, > > My understanding was that those pictures were of Xilinx parts. Can Philip Freidin clarify these photos ? ie devices (date codes & process?) under test, and clock / data conditions to stimulate the failures, and appx failure rates observed ? -jg >From Philip's excellent FAQ: > The test systems that I have designed are quite different. These > test systems only collect trajectory data when the flip flop > goes metastable, and they sample the DUT output at 1GSamples per > second, thus taking a sample every nanosecond. The result is > that the scope pictures I have show the actual trajectory of > the metastable. > > For your viewing pleasure, I have put them up on the web: > > www.fpga-faq.com/Images/meta_pic_1.jpg > www.fpga-faq.com/Images/meta_pic_2.jpg > www.fpga-faq.com/Images/meta_pic_3.jpg > > These are far from just delayed outputs! The end result though > is still the same, systems that fail. But seeing these scope > pictures of the actual Q output might make you think about how > you measure metastability. > Of course if > you sample them at a low enough rate, it looks like an unpredictable delay > even if it is not. > > Peter Alfke wrote: > > > I have a lot of respect for Phil, we are personal friends and have > > worked together for over 20 years. I think he used old TTL pictures.Article: 60528
>In devices like V2Pro and S3, the maximum allowed voltages >(both positive and negative) on the I/O pins form a smaller >window than in some previous families. ... Is that window just smaller in terms of volts, or is it smaller in terms of percent? Why wasn't this a problem several years ago? Consider a 5V IOB or junk CMOS logic. It would get pulsed to 10 V from nasty reflections if the clamp diodes didn't do their thing. Clearly that's way above the max ratings. So we have been operating out-of-spec for a long time. Has technology in this area changed in the past few years? Have I missed similar discussions in other areas? (That would be easy.) Is there something about the way transistors scale that I don't know about? (yet) Are fab lines cutting things closer now? ... -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 60529
>I see why metastability can't be detected or corrected within the >digital domain, but I still don't quite understand why metasability >can't be detected in the ANALOG domain and then corrected after a >FIXED (rather than exponentially decaying probability) time-window >after the clock cycle to be forced into one of the stable states. [Apologies if everybody was hoping this horse was dead.] Suppose you have an analog detector. It's output is 0, 1, or maybe when in transition. How do you turn that into a clean digital signal? Doing that is the same as solving the metastability problem. A digital logic gate when operating near threshold is roughly linear. It's trying to decide if the input is above or below the threshold. A gate is really an analog circuit if you look hard enough, just saturated most of the time. But the times we are interested in are when it's not saturated. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 60530
Hi all!
I have a query regarding Xilinx FPGAs and the XST. In many documents
relating FPGA designs, there are such statements as:
BUFG instance_name (.O (user_O),
.I (user_I));
My question is that do we really need to instantiate BUFG, IBUFG etc
in this manner? Isn't this automatically done by the tool(XST etc)?
Lets say i am using a clk signal in my design. I LOC this clk signal
to one of FPGAs IGCLK pad. Wont' the IBUFG primitive be used
automatically? Similarly, does the tool not automatically insert IBUF
and OBUF at the input/output signals?
Thanks
Article: 60531"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:qoocmv4dr277d3hu3tem6qbik3ap5ju1g7@4ax.com... > Hi, > > Does anyone know what to do with the pin on V2P called "RSVD"? > > I guess I'm meant to leave it open, but I haven't found anything in > the datasheet or the Xilinx answers database that says for sure. > > TIA, > Allan. Allan, In several designs that I've done it's been left open, and all is well. In fact, on the schematic symbols I've created I've added the note "DO NOT CONNECT" next to the pin. I can't recall where I got that information. BobArticle: 60532
Duane Clark wrote: > rickman wrote: > >> ... >> If you need info on changing your hard drive serial number, there is a >> program available for that (as long as you are running a FAT drive and >> not NTFS)... > > > VolumeID: > http://www.sysinternals.com/ntw2k/source/misc.shtml > WOW, thanks Rick and Duane! Together, you've given me all the things to fix this! I didn't know how to change the volid on an NTFS disk. This fixed it, and the license seems to be working! (Now, i just have to beat my vhdl file into shape so FPGA express likes it!) Thanks again, JonArticle: 60533
jakespambox@yahoo.com (Jake Janovetz) wrote in message news:<d6ad3144.0309151854.54e599c2@posting.google.com>... > Has anyone tried 6.1i yet? I took a Spartan IIE design and compiled > it under 6.1i (from 5.2i, previously). It failed timing by about 20% > where it previously passed. > > Anyone have similar "luck" ? > > Jake where did you get 6.1i ? dont see it been released on xilinx website? anttiArticle: 60534
"Kenneth Land" <kland1@neuralog1.com> wrote in message news:<vmcl99c2s5jgc0@news.supernews.com>... > Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com? > > I looked very closely at the 1.1 version and found it took only 6 pins and > $1.75 transceiver chip. > > Ken there is a japanese design (VHDL, and Visual basic host example) that uses no tranceiver at all, ie USB DM,DP directly to FPGa anttiArticle: 60535
I wrote some constrains (indicating simply the side where I want the
signals). I want the tools to use these constrains in place-and-route
phase, and then I want to back-annotate the pin assignmet in the
constrain file (to lock pin locations for the future change).
Unfortunately "Back-annotate pin location" exit with this error:
ERROR:Pin2Ucf - pin2ucf found that the UCF file for this design
already have
some pin locking constraints. Since pin2ucf will not overwrite
user
constraints, please check the UCF file and remove those
constraints before
trying pin2ucf again. You could also delete the UCF file before
trying
again. To get a listing of all possible conflicts among
constraints for
this design please check the pin2ucf report file: filename.lck
constrain file is simple:
NET "addr_bus<0>" LOC = "B" ;
NET "addr_bus<1>" LOC = "B" ;
NET "addr_bus<2>" LOC = "B" ;
NET "addr_bus<3>" LOC = "B" ;
NET "addr_bus<4>" LOC = "B" ;
NET "addr_bus<5>" LOC = "B" ;
NET "addr_bus<6>" LOC = "B" ;
NET "addr_bus<7>" LOC = "B" ;
NET "data_bus<0>" LOC = "B" ;
NET "data_bus<1>" LOC = "B" ;
NET "data_bus<2>" LOC = "B" ;
NET "data_bus<3>" LOC = "B" ;
.........
I tried with or without PINLOCK section but the result is the same.
in the report there is:
Pin name conflicts on the nets
-----------------------------------------------------------------
NET Name New PIN Old PIN
-----------------------------------------------------------------
addr_bus<0> N7 B
addr_bus<1> P8 B
...................
I also tried to delete the constrain file (or delete its contents)
after first pass, but in this case it restart from place-route and
discard all previously allocated pin.
any idea?
thanks
Article: 60536Had you regenerate the ucf file with PACE? I regenerate copletely this file and the time constrain return to the original (5.2 version) Bye Giuseppe "Jake Janovetz" <jakespambox@yahoo.com> ha scritto nel messaggio news:d6ad3144.0309151854.54e599c2@posting.google.com... > Has anyone tried 6.1i yet? I took a Spartan IIE design and compiled > it under 6.1i (from 5.2i, previously). It failed timing by about 20% > where it previously passed. > > Anyone have similar "luck" ? > > JakeArticle: 60537
Also this morning I saw that there is the first service pack available to the web for 6.1 version Bye Giuseppe "Giuseppe³" <miaooaim@inwind.it> ha scritto nel messaggio news:bk6kph$qb16m$1@ID-61213.news.uni-berlin.de... > Had you regenerate the ucf file with PACE? > I regenerate copletely this file and the time constrain return to the > original (5.2 version) > > Bye > Giuseppe > > "Jake Janovetz" <jakespambox@yahoo.com> ha scritto nel messaggio > news:d6ad3144.0309151854.54e599c2@posting.google.com... > > Has anyone tried 6.1i yet? I took a Spartan IIE design and compiled > > it under 6.1i (from 5.2i, previously). It failed timing by about 20% > > where it previously passed. > > > > Anyone have similar "luck" ? > > > > Jake > >Article: 60538
I have a homebuilt Byteblaster MV which works fine with Altera Max+PlusII 10.2. With Quartus II 3.0 SP1 "Auto Detect" of the devices in the JTAG chain works, but when I try to program it reports Info: Configuring device index 2 Error: Can't configure device. Expected JTAG ID code 0x110500DD for device 2, but found JTAG ID code 0x00000000. Error: Unexpected error in JTAG server -- error code 44 Error: Unexpected error in JTAG server -- error code 34 Error: Operation failed With an original Altera ByteBlasterII I have the same problem. Does anybody know this problem? ChristianArticle: 60539
Hi all, I'm trying to design a Microblaze system which uses an external SRAM as instruction memory. I'm using the V2MB1000 board from Insight Memec with P160 Communication module. The SRAM is conected to Microblaze through an external memory controller conected to the Instruction side OPB bus. The thing is that I don't know how to save my "executable.elf" file to the external SRAM. I've seen other microprocessors that firstly they copy the program from flash or another Read Only storage device to a faster memory, such as SRAM. They use a boot program, stored in FLASH, to do this. But in my system I don't know neither how to save it to the FLASH because my program is too large and it can't be stored in the Block RAMs. I'll very grateful if someone could help me. Thanks a lot. Arkaitz.Article: 60540
Hi Arkaitz, You can always download the executable to the external memory from the host using the xmd tool. Göran Arkaitz wrote: > Hi all, > > I'm trying to design a Microblaze system which uses an external SRAM > as instruction memory. I'm using the V2MB1000 board from Insight Memec > with P160 Communication module. > > The SRAM is conected to Microblaze through an external memory > controller conected to the Instruction side OPB bus. > The thing is that I don't know how to save my "executable.elf" file to > the external SRAM. > I've seen other microprocessors that firstly they copy the program > from flash or another Read Only storage device to a faster memory, > such as SRAM. They use a boot program, stored in FLASH, to do this. > > But in my system I don't know neither how to save it to the FLASH > because my program is too large and it can't be stored in the Block > RAMs. > > I'll very grateful if someone could help me. > > Thanks a lot. > > Arkaitz.Article: 60541
> > The other thing is that if *any* logic changes it has to re-run the > fitter, which at least for my designs is 60% of the compile time. > Well, I guess a few wires change is also "any logic changes". poor me ...Article: 60542
> "Smart Compilation" just means save the cache files > in case they can be reused. It doesn't make the cache > any more likely to be reusable. That is a function > of device utilization, routing strategy and the > impact of the design change. > Now it looks like that's really the case here. I was mistaken and thought it is something like Design Compiler's incremental compile or ECO changes of final layout. I should have realized that for the prize that I paid for the board + software, it is too good to be true. :-) > > -- Maybe "didn't work" means > "routed successfully, but did not function correctly" It is different from in asic design that I changed 8 pads without running any simulations, I could mis-connect those pads. Here is FPGA you just "assign" the output signals to different pins using "assignment editor". How can it be "not function correctly" is beyond me.Article: 60543
> Doesn't look good. What version of Quartus are you running? 2.2 or 3.0? Did > you later retry using a normal compile, and did that work? > Ben, I used Quartus II 2.2, then a few weeks ago I upgraded it 3.0. I still have the same problem. YiArticle: 60544
Hi, I'm looking for a way to get a report on failing paths, one pr endpoint, from timing analyzer. The timing analyzer reports number of errors, and the documentation states that this is the number of end-points failing in the analysis (not dependent on the number of paths to these endpoints). But when specifying that I want to se this number of error messages I'm only getting a few end-points, but several paths to that end-point. I want to see all the endpoints and one (or a specified number of) paths to these failing endpoints. Any suggestions? --JosteinArticle: 60545
Hi all! I'd like to buy an FPGA prototyping board and, after some searches, I am oriented to the Digilent Digilab 2. They sell directly, but I live in Italy, and I am a little scared about customs and shipping fees. Is there anybody out there living in Europe that has bought a board from Digilent? How much did you pay for shipping and customs charges? Many thanks! Sergio TassinariArticle: 60546
Sergio Tassinari wrote: > Hi all! > I'd like to buy an FPGA prototyping board and, > after some searches, I am oriented to the Digilent Digilab 2. > They sell directly, but I live in Italy, and I am a little > scared about customs and shipping fees. > > Is there anybody out there living in Europe that has bought > a board from Digilent? > How much did you pay for shipping and customs charges? > > Many thanks! > > Sergio Tassinari > > > Hello Sergio, I live in Belgium, and I recently ordered a combination of the D2E and the DIO2 board, it has arrived yesterday. Here in Belgium it was only regular taxes and administration costs of the customs that came on top of the price given by digilent. So the 210$ (order + shipping) was 196Euro, and on top of that came a 52Euro fee. (Regular taxes in Belgium are 21%, I don't know how much it is in Italy though). Good luck. YvesArticle: 60547
> Hi Yi, > > The smart recompile feature in Quartus skips only entire steps in the > compilation process that aren't needed. So if you move pins, it knows > that your design does not need to be re-synthesized & mapped, but it > does need to be re-placed and routed (fit). So you still wind up > paying the CPU time for a full place and route, even though you moved > only a few pins. > Vaughn, Thank you very much for your detailed explaination! I really appreciate it!! I kind of realized that "need to be re-placed and fitted" even I move a few pins before too. But I did notice in this case, the synthesis is also repeated, takes about 15 minutes on an AMD 1700+ machine with 1G memory. > To speed things up, you can back-annotate your design to LABs before > you recompile. Back-annotate, move the pins you want to move, and > recompile. It will now be a lot faster, since your logic is locked > down, so placement is trivial. It will still need to be routed and > timing analyzed though, but it should still be 3x or so faster to > compile. > I will try this and hope it works. Thanks! > > Now for your second issue: why did your design not work after a smart > recompile? I can think of two possibilities: > > 1. There is some dangerous timing in your design (race conditions, > asynchronous transfers without handshaking, transfers between clock > domains without timing constraints, etc.). By re-placing and routing > your design, a race condition that was latent may have become a > problem. Yes, you are right. The clocking is kind of messy in my design, lots of clock gating and other manipulations. So, I can accept it if the compiled design never worked, that may even make me feel better: I really shouldn't do those nasty things on clock. If I change any logics around cross-clock domain region, clock generator (not pll), clock pll or even an inverter anywhere, I can probably accept the fact that re-placing and fitting kill the design. However, failing after moving a few output pins, which have no timing constraints at all, is hard to understand. YiArticle: 60548
Is it free? :) That is very interesting and that is what I went looking for. I imagined the logic in the FPGA would wiggle D+ and D- appropriately. I understand that the 480Mbps of 2.0 might be tough in a garden variety FPGA, but 1.1 might be doable. I wonder if the special LVDS pins of a Cyclone or Stratix would do 2.0? Of course going to Stratix would negate any BOM savings. Ken "Antti Lukats" <antti@case2000.com> wrote in message news:80a3aea5.0309152348.5ffd5049@posting.google.com... > "Kenneth Land" <kland1@neuralog1.com> wrote in message news:<vmcl99c2s5jgc0@news.supernews.com>... > > Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com? > > > > I looked very closely at the 1.1 version and found it took only 6 pins and > > $1.75 transceiver chip. > > > > Ken > > there is a japanese design (VHDL, and Visual basic host example) > that uses no tranceiver at all, ie USB DM,DP directly to FPGa > > anttiArticle: 60549
480 MHz LVDS IO is not out of question on Xilinx FPGAs (Altera ? don't know) in terms of frequency; what I question is the voltage/current levels to/from the USB, have to dig into the USB spec to figure this one out. Any pointers to this japanese design or its documentation? --- jakab "Ken Land" <kland1@neuralog1.com> wrote in message news:vme5iv66sv911@news.supernews.com... > Is it free? :) > > That is very interesting and that is what I went looking for. I imagined > the logic in the FPGA would wiggle D+ and D- appropriately. I understand > that the 480Mbps of 2.0 might be tough in a garden variety FPGA, but 1.1 > might be doable. > > I wonder if the special LVDS pins of a Cyclone or Stratix would do 2.0? Of > course going to Stratix would negate any BOM savings. > > Ken > > "Antti Lukats" <antti@case2000.com> wrote in message > news:80a3aea5.0309152348.5ffd5049@posting.google.com... > > "Kenneth Land" <kland1@neuralog1.com> wrote in message > news:<vmcl99c2s5jgc0@news.supernews.com>... > > > Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com? > > > > > > I looked very closely at the 1.1 version and found it took only 6 pins > and > > > $1.75 transceiver chip. > > > > > > Ken > > > > there is a japanese design (VHDL, and Visual basic host example) > > that uses no tranceiver at all, ie USB DM,DP directly to FPGa > > > > antti > >
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