Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
> Hi Yi, > > When you change anything in your design, and you haven't > back-annotated, and aren't using incremental fitting, nothing stops > the compiler from changing the placement and routing a lot. In > general the placement and routing will change a lot, but will still > achieve similar speed and routability -- that's all that matters. > Hi, Vaughn, I totally agree with what you said above. I am just a little frustrated when I simply bring one internal node (memory lock indicator, quite static signal) to one LED on board, without changing anything else, the compilation result changed from "no timing violation" to "300,000 timing violations" and the longest datapath increase from 180ns to 210ns. One friend suggested to me to increase the clock-to-output time for all the 5MHz output bus to 200ns (otherwise, Quartus will automatically use the 40MHz input clock to calculate the tco for the 5MHz output signal). That worked 80% of the time. Anyway, there seems just too many unrelated issues that can affect the compilation result. ...... waiting for Quartus II 4.0 .... :-) YiArticle: 60701
John,
Thanks. That was the kind of answer I was anticipating. However, the
other ideas have given me some potentially better solutions to consider.
Thanks to everyone who provided an input. As Peter said, "There seem to be
many different ( very different) ways to solve the
digital portion of your design..."
Theron Hicks
"John_H" <johnhandwork@mail.com> wrote in message
news:BhHab.16$Kq4.10256@news-west.eli.net...
> 16 cycles of compare/subtract can go pretty darned fast! You can do it
> compact in a single stage with a shift register for the result (16 bit
> suptractor, 16 bit registered mux). 16 clock cycles at 6ns per clock
cycle
> is very achievable. If you want to throw resources at it, you could do a
> simple combinatorial divide. I got 81ns in the tiny Spartan-3 with a
first
> rough-cut, no attempts to make it fast.
>
> "Theron Hicks (Terry)" <hicksthe@egr.msu.edu> wrote in message
> news:3F6A4BF2.6D4F21A@egr.msu.edu...
> > Sorry Ray,
> > I meant to give a little more detail than I ended up with. The
number
> of
> > clock cycles per divide is not critical. I cannot accept any pipeline
> delay, but
> > I am willing to wait a few clock cycles before I get a final result. I
> basically
> > need to get a divide-by result as quickly as possible. The inputs are 2
> 16 bit
> > numbers and I need a minimum of 14 bits in the result. I would really
> like to get
> > to 16 bits if possible. The resultant resistance (the quotient) is
> subtracted
> > from the desired resistance. This difference serves as the input to a
> very fast
> > PID controller. This controller serves to control the temperature of a
> hot-wire
> > sensor in a research grade hot-wire anemometer. Based on that, the
> time delay
> > between requesting a quotient and the time when that quotient is valid
> needs to be
> > minimum. The 16 bit A/D currently has a latency of 460ns. The
remainder
> of the
> > PID control loop should take about 30ns. I want the division to be
> substantially
> > faster than the sum of those two times if possible. As a maximum, it
must
> be
> > faster that 500ns. If it were much faster (~100ns) then I could look at
> faster
> > A/D converters for an even higher system throughput when desired. I
hope
> this
> > clarifies things.
> >
> > Thanks,
> > Theron
> >
> > Ray Andraka wrote:
> >
> > > You need to decide what your requirements are:
> > > size, precision, accuracy, number of clocks per sample and clock
rate.
> > > You aren't going to get all of them at once, however if you can
> compromise on
> > > accuracy, a normalize -> look up -> denormalize might be the best
> approach.
> > >
> > > Theron Hicks wrote:
> > >
> > > > Hello,
> > > > I have a project in mind where I would like to caclculate the
> resistance
> > > > of a sensor. Because of the remainder of the circuit configuration,
> this
> > > > must be done using a voltage divider. If I implement this in a
> spartan3,
> > > > what is the fastest I can do a 16bit divide (unsigned) Obviously I
> can do a
> > > > shift and subtract, but I would prefer something a little faster.
Any
> > > > suggestions? (I know I could go to a fast DSP but again, I would
> prefer to
> > > > stick with what I am most comfortable with (FPGAs). My intent is to
> use the
> > > > smallest spartan3 if posible.
> > > > Thanks,
> > > > Theron Hicks
> > >
> > > --
> > > --Ray Andraka, P.E.
> > > President, the Andraka Consulting Group, Inc.
> > > 401/884-7930 Fax 401/884-7950
> > > email ray@andraka.com
> > > http://www.andraka.com
> > >
> > > "They that give up essential liberty to obtain a little
> > > temporary safety deserve neither liberty nor safety."
> > > -Benjamin Franklin, 1759
> >
>
>
Article: 60702
The equation for utilization is very complex. For arithmetic data path however,
I do find
that the Xilinx structure permits a higher density measured in LUTs occupied
when comparing designs
for the same algorithm but optimized for the particular device. This is due
partially
to the fact that the Altera carry chain breaks the LUTs into a pair of 3 LUTs so
your arithmetic is
2 input arithmetic where Xilinx's is 4 input arithmetic. Granted, Altera has
greatly improved the situation
by adding dedicated gating for doing an adder-subtracter in one level, as well
as logic to permit an
accumulator with load, which are probably the most common use of more than two
input arithmetic.
To be fair, the average user is not going to fully use the Xilinx capability
because the synthesis tools
do not do a great job at inferring more complex structures such as an add/mux or
mux/add etc. In order
to use that, you more or less need to do some very careful coding. Same is true
for taking advantage of
the SRL16s.
The fact of the matter is, I think both vendor's numbers are slanted. Unless
you do the design with the
specific architecture in mind, you are not going to get optimum utilization of
that array. A design that is
optimized for one array is going to generally be a poor fit for another.
Presumably, both vendors have
taken a design or designs that were targetted to their parts, and then ported
those designs to the competition
to come up with these numbers. In both cases, naturally, their device is going
to show superior results
simply because the design database they are drawing upon was optimized to their
parts.
As I've stated many times before, the comparison metric should be a raw count of
the number of 4 LUT/flip-flop
pairs plus a list of additional features with perhaps an equivalent utilization
of that feature if it were not available.
That way, the designer can make an informed decision based on what features he
thinks he will use. In cases
where he doesn't know, the most accurate comparision would be to ignore the
effect of special features altogether,
then accept the gains he gets by using them as gravy.
Paul Leventis wrote:
> I might as well give the Altera view -- 12.5% is a gross overstatement of
> the relative abilities of a Virtex LC vs. a Stratix LE. Our data suggests
> that nearly the reverse is true (about a 9% advantage for Stratix). Please
> see the following whitepaper for our reasoning and data. As you can see
> from Figure 1, your mileage will vary -- depending on your design, you could
> see vast density advantages from one architecture or the other.
>
> http://www.altera.com/literature/wp/wp_stx_logic_efficiency.pdf
>
> If we wanted to, we could start counting our M512 blocks as logic, as they
> can be used for shift-registers, small memories, and soft multipliers, but
> we don't bother.
>
> Bottom line -- you really need to compile *your* design to both Stratix and
> Virtex (or whatever families you are interested in) before you will really
> know what the story is density. Averages don't matter much to you if yours
> is that design that gets hosed in one architecture or the other!
>
> Regards,
>
> Paul Leventis
> Altera Corp.
>
> "Peter Alfke" <peter@xilinx.com> wrote in message
> news:3F69D605.63B715DB@xilinx.com...
> > Rick, I will not defend the +12,5%, but I can explain it:
> >
> > It is the price we all pay for the intense and sometimes ruthless
> > competition in this market. Without a bloodthirsty competitor "in our
> > rear-view mirror", we would be gentlemanlike and give you conservative
> > numbers. But the way it is, our marketing folks think it would throw
> > away some really (really!) powerful features if they are not somehow
> > represented in the numbers. Each Xilinx Logic Cell does more than an
> > Altera LE, there can be no doubt about that.
> >
> > This is not an excuse (personally I agree with you), but an explanation.
> >
> > Peter Alfke
> > ==========================
> >
> > rickman wrote:
> > I care about the fact that I have to ignore a
> > > column of data in a data sheet as marketing hype and use a calculator to
> > > get the *real* numbers. Clearly the marketing people don't think we can
> > > add and multiply ourselves.
> > >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60703Hi Eva, You can use AN221E04 from Anandigm. AN221E04 is a FPAA (Field Programmable Analog Arrays). Visit www.anadigm.com to know more. For delta-sigma modulator in digital domain,you may use a Xilinx FPGA--- Virtex-II family device. You get a nice programmable system.A convergence of Analog and Digital programmabilty. Regards, SANKET. Eva Lau <eva_lau@yahoo.com> wrote in message news:<3F6AE6D4.2020500@yahoo.com>... > Hi! > I'm a student and doing a project to construct an Oversampling > Delta-Sigma DAC. I planned to build the system using Cadence, Verilog > HDL and FPGA which are totally new to me, I don't know whether the FPGA > can be programmed to build functions like oversampling and > interpolation, or should I make that part by other electronic components > and connect to the FPGA containing the delta-sigma modulator only? > Hope someone can answer my question. Thanks in advance! > > Best Regards, > EvaArticle: 60704
So much so, that they stripped out half of the SRL16's and LUTRAMs in the
SpartanIII. In all fairness, that was because customers aren't using them to the
full advantage. The not using them is partially an education problem (Xilinx has
not done all that much to tout the SRL16), partly a synth tools problem (they don't
infer them except in the most obvious brain dead cases), and partly due to a
generic code mindset propagated by the EDA community.
Peter Alfke wrote:
> ... Xilinx is very proud of its LUTRAMs, SRL16s and DCMs with fine phase
> stepping. ...
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60705Hi, I have some questions about XPower. 1)Can we get a time-based "detailed" report using XPower? I would like to know the power consumed by each logic block at different instances of time. Is it possible? (using XPower or otherwise) The -tb switch in XPower only reports the total power consumed by the entire FPGA at different time instances. 2)XPower normally reports the average power consumed by different components of the FPGA over the entire simulation time. Is it possible to get the maximum power, instead of average power. Any help will be highly appreciated. Thanks, Aman PS: BTW, Is there another place to ask these tool-specific questions? My questions seem to be too Xilinx-specific; please let me know if Xilinx provides any such user group which might be a better place to ask such questions.Article: 60706
Don't do it. Use a crystal oscillator instead. The reason is that the
"inverter" created from FPGA resources between two pins consists of many
gain stages. In order for the crystal oscillator to work, the inverter
has to get biased into its active region. The string of logic gates
required to get an invert function between two FPGA pins involves too many
stages for it to reliably have a linear range, so the oscillator at best
will function only under some conditions. The old families had an
unbuffered inverter available at the pins.
Nagaraj wrote:
> Hi,
> I want to interface a crystal to a Xilinx FPGA. Earlier Xilinx FPGA
> devices like XC2000 series had crystal input provision which is not
> there in Spartan 30K gate device which I am using for my design.
> I want to know how to build an oscillator circuit (amplifier) for
> the crystal in FPGA.
> Any references?
>
> Regards,
> Nagaraj
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60707Maybe you should put a little PIC on the board just for configuration. That way you could use regular compression on the bitstream and put a smaller prom on the board and save money. The Spartan 3 supports partial configuration. Remember that the JTAG port is always live. If you can afford some consulting I can port some code to your system. SteveArticle: 60708
For simulation or for mapping into hardware?
MACEI'S wrote:
> Hi guys,
>
> Does anybody have any idea or any link or code for Additive White
> Gaussian Noise in VHDL ? Or any body have written it or not ?
>
> Also how to generate Random Number's in VHDL?
>
> Thanks
>
> Rgds
>
> Macie
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60709Recently came across an old FPGA circuit board, its an ORCA Version 1.0 evaluation module. It looks quite antiquated and came with no manuals or softwares whatsoever. I am wondering if there are any softwares out there on the net that I can find for it. Might be able to put it to some good use if I can find the darn softwares or at the very least documents, data sheets. Anyone know anything about it?Article: 60710
Peter Alfke <peter@xilinx.com> writes: > Ray Andraka wrote: > > > > True, but those muxes are virtually useless for data path because the bit > > pitch doesn't match the bit pitch of the arithmetic. No problem at all. 2 LUTs with F5 enabled may by double the vertical size of an data path bit. But as one is not using the carry chain when using F5 (the Lut/Fn/carry MUX ensures this) it is no problem to "zigzag" data path bits. Put each pair of data path bits into 2 vertical stripes of slices, very simple: . . . . . . . . 3 2 3 3 0..3.. = where bit gets processed 2 2>3> 2 > = enabled F5 MUX 1 0 1 1 0 0>1> 0 And with F5 being "vertical" it can be used (combining 2 LUTS to an 8 input AND or OR) in the corresponding control logic of an 1 slice wide data path segment, without having to sacrifice an 2nd slice or use up logic of the next (or even worse previous) segments control logic space. Now F6 using 2 horizontally neighboring slices (which is what you suggest for F5), that messes this scheme up. > So, the 12.5% stand for "virtually useless" multiplexers, useful RAM > capability, and the super-useful SRL16 shift-register capability that > enhances Ray's formidable talents even more. :-) Or the 12.5% stand for "LUT-saving and next to no delay" 2nd level in multiplexers (halves levels, 2/3s LUT usage), usefull RAM (inclusive F5-using 32bit, same trick!) and "I don't reconfigure LUTs" useless SRL16s. :-) Everyone sees their 1/8th of an LUT in different extra features. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Blacksmith - hardware runs the world, software controls the hardware code generates the software, have you coded today?Article: 60711
Aman Gayasen wrote: > 2)XPower normally reports the average power consumed by different > components of the FPGA over the entire simulation time. Is it possible > to get the maximum power, instead of average power. Why do you care to know? Instantaneous power is always supplied by the decoupling capacitors. Most people worry about power because it generates heat and/or discharges the battery. Both of these actions have a long time constant... Peter Alfke > >Article: 60712
Ray, You failed to take into account the many IP cores that are available that are optimized for a particular architecture. Examine the vendor's own free IP, for fee IP, and the community around that vendor for the number of independent or partner vendors of IP. You don't always have to suddenly create the most complex and highest performing logic out of thin air (as that is a tough job for the best of us). And don't forget the many talented consultants that create product specific IP that beats the performance of the best cores that folks may offer. But it is true that the more specialized and targeted you get, the less likely it will port conveniently to any other device, other than the manufacturer that it was originally on (and not even then if it is a new architecture). Austin Ray Andraka wrote: > The equation for utilization is very complex. For arithmetic data path however, > I do find > that the Xilinx structure permits a higher density measured in LUTs occupied > when comparing designs > for the same algorithm but optimized for the particular device. This is due > partially > to the fact that the Altera carry chain breaks the LUTs into a pair of 3 LUTs so > your arithmetic is > 2 input arithmetic where Xilinx's is 4 input arithmetic. Granted, Altera has > greatly improved the situation > by adding dedicated gating for doing an adder-subtracter in one level, as well > as logic to permit an > accumulator with load, which are probably the most common use of more than two > input arithmetic. > To be fair, the average user is not going to fully use the Xilinx capability > because the synthesis tools > do not do a great job at inferring more complex structures such as an add/mux or > mux/add etc. In order > to use that, you more or less need to do some very careful coding. Same is true > for taking advantage of > the SRL16s. > > The fact of the matter is, I think both vendor's numbers are slanted. Unless > you do the design with the > specific architecture in mind, you are not going to get optimum utilization of > that array. A design that is > optimized for one array is going to generally be a poor fit for another. > Presumably, both vendors have > taken a design or designs that were targetted to their parts, and then ported > those designs to the competition > to come up with these numbers. In both cases, naturally, their device is going > to show superior results > simply because the design database they are drawing upon was optimized to their > parts. > > As I've stated many times before, the comparison metric should be a raw count of > the number of 4 LUT/flip-flop > pairs plus a list of additional features with perhaps an equivalent utilization > of that feature if it were not available. > That way, the designer can make an informed decision based on what features he > thinks he will use. In cases > where he doesn't know, the most accurate comparision would be to ignore the > effect of special features altogether, > then accept the gains he gets by using them as gravy. > > Paul Leventis wrote: > > > I might as well give the Altera view -- 12.5% is a gross overstatement of > > the relative abilities of a Virtex LC vs. a Stratix LE. Our data suggests > > that nearly the reverse is true (about a 9% advantage for Stratix). Please > > see the following whitepaper for our reasoning and data. As you can see > > from Figure 1, your mileage will vary -- depending on your design, you could > > see vast density advantages from one architecture or the other. > > > > http://www.altera.com/literature/wp/wp_stx_logic_efficiency.pdf > > > > If we wanted to, we could start counting our M512 blocks as logic, as they > > can be used for shift-registers, small memories, and soft multipliers, but > > we don't bother. > > > > Bottom line -- you really need to compile *your* design to both Stratix and > > Virtex (or whatever families you are interested in) before you will really > > know what the story is density. Averages don't matter much to you if yours > > is that design that gets hosed in one architecture or the other! > > > > Regards, > > > > Paul Leventis > > Altera Corp. > > > > "Peter Alfke" <peter@xilinx.com> wrote in message > > news:3F69D605.63B715DB@xilinx.com... > > > Rick, I will not defend the +12,5%, but I can explain it: > > > > > > It is the price we all pay for the intense and sometimes ruthless > > > competition in this market. Without a bloodthirsty competitor "in our > > > rear-view mirror", we would be gentlemanlike and give you conservative > > > numbers. But the way it is, our marketing folks think it would throw > > > away some really (really!) powerful features if they are not somehow > > > represented in the numbers. Each Xilinx Logic Cell does more than an > > > Altera LE, there can be no doubt about that. > > > > > > This is not an excuse (personally I agree with you), but an explanation. > > > > > > Peter Alfke > > > ========================== > > > > > > rickman wrote: > > > I care about the fact that I have to ignore a > > > > column of data in a data sheet as marketing hype and use a calculator to > > > > get the *real* numbers. Clearly the marketing people don't think we can > > > > add and multiply ourselves. > > > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 60713
Go to google.com and enter "ORCA FPGA" ( with the quotation marks) and you will find 740 hits. ATT-Lucent sold the line to Lattice a while ago... Peter Alfke Sam Kaan wrote: > > Recently came across an old FPGA circuit board, its an ORCA Version > 1.0 evaluation module. It looks quite antiquated and came with no > manuals or softwares whatsoever. I am wondering if there are any > softwares out there on the net that I can find for it. Might be able > to put it to some good use if I can find the darn softwares or at the > very least documents, data sheets. Anyone know anything about it?Article: 60714
cadnewbie found a gem - >Recently came across an old FPGA circuit board, its an ORCA Version >1.0 evaluation module. It looks quite antiquated and came with no >manuals or softwares whatsoever. I am wondering if there are any >softwares out there on the net that I can find for it. Might be able >to put it to some good use if I can find the darn softwares or at the >very least documents, data sheets. Anyone know anything about it? > Don't have a lot of information on what you have in hand - but Lattice is now the company building the ORCA FPGA products, and developing new devices and families based on this technology. The history lesson is a bit long: ATT and Xilinx were once partnered for early XLX FPGAs, with ATT being a foundry source - at some point the partnership dissolved - and ATT created it's own family called ORCA( for Optimized Reconfigurable Component Array) - ATT spun off LUCENT (with microelectronics along for the ride) Lucent spun off AGERE (with microelectronics along, essentially this is AGERE) AGERE sold off the ORCA technology, along with ASIC technology used for high-end SERDES based FPSC, to Lattice Semiconductor. Lattice now builds and develops device families based on the technology acquired. So, I guess check the lattice website, at least you will find the datasheets for the device on the pcb, and software to design and develop these devices as well. Good luck with your project, I would suggest a call to your Lattice FAE - Michael Thomas Lattice SFAE NY/NJArticle: 60715
Jason Daughenbaugh wrote: >Hello all, > >I am considering using the LVDS mode in spartan-3 FPGAs to run >offboard via a cat-5 RJ-45 connector. We have been doing this for a >long time with LVDS parts from TI and National, but using the FPGA >directly would be a cost savings (but also require a lot of pins!) > >I am concerned about exposing these I/O pins this way, I feel much >safer with the layer of protection the LVDS parts put between the FPGA >and the outside world. I have no doubt that these parts are safer, >but do I need this? Most Xilinx parts claim a 2kV ESD spec, >human-body model, whereas the LVDS components spec 20kv. Or maybe I >would need to diode-protect these (expensive). > > Yup, that is a big difference. 2 KV of HBM ESD is really not very robust at all. >Does anyone have any advice, or has anyone had any good or bad >experiences doing this? Along these lines, what do you recommend to >protect any exposed FPGA pin? > My only experience is 5V Spartan FPGAs and XC9500 CPLDs. I have ONE customer who has blown up DOZENS of Xilinx parts. I have never been to his location, I'd like to find out what he is doing to cause this much damage. I have never had a field failure with any other customer. The product consists of several boards, one FPGA or CPLD each, that plug into a backplane. In another related product that puts much of that function into one larger FPGA, I went to the trouble of adding a bunch of Littelfuse SP720AB ESD suppressor arrays. I get them from Digi-Key, with 14 protected lines for $2.82 in quantity of 10. All I can say at this point is they don't affect the operation of the circuit. They do spec a low capacitance. I have had a few strasnge Xilinx incidents I can comment on. Once, in the winter, I was working on a board with an XCS10-3PC84C FPGA, and as I sat down, I touched the board. Sparks shot all over it, I am positive I saw at least 5 separate sparks, 4 of them jumping between pins on the board, and one from my finger! The board was powered on at the time, which may be relevant. That board is still working today! Another time, on the "related" product mentioned above, with an XCS30-4TQ144 FPGA, I had just assembled the board, powered it on, checked that it configured correctly (I have a RED LED that lights and goes off when the config completes OK) and then powered it off, to connect it to test gear. When I applied power again, it did not power up. The chip was shorted, and when I applied an external bench supply, the chip was drawing 1.8 A. I replaced the Spartan, and it worked fine. I was not aware of any particular thing that happened that could have caused an ESD event. JonArticle: 60716
Hello all, I am considering using the LVDS mode in spartan-3 FPGAs to run offboard via a cat-5 RJ-45 connector. We have been doing this for a long time with LVDS parts from TI and National, but using the FPGA directly would be a cost savings (but also require a lot of pins!) I am concerned about exposing these I/O pins this way, I feel much safer with the layer of protection the LVDS parts put between the FPGA and the outside world. I have no doubt that these parts are safer, but do I need this? Most Xilinx parts claim a 2kV ESD spec, human-body model, whereas the LVDS components spec 20kv. Or maybe I would need to diode-protect these (expensive). Does anyone have any advice, or has anyone had any good or bad experiences doing this? Along these lines, what do you recommend to protect any exposed FPGA pin? We usually try to avoid them, but otherwise we will use series resistors and diode protection depending on the application. Thanks! Jason Daughenbaugh http://www.aedbozeman.comArticle: 60717
Jason Daughenbaugh wrote: > Hello all, > > I am considering using the LVDS mode in spartan-3 FPGAs to run > offboard via a cat-5 RJ-45 connector. We have been doing this for a > long time with LVDS parts from TI and National, but using the FPGA > directly would be a cost savings (but also require a lot of pins!) > > I am concerned about exposing these I/O pins this way, I feel much > safer with the layer of protection the LVDS parts put between the FPGA > and the outside world. I have no doubt that these parts are safer, > but do I need this? Most Xilinx parts claim a 2kV ESD spec, > human-body model, whereas the LVDS components spec 20kv. Or maybe I > would need to diode-protect these (expensive). Consider that a customer may plug your RJ-45 into an ISDN socket with 100V DC across some of those pins. Look at at some ethernet phy app notes. -- Mike TreselerArticle: 60718
Yes, a delta sigma DAC can be done completely in an FPGA. All you need is
an RC filter on the pin. The shortwave radio demo I presented at MAPLD
(block diagram on the top page of my website) uses a pair of delta-sigma
dacs to produce quite good quality sound at a 25KHz sample rate (160 MHz
chip rate). Xilinx has an app-note for one possible design. A delta sigma
ADC, on the other hand requires some analog components to handle the compare
(although that may be able to be done with an LVDS input pair).
Eva Lau wrote:
> Hi!
> I'm a student and doing a project to construct an Oversampling
> Delta-Sigma DAC. I planned to build the system using Cadence, Verilog
> HDL and FPGA which are totally new to me, I don't know whether the FPGA
> can be programmed to build functions like oversampling and
> interpolation, or should I make that part by other electronic components
> and connect to the FPGA containing the delta-sigma modulator only?
> Hope someone can answer my question. Thanks in advance!
>
> Best Regards,
> Eva
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60719
Who said anything about the divisor being a constant?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60720
Depends on how clever the designer is. I'd wager that better than 95%t of the
hardware engineers today couldn't design the 360/91 from scratch with 10 times
the logic resources of the original.
Glen Herrmannsfeldt wrote:
>
> I do wonder how many Virtex devices it would take to implement a 360/91.
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60721
More than you can count on both hands and feet, even if you count in binary
:-)
Arnaldo Oliveira wrote:
> Hi!
>
> Could someone tell me how many transistors are integrated on the XC3S5000
> Spartan-3 device?
> Thank You.
> Arnaldo.
>
> --
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60722
Several of the textbooks on FFTs such as Smith & Smith "Handbook of realtime FFTs"
describe higher radix FFTs. I believe the Xilinx FFT core data sheet goes into a fair
amount of detail on a radix 4 kernel. The easiest way to do hardware sharing is to use
one kernel and run the data through it in multiple passes. You'll need to change the
twiddle factors (which are really a phase rotation) and the data ordering. The twiddles
can be handled by changing the input to a multiplier using a table. The data reordering
is doable by permuting the bits of your address counter.
DA is really a technique for doing multiply-accumulate, not just a multiply. There are
many ways to do the multiplications, for example if speed is not an issue you can use a
scaling accumulator for a fairly compact multiplier. See the page about multiplication on
my website. Flip-flop count is not the whole story, you also have to account for the
combinatorial logic between flip-flops. You could do a totally combinatorial multiplier
with no flip=flops, for example (although it would be quite slow if it is reasonably
sized)
PJ wrote:
> Hi Ray/Andyman,
>
> Thanks for replying.
>
> Ray ....
> Is there a good explanation on radix-4 ffts ? If I can mod the code
> quickly, I will certainly do it. As regarding shared hardware, I
> thought about that when implementing my design, but I really couldn't
> figure out a way to do it. Are you talking about reducing the number
> of stages ? Did you use RAM to provide the hardware sharing ?
>
> I have let the synthesis tools generate the multiplier. I just used
> the '*' function. This is one area I think I could make good space
> saving. I have seen your articles about multipliers on your website.
> Would a DA type multiplier save me much space ?
>
> What is the most efficient multiplier in terms of flop count, and is
> there VHDL code or verilog code available. I'll gladly write it
> myself, if I can get some pointers. I can trade speed for gate count.
> My problem now is the lack of time I have to get this project
> completed.
>
> Andyman
>
> I have implemented RAM in my design, and thankfully it synthesis to
> RAM fine. However in saying that...that is for very small designs.
> This certainly might be a problem. I am using leonardo spectrum, and
> will give synplify a try next.
> If you found any solutions...I would be glad to hear.
>
> Thank you both for your time and your replies.
>
> Good luck
> PJ
>
> Ray Andraka <ray@andraka.com> wrote in message news:<3F664CBB.86459E77@andraka.com>...
> > It very heavily depends on your implementation. The fact that it is
> > radix2 and
> > not radix 4 or higher tells me already that your implementation is not a
> > very
> > efficient one. A radix 4 kernel is very little added complexity over a
> > radix 2
> > kernel and cuts the processing time and area considerable. Depending on
> > your
> > speed requirements and your design prowess, you can certainly fit a 128
> > point
> > real-only FFT in a much smaller part than a 1M gate part. As your speed
> > requirements decrease, you can take advantage of iterative or shared
> > hardware
> > to reduce the gate count considerably. I did a 4096 point design in a
> > Xilinx
> > XCV1000 that does the complex transform in 68 us (the floorplan and a
> > brief
> > description are on the gallery page on my website). That one only
> > occupies
> > about 40% of the FPGA and includes some floating point stuff as well as
> > windowing multipliers and some other goodies. It takes intimate
> > knowledge
> > of the FPGA structure and of algorithms to achieve that level of density
> > (the customer called the design "a work of art"), but even a novice can
> > achieve a density/performance level of half that design with some
> > carefully
> > thought out design.
> >
> > PJ wrote:
> >
> > > Hello,
> > >
> > > I am implementing a 128 point real Radix-2 fft, data and coefficient
> > > widths are 16 bit.
> > > I am synthezising it for use in an FPGA. However, it is taking a very
> > > long time to synthesize. (approx 3 days using Leonardo on a 2 GHz
> > > machine with 512 MByte RAM) I am using a 20K1000 Altera FPGA. The ram
> > > required by the fft will be internal to the FPGA
> > >
> > > Will this design take up all the space on the device. From past
> > > experience, can someone give me an indication of what area of the
> > > device the fft will occupy.
> > >
> > > Surely if it takes up most of the device, then it will be too big, as
> > > I have other features to implement in the FPGA also !!
> > >
> > > Thank you
> > > PJ
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60723I think the answer is " more than 100 million, but less than 300 million". We are caught between embarrassment: "that's how many we need" and pride: "that's how good we are, to be able to make and sell that many for a reasonable price". An then there still are some people who really and seriously (!) think they can calculate device reliability and MTBF from the total number of transistors. These guys do not seem to die out, even though we have told them, and proven to them, again and again, that such calculations are utter nonsense. So Ray is right, you would need another seven or eight fingers... Peter Alfke ======================== Ray Andraka wrote: > > More than you can count on both hands and feet, even if you count in binary > :-) > > Arnaldo Oliveira wrote: > > > Hi! > > > > Could someone tell me how many transistors are integrated on the XC3S5000 > > Spartan-3 device? > > Thank You. > > Arnaldo. > > > > -- > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 60724
Ray Andraka wrote: > > Yes, a delta sigma DAC can be done completely in an FPGA. All you need is > an RC filter on the pin. The shortwave radio demo I presented at MAPLD > (block diagram on the top page of my website) uses a pair of delta-sigma > dacs to produce quite good quality sound at a 25KHz sample rate (160 MHz > chip rate). Xilinx has an app-note for one possible design. A delta sigma > ADC, on the other hand requires some analog components to handle the compare > (although that may be able to be done with an LVDS input pair). Depends on the precision you are chasing. A straight FPGA pin -> RC will have 50% of the power/ground noise at idle. ( ie lousy PSRR, and crosstalk) but would be OK for mono shortwave radio audio. For higher presisons 12/16/24 bit regions, external TinyLogic Buffer or analog switches should be used, to 'clean/low noise' +ve/Gnd lines. Keeps the FPGA for digital stuff, and separate, but very simple parts for the analog stuff. Highest presisions should also use a true integrator, for the charge balancing. -jg > > Eva Lau wrote: > > > Hi! > > I'm a student and doing a project to construct an Oversampling > > Delta-Sigma DAC. I planned to build the system using Cadence, Verilog > > HDL and FPGA which are totally new to me, I don't know whether the FPGA > > can be programmed to build functions like oversampling and > > interpolation, or should I make that part by other electronic components > > and connect to the FPGA containing the delta-sigma modulator only? > > Hope someone can answer my question. Thanks in advance! > > > > Best Regards, > > Eva
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z