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Marc Randolph wrote: > > "Pete Fraser" <pete@rgb.com> wrote in message news:<vm1nindpbsac54@news.supernews.com>... > > You mentioned in a recent thread that the 3S1000 would sell > > for $20 in CY2004 in the slowest speed grade and large > > quantities. > > > > I was recently quoted $85.65 for XC3S1000-4FG676C > > in 5000s for CY2004. Is there really such a huge difference > > between 5000 piece prices and "large quantities"? > > > > Howdy Pete, > > Believe me, you are not anywhere near "large quantities." Xilinx uses > that phrase when they put useless prices in their press releases - it > most often refers to 250k pieces a year, so you are only off by 50x. > See > http://www.xilinx.com/prs_rls/silicon_spart/0333spartan3.htm or almost > any other of their recent press releases for examples. He may be nowhere near the quarter million pieces to get the optimum price, but I bet with a little arm twisting - I mean, by asking nicely - he can get $30 or better. When a part is new a chip maker will try very hard to get early design wins. Without them their parts will wither on the vine and never recover. I don't think 5000 pieces a year is anything to ignore in this market. He actually said he would be ordering in 5000 piece quantities, so the annual volume may be much larger. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60401
rickman wrote: > > Peter Alfke wrote: <snip> > > To repeat, I like the capture window approach because it is independent > > of data rate and clock rate. > > Greetings, and thanks for the discussion. It helped me clear up my mind... > > I don't want to beat a dead horse, but I do want to make clear that the > capture window model does not eliminate the frequency of the clock and > data from the failure rate calculation. The basic probability of a > failure from any single event is clearly explained by the window model, > but to get a failure rate you need to know the clock rates to know how > often the the possible event is tested, so to speak. If you double > either the clock or the data rate, you double the failure rate. I'm collecting empirical results - do you have any URLs, especially covering the 'double either' aspect ? -jgArticle: 60402
I think after XACT 6 was rechristened to "M" ("merged" due to Neocad
purchase) it became M1, M1.5 etc. and AFAIR it was somewhere there the "i"
was added. (and later M was replaced by ISE when XST was added) "i" meant
"internet aware" as Rickman pointed out, and the reasons I think was context
sensitive help documents being linked to the web documents...or something
similar...
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F60CAC2.56AF1034@yahoo.com...
> "Steven K. Knapp" wrote:
> >
> > Correct, for the XC3S50J devices, you'll want to keep ISE5.2i around.
> >
> > What does the "i" stand for? For me, it stands for "I don't know". :-).
I
> > believe that it stands for ISE (Integrated Software Environment) to
> > distinguish it from earlier "Foundation" software. Still, just a guess.
>
> IIRC, the 'i' was added on the first version that was Internet aware. I
> can't say what features were made possible by having web connectivity,
> but they have never dropped the designation.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
Article: 60403Hi everyone, Lets say I have an application that needs the following: Do a partial RTR ( Run Time Reconfiguration) of a Virtex Device continuosly through out its life time at very frequent intervals. And I can live with the Reconfiguratin delay Can this be done? Do you see any issues with this? Any comments? Are there any tools (API) made using JBITS that currently handle scheduling of RTR that anyone is aware of? Thanks in Advance KodeArticle: 60404
soar2morrow@yahoo.com (Tom Seim) wrote in message news:<6c71b322.0309111000.5458aeee@posting.google.com>... > Check these IEEE references: > > Efficient designs of unified 2's complement division and square root > algorithm and architecture > Sau-Gee Chen; Chieh-Chih Li; > TENCON '94. IEEE Region 10's Ninth Annual International Conference. > Theme: 'Frontiers of Computer Technology'. Proceedings of 1994 , 22-26 > Aug. 1994 > Page(s): 943 -947 vol.2 > > A new pipelined divider with a small lookup table > Jong-Chul Jeong; Woong Jeong; Hyun-Jae Woo; Seung-Ho Kwak; Woo-Chan > Park; Moon-Key Lee; Tak-don Han; > ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on , 6-8 > Aug. 2002 > Page(s): 33 -36 > > > Efficient semisystolic architectures for finite-field arithmetic > Jain, S.K.; Song, L.; Parhi, K.K.; > Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , > Volume: 6 Issue: 1 , March 1998 > Page(s): 101 -113 thanks for the pointers .. i have found some of them. looking into the NR and its variants .. whether it's possible to fit it into some 3000 slices in virtex-ii .. may be i'll have to increase no of iteration per div step ..Article: 60406
Hi, I have already used DCMs in real hw : a DDR controller on an Avnet board and I got it to work. It used 3 DCM (2 for the DDR and another for something else). There were even cascaded. Now, on a simpler design, I can't get it to lock. It simulates ok, synthesis ok, place and route ok, but the DCM does not lock. I can see that that's the case since I connected the lock signal to the LEDs on the board. Basically, I have an SDRAM addition to the Avnet board. Because the clock can only be provided by the FPGA, I need to make sure that clock and data going out to the SDRAM have some reasonable skew to avoid set up and hold time problems. So, I simply anticipate the outgoing clock of about 1 ns using a DCM. The output of the DCM is fed back to the CLK_FBK input through a BUFG. It also goes out to a pad (after BUFG) through a FDDRSE primitive and OBUF. To see if there is a clock at all, this skewed clock is divided and connected to a LED on the board. The clock is there as the LED flashes. However, it does not lock. The clock goes nowhere else : only to the divider and to the OBUF. The clock is 40 MHz which is within the range specs for XC2V4000-4 (24-180 MHz) in low frequency mode. This is much simpler than the DDR code and I'm going mental trying to find out why. Any ideas ? The code is pretty small and I could even post it here, there's nothing secret about it. Please help, ArthurArticle: 60407
Hi Terry, have your read Xilinx's Application Note xapp663 "TCP/IP on Virtex-II Pro Devices Using lwIP"? They have implemented an light-weight IP stack. Perhaps you an see from their sources how to send and receive Ethernet frame. The Application Note and the source code is availble form Xilinx's hompage Regards ErikArticle: 60408
Hi John! John Williams wrote: > They're there, but for some reason Xilinx makes them very hard to find: > > http://www.xilinx.com/guest_resources/gnu/index.htm Thanks a lot for that link! I just grabbed the file. I expected that this stuff is somewhere available due to the GPL. But I can also understand why the source code is not being actively promoted... >> Actually, I would like to use the debugger under native >> Linux with ddd frontend rather than inside a VMware with >> Windows/Cygwin as I'm doing it right now. > > The source package at the address I just gave has the entire toolchain > source for the EDK, microblaze and PPC, binutils, gcc, gdb and so on. > > We've successfully rebuilt binutils and gdb under linux native, so it > definitely can be done. So far, I'm already using a gcc-3.3.1 as compiler (cross-compiler under x86-Linux) and it is working fine. Perhaps I can adopt the Xilinx-changes of gdb-5.1 to the recent gdb. Again, thanks for your help. Regards, MarioArticle: 60409
Hi Look at signal connected to feedback in DCM. Try to connect output signal from DCM (that You use for feedback) to ordinary BUF and then to feedback input (CLKFB). Maybe feedback needs little delay? Best regards Jerzy Gbur -- "Everything is simple until it'll be comprehensible" - furiaArticle: 60410
"ykagarwal" <yog_aga@yahoo.co.in> wrote in message news:4d05e2c6.0309112255.3dbc30e4@posting.google.com... > soar2morrow@yahoo.com (Tom Seim) wrote in message news:<6c71b322.0309111000.5458aeee@posting.google.com>... > > Check these IEEE references: > > > > Efficient designs of unified 2's complement division and square root > > algorithm and architecture > > Sau-Gee Chen; Chieh-Chih Li; > > TENCON '94. IEEE Region 10's Ninth Annual International Conference. > > Theme: 'Frontiers of Computer Technology'. Proceedings of 1994 , 22-26 > > Aug. 1994 > > Page(s): 943 -947 vol.2 > > > > A new pipelined divider with a small lookup table > > Jong-Chul Jeong; Woong Jeong; Hyun-Jae Woo; Seung-Ho Kwak; Woo-Chan > > Park; Moon-Key Lee; Tak-don Han; > > ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on , 6-8 > > Aug. 2002 > > Page(s): 33 -36 > > > > > > Efficient semisystolic architectures for finite-field arithmetic > > Jain, S.K.; Song, L.; Parhi, K.K.; > > Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , > > Volume: 6 Issue: 1 , March 1998 > > Page(s): 101 -113 > > thanks for the pointers .. i have found some of them. looking into the > NR and its variants .. whether it's possible to fit it into some 3000 slices > in virtex-ii .. may be i'll have to increase no of iteration per div step .. The 360/91 was built from transistors glued onto ceramic substrates, and wired together. It did double precision floating point divide in 18 clock cycles, though. I think it is three clock cycles per iteration, so six iterations. I do wonder how many Virtex devices it would take to implement a 360/91. -- glenArticle: 60411
Hi NG. I have downloaded the mbvanilla_ddr_v2_00_b.zip project at:
http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
When I try to download it, gives the error below, what is wrong??? I am
unsign the Insight/Memec V2MB1000 Virtex2 evaluation board, if it is
problems with the scan-chain then where do I set this? When I download other
examples (for example LED og other projects from Xillinx dedicated to this
board) they download fine, so something is bugging me on this :-(
Best Regards
Terry Andersen
INFO:iMPACT:1366 -
Reading etc\xcr3064xl_vq44.bsd...
// *** BATCH CMD : program -p 2
Validating chain...
INFO:iMPACT:1209 - Testing for '0' at position 12.The Instruction capture of
the
device 2 does not match expected capture.
INFO:iMPACT:1206 - Instruction Capture = '1111100000001110101'
INFO:iMPACT:1207 - Expected Capture = '000XXX01XXXX0100001'
ERROR:iMPACT:1210 - '2':Boundary-scan chain test failed at bit position '1'.
A problem may exist in the hardware configuration.
Check that the cable, scan chain, and power connections are intact,
that the specified scan chain configuration matches the actual hardware,
and
that the power supply is adequate and delivering the correct voltage.
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
Done.
Article: 60412>> "Erik Hansen" <hansen@shf.biz> wrote in message news:ee7fb33.0@WebX.sUN8CHnE... >> Hi Terry, >> have your read Xilinx's Application Note xapp663 "TCP/IP on Virtex-II Pro >> Devices Using lwIP"? >> They have implemented an light-weight IP stack. Perhaps you an see from >> their sources how to send and receive Ethernet frame. >> The Application Note and the source code is availble form Xilinx's hompage >> Regards >> Erik Hi Erik. Thanks a lot for the reply. Here is my MHS: # Parameters PARAMETER VERSION = 2.0.0 # Global Ports PORT sys_clk_raw = sys_clk_raw, DIR = IN, SIGIS = CLK PORT ddr_clk_fb = ddr_clk_fb, DIR = IN, SIGIS = CLK PORT rx = rx, DIR = IN PORT tx = tx, DIR = OUT PORT IAD_GP = IAD_GP, DIR = INOUT, VEC = [0:15] PORT IDMA_CNTL_GP = IDMA_CNTL_GP, DIR = INOUT, VEC = [0:7] PORT Buttons_GP = Buttons_GP, DIR = INOUT, VEC = [0:1] PORT pwm0 = pwm0, DIR = OUT PORT ddr_clk = ddr_clk, DIR = OUT PORT ddr_clkn = ddr_clkn, DIR = OUT PORT ddr_clke = ddr_clke, DIR = OUT PORT ddr_csn = ddr_csn, DIR = OUT PORT ddr_rasn = ddr_rasn, DIR = OUT PORT ddr_casn = ddr_casn, DIR = OUT PORT ddr_wen = ddr_wen, DIR = OUT PORT ddr_dqm = ddr_dqm, DIR = OUT, VEC = [0:1] PORT ddr_ba = ddr_ba, DIR = OUT, VEC = [0:1] PORT ddr_addr = ddr_addr, DIR = OUT, VEC = [0:12] PORT ddr_dq = ddr_dq, DIR = INOUT, VEC = [0:15] PORT ddr_dqs = ddr_dqs, DIR = INOUT, VEC = [0:1] PORT RESET_GP = RESET_GP, DIR = INOUT, VEC = [0:1] PORT system_reset = system_reset, DIR = IN # Sub Components BEGIN dcm_ip PARAMETER INSTANCE = mydcm1_dcm_ip PORT sys_clk = sys_clk_raw PORT clk0_out = sys_clk PORT clk90_out = sys_clk_90 END BEGIN dcm_ip PARAMETER INSTANCE = mydcm2_dcm_ip PORT sys_clk = ddr_clk_fb PORT clk90_out = ddr_clk_90 END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = islmb PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x0000FFFF BUS_INTERFACE SLMB = i_lmb BUS_INTERFACE BRAM_PORT = porta END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dslmb PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x0000FFFF BUS_INTERFACE SLMB = d_lmb BUS_INTERFACE BRAM_PORT = portb END BEGIN bram_block PARAMETER INSTANCE = bram1 PARAMETER HW_VER = 1.00.a PARAMETER C_MEMSIZE = 131072 PARAMETER C_PORT_DWIDTH = 32 PARAMETER C_PORT_AWIDTH = 32 PARAMETER C_NUM_WE = 4 BUS_INTERFACE PORTA = porta BUS_INTERFACE PORTB = portb END BEGIN microblaze PARAMETER INSTANCE = mblaze PARAMETER HW_VER = 1.00.c PARAMETER C_DATA_SIZE = 32 PARAMETER C_USE_BARREL = 0 PARAMETER C_FSL_LINKS = 0 PARAMETER C_FSL_DATA_SIZE = 32 PORT CLK = sys_clk PORT INTERRUPT = the_interrupt BUS_INTERFACE DLMB = d_lmb BUS_INTERFACE ILMB = i_lmb BUS_INTERFACE DOPB = myopb END BEGIN opb_uartlite PARAMETER INSTANCE = myuart PARAMETER HW_VER = 1.00.b PARAMETER C_DATA_BITS = 8 PARAMETER C_CLK_FREQ = 100000000 PARAMETER C_BAUDRATE = 19200 PARAMETER C_USE_PARITY = 0 PARAMETER C_BASEADDR = 0xFFFF8100 PARAMETER C_HIGHADDR = 0xFFFF81FF PORT RX = rx PORT TX = tx BUS_INTERFACE SOPB = myopb END BEGIN opb_gpio PARAMETER INSTANCE = IAD PARAMETER HW_VER = 1.00.a PARAMETER C_GPIO_WIDTH = 16 PARAMETER C_ALL_INPUTS = 0 PARAMETER C_BASEADDR = 0xFFFF9000 PARAMETER C_HIGHADDR = 0xFFFF90FF PORT GPIO_IO = IAD_GP BUS_INTERFACE SOPB = myopb END BEGIN opb_gpio PARAMETER INSTANCE = IDMA_CNTL PARAMETER HW_VER = 1.00.a PARAMETER C_GPIO_WIDTH = 8 PARAMETER C_ALL_INPUTS = 0 PARAMETER C_BASEADDR = 0xFFFFA000 PARAMETER C_HIGHADDR = 0xFFFFA0FF PORT GPIO_IO = IDMA_CNTL_GP BUS_INTERFACE SOPB = myopb END BEGIN opb_gpio PARAMETER INSTANCE = Buttons PARAMETER HW_VER = 1.00.a PARAMETER C_GPIO_WIDTH = 2 PARAMETER C_ALL_INPUTS = 0 PARAMETER C_BASEADDR = 0xFFFFB000 PARAMETER C_HIGHADDR = 0xFFFFB0FF PORT GPIO_IO = Buttons_GP BUS_INTERFACE SOPB = myopb END BEGIN opb_timer PARAMETER INSTANCE = Sampling_Timer PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0xFFFFC000 PARAMETER C_HIGHADDR = 0xFFFFC0FF PORT CaptureTrig0 = net_gnd PORT CaptureTrig1 = net_gnd PORT PWM0 = pwm0 PORT Interrupt = timer1_interrupt BUS_INTERFACE SOPB = myopb END BEGIN opb_jtag_uart PARAMETER INSTANCE = myjtag PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0xFFFFD000 PARAMETER C_HIGHADDR = 0xFFFFD0FF PORT OPB_Clk = sys_clk BUS_INTERFACE SOPB = myopb END BEGIN opb_ddr PARAMETER INSTANCE = my_opb_ddr PARAMETER HW_VER = 1.00.b PARAMETER C_DDR_TMRD = 15000 PARAMETER C_DDR_TWR = 15000 PARAMETER C_DDR_TWTR = 1 PARAMETER C_DDR_TRAS = 40000 PARAMETER C_DDR_TRC = 65000 PARAMETER C_DDR_TRFC = 75000 PARAMETER C_DDR_TRCD = 20000 PARAMETER C_DDR_TRRD = 15000 PARAMETER C_DDR_TREFC = 70000000 PARAMETER C_DDR_TREFI = 7800000 PARAMETER C_DDR_TRP = 20000 PARAMETER C_DDR_CAS_LAT = 2 PARAMETER C_DDR_DWIDTH = 16 PARAMETER C_DDR_AWIDTH = 13 PARAMETER C_DDR_COL_AWIDTH = 9 PARAMETER C_BASEADDR = 0xFE000000 PARAMETER C_HIGHADDR = 0xFEFFFFFF PORT OPB_Clk = sys_clk PORT DDR_Clk = ddr_clk PORT DDR_Clkn = ddr_clkn PORT DDR_CKE = ddr_clke PORT DDR_CSn = ddr_csn PORT DDR_RASn = ddr_rasn PORT DDR_CASn = ddr_casn PORT DDR_WEn = ddr_wen PORT DDR_DM = ddr_dqm PORT DDR_BankAddr = ddr_ba PORT DDR_Addr = ddr_addr PORT DDR_DQ = ddr_dq PORT DDR_DQS = ddr_dqs PORT Clk90_in = sys_clk_90 PORT DDR_Clk90_in = ddr_clk_90 BUS_INTERFACE SOPB = myopb END BEGIN opb_gpio PARAMETER INSTANCE = RESET PARAMETER HW_VER = 1.00.a PARAMETER C_GPIO_WIDTH = 2 PARAMETER C_ALL_INPUTS = 0 PARAMETER C_BASEADDR = 0xFFFFE000 PARAMETER C_HIGHADDR = 0xFFFFE0FF PORT GPIO_IO = RESET_GP BUS_INTERFACE SOPB = myopb END BEGIN opb_intc PARAMETER INSTANCE = interrupt_controller PARAMETER HW_VER = 1.00.c PARAMETER C_BASEADDR = 0xFFFFF000 PARAMETER C_HIGHADDR = 0xFFFFF0FF PORT Intr = timer1_interrupt PORT Irq = the_interrupt BUS_INTERFACE SOPB = myopb END BEGIN lmb_v10 PARAMETER INSTANCE = d_lmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT LMB_Clk = sys_clk PORT SYS_Rst = system_reset END BEGIN lmb_v10 PARAMETER INSTANCE = i_lmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT LMB_Clk = sys_clk PORT SYS_Rst = system_reset END BEGIN opb_v20 PARAMETER INSTANCE = myopb PARAMETER HW_VER = 1.10.a PARAMETER C_EXT_RESET_HIGH = 0 PORT SYS_Rst = system_reset PORT OPB_Clk = sys_clk ENDArticle: 60413
lishu99@yahoo.com (Lis Hu) writes: [Top post moved down] > murkspi@amuro.net (mur KSpi) wrote in message news:<e0e6dba0.0309110536.18a61b2b@posting.google.com>... > > Is the following achievable? > > > > - Two PCs render graphics and output it to their graphics card DVI > > outputs > > - A FPGA based board reads these two data streams (maybe using Silicon > > Image receivers?) and processes the data (basically a comparison of > > pixel values) > > - The processed data is output via DVI. This output could be used as > > an input to another FPGA board and so forth.. > > > > What components (FPGAs, DVI receivers, transmitters) would one need? > > Thanks for all answers.. > > > > Andre > You would need at least DVI receivers, transmitters, and the FPGA. > Unless you can synchronize the two output streams, you would need > memory for buffering, so that you can "line up" the pixels. If the PCs > are outputting different resolutions or at different refresh frequencies, > you would need a scaler/converter. > > I missed the start of this thread for some reason, but it sounds fairly straightforward - you could use wither TI or SiI parts for the DVI input and output. Are you just looking for a BW image out as to whether the pixels differ or not, or are you going to quantify the difference and display it in gray/colour? Either way it should be fairly straightforward, even in a smallish FPGA Out of interest what's the end-application? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 60414
Terry, Depending on your board with/without the P160 Module attached, your JTAG chain may be different I suggest to run Impact first (with the GUI) to figure out what's the chain content (graphic mode) and then check it against the ./etc/download.cmd file (script file for Impact) After that modify the ./etc/download.cmd file to match the actual chain. Aurash Terry Andersen wrote: > Hi NG. I have downloaded the mbvanilla_ddr_v2_00_b.zip project at: > > http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux > > When I try to download it, gives the error below, what is wrong??? I am > unsign the Insight/Memec V2MB1000 Virtex2 evaluation board, if it is > problems with the scan-chain then where do I set this? When I download other > examples (for example LED og other projects from Xillinx dedicated to this > board) they download fine, so something is bugging me on this :-( > > Best Regards > Terry Andersen > > INFO:iMPACT:1366 - > Reading etc\xcr3064xl_vq44.bsd... > // *** BATCH CMD : program -p 2 > Validating chain... > INFO:iMPACT:1209 - Testing for '0' at position 12.The Instruction capture of > the > device 2 does not match expected capture. > INFO:iMPACT:1206 - Instruction Capture = '1111100000001110101' > INFO:iMPACT:1207 - Expected Capture = '000XXX01XXXX0100001' > ERROR:iMPACT:1210 - '2':Boundary-scan chain test failed at bit position '1'. > A problem may exist in the hardware configuration. > Check that the cable, scan chain, and power connections are intact, > that the specified scan chain configuration matches the actual hardware, > and > that the power supply is adequate and delivering the correct voltage. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > Done. -- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324Article: 60415
Hi, I am quite new in this field. I was wondering if we can run a linux mini kernel on fpga with full networking support. I went to the site www.uclinux.org, but could not find any port for fpga. I might be wrong, may be I could not recognize it. Any info on this is greatly appreciated. Thanks SrikanthArticle: 60416
Hi! I am using SPARTAN 2 XC2S150 for my design. I have a question regarding pull up resistors. I am using ISE5.1. 1)What is meant by optional pull ups? There are options in the Constraints Editor to insert pull ups at the I/Os. Are these PERMANENT pull ups or just during configuration? If I select these pull ups, then i also need to set M2M1M0=100 ? 2)Alternatively if i DO NOT select those pull ups in the Constraints editor, but i still set M2M1M0=100 then what will happen? Pull ups will be used for configuration only? 3) Do i need to connect all my VCCO pins to 3.3V and VCCINT to 2.5V? All GND pins on the pacakge be grounded? 4)If I use one clock signal in my design, then it can be input on only one IGCKO(input global clock buffer) or i need to connect all IGCK's to this clk signal? Regards RiderArticle: 60417
Clyde R. Shappee <clydes@the_world.com> wrote in message news:3F6118EE.96AB3E46@the_world.com... > I have used Webpack 4.2 something and I believe the ISE foundation of about the > same edition. > > I have found that they are essentially identical, with the following > differences: > > Webpack does not have the core generator. You cannot use the block rams and > other on chip resources. That's not true Clyde, you've just got to know what they're called and instantiate them directly. See the Picoblaze and 'VirtexII picoblaze (more instruction memory) on a SpartanII' projects on the Downloads page of my web site below. Both done with web-pack and both instantiate blockrams. Nial Stewart ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 60418
"GB" <donotspam_grantbt@jps.net> schrieb im Newsbeitrag
news:fNH6b.2542$PE6.510@newsread3.news.pas.earthlink.net...
> Hi,
>
> I'm a firmware guy pulled into a project well out of my area of
> expertise. My boss wants to build (essentially) a digital camera
> using an image sensor chip (1600x1200) and output it's data
> "as fast as possible" using USB2.0.
{some text removed}
> Also, this is something that I am sure we will have to contract
> out, so if you have any past experience with this, please let
> me know your thoughts (and if you are available).
>
> Thanks!
You might consider using a FPGA-board (Xilinx Spartan-II) with integrated
USB-2 interface (Cypress).
You can find a list of boards on
http://www.optimagic.com/boards.html
The USB-2 FPGA board I made (USB2FPGA), comes with schematics.
You can use it to build your own hardware if you like. If you dont want to
buy it, you can load the schematics from
http://www.cesys.com/english/Ebene2/download.htm
Here you find information about the board itsself:
http://www.cesys.com/english/Ebene3/USB2FPGA.htm
-> If you need help connecting your CCD to the board please contact me.
-Manfred, CESYS GmbH
mkraus-at-cesys-dot-com
Article: 60419> > Try removing the db directory and recompiling. > > -hpa I think the title I used was not accurate: it should be "smart compilation did not SAVE my design". The fact it runs for more than one hour can only mean that Quartus did recompile everything (even the design has no change except 8 wires and I didn't remove the db directory). So, let me redefine my questions: 1. Why with "smart compilation" turned on it still recompiles everything? 2. Why the compilation didn't work after I moved 8 wires? thanks! YiArticle: 60420
Hi! Could someone tell me how many transistors are integrated on the XC3S5000 Spartan-3 device? Thank You. Arnaldo. --Article: 60421
Hi! Is it possible to convert a Xilinx Foundation 3.1i project (including schematic diagrams) to Xilinx ISE 4.1/5.1/5.2 ? Thank You Arnaldo.Article: 60422
dont try to download with XPS (waste of time) download with impact manually, or if that doesnt work use Chipscope for downloading - for some of the boards we have Chipscope is only thing that works, dont understand why xilinx cant make their download software to work. antti > When I try to download it, gives the error below, what is wrong??? I am > unsign the Insight/Memec V2MB1000 Virtex2 evaluation board, if it is > > INFO:iMPACT:1366 - > Reading etc\xcr3064xl_vq44.bsd... > // *** BATCH CMD : program -p 2 > Validating chain... > INFO:iMPACT:1209 - Testing for '0' at position 12.The Instruction capture of > the > device 2 does not match expected capture. > INFO:iMPACT:1206 - Instruction Capture = '1111100000001110101' > INFO:iMPACT:1207 - Expected Capture = '000XXX01XXXX0100001'Article: 60423
Austin, I am guessing that you did not work on the design for the S3. Xilinx has told me everything from there would be no adverse effect from a mismatched output, to causing complete failure. I have kept all of the correspondences if you would like me to post them, but I really don’t see the value in doing so. I am not sure why they seem unable to come up with an answer that they all agree upon. I do not agree with your statement “…, as the nmos is ON, or the pmos is ON, effectively clamping the IOB pin to either gnd or Vcco.” . If we look at an example of an I/O pin (so not a dedicated output), when we transition from a low to high state on the output, the high side driver is sourcing current to the load. As the signal propagates down our transmission line and reaches the end, some energy will reflect back. Let’s use a very high impedance for our termination, so the reflected signal is in phase with the incident. As the reflected signal reaches the output pin it will raise the voltage. Because the driver is sourcing, it has no way to clamp this transient. So, the catch diodes would clamp the reflected signal to a level just over the supply voltage. It’s nice to make the comment about “is not recommended to have poor signal integrity”, but it does not help with the problem. If the devices MTBF decreases with the amount of reflected energy, it would be good to know how close the impedance must be matched. Let’s say you did all of your homework in the layout. You have simulated every trace. Even so, most of the board houses will not guarantee a perfect board is made. There will be a tolerance for the board. Especially if you are playing around with FR-4. So, then we have to ask how close do we need to match the impeadances before we start to see an increase in the failure rates. If this is really an issue with the S3, it will be the first time I have seen this in a digital device. I have seen damage to some higher-powered RF output devices when they have not been matched correctly, due to overheating. Maybe the S3 is so sensitive that it can be damaged this way. Had they not mentioned the S3 being so sensitive during their presentation, I would not have tried to investigate it. Well, Xilinx, can you come up with an answer that you KNOW is correct?Article: 60424
"Tom Hawkins" <tom1@launchbird.com> wrote in message = news:833030c0.0309100656.72bb2da8@posting.google.com... > I need a single chip solution for a control system and DSP > application. > The primary consideration is board area. The second, cost. > Here's what I'm looking for: > - 5V supply and I/O. > - Embedded ADC (at least 1, preferably 8). Slow rate (50 Hz). > - Small FPGA fabric. About the size of a small spartan. > - Embedded block ram (4 KBytes). > - Flash FPGA. Would like not to have separate config prom. > - Low I/O count. I only need about 30 pins. >=20 > Does anything like this exist? If 5V I/O is not possible, what's > needed to translate about 12 pins from 3.3/1.2 to 5V? >=20 > Also, what's envolved for FPGA based software defined radio? I'd like > to build an RC (as in radio control airplane) receiver. Most FM > radios hop between 2 frequencies to encode pulse widths which in turn > drive the RC servos. So nothing digital. It just needs to extract > the pulse train from the FM. I would consider trading an FM receiver > chip for an external high-speed ADC and a larger FPGA if it buys > enough flexibility. >=20 > Regards, > Tom looked at the atmel fpslic devices? big cost is the license after the one in the dev kit runs out(4 months). basically an avr + small fpga http://www.atmel.com/products/FPSLIC/ http://www.atmel.com/dyn/products/devices.asp?family_id=3D627 http://www.atmel.com/dyn/products/tools.asp?family_id=3D627 http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3D2752
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