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Here is what I say in seminars: Latches are only used by very inexperienced designers, and by very experienced designers. The inexperienced ones don't realize the pitfalls ( and get themselves into bad trouble), the really experienced ones appreciated the advantages ( and know how to stay out of trouble). The average designer is much better off with only flip-flops. Peter Alfke ================== David R Brooks wrote: > > As others have written, your code doesn't actually infer a latch. > > Indeed, you should not be using latches unless you are very sure what > you are doing. One of their few uses on a FPGA is in linking > asynchronous clock domains (itself a very specialised business). > There is a design note on Xilinx TechXclusives that does this. > > Download a copy of the Xilinx Libraries Guide: it includes sample > code to instantiate all the different primitives. > Xilinx will implement a latch using the asynchronous set/reset inputs > to a flipflop. > > J_Jeniffer@excite.com (Jeniffer) wrote: > > :Hi all, > :I am trying to implement a design in virtex device. My design contains > :quite a few latches (intended). When I implement the design and open > :the design in the FPGA editor, I see that the latches are implemented > :using LUTs and not using the registers in the slice. The device contains > :free resources of registers. Is there a way, I can force the latches to > :be implemented in registers (other than using primitives)? I would > :prefer the code to be portable. > : > :My code (VHDL) for latch looks something like this: > : > :process (enable, din) > :begin > :if (enable = 0) then > :dout <= din; > :else > :dout <= dout; > :end if; > :end process; > : > :Thankyou for your time, > :JenifferArticle: 53151
"Kevin Neilson" <kevin_neilson@removethistextattbi.com> wrote in message news:<fVV8a.348429$vm2.264512@rwcrnsc54>... > He wants to use `include, to include a text file of comments that > initializes a blockRAM, but he wants to do it conditionally based on the > hierarchy of the module. That is, he wants to reuse the same module in many > places, but wants to `include a different text file in each one. This is not possible. The `include directive is effectively done before the file compiles, and changes the source code that gets compiled, just as if you had copied the text in with an editor before compiling. It can't be changed later in the process, any more than the source code can be changed at that point. There are ways of getting different RAM contents into different modules in Verilog. However, from the reference to "a text file of comments", I gather that your tool has some kludge mechanism of its own that uses comments for this. This would make it very clumsy to do what he wants to do. If you meant something else, you should explain it. The normal way of doing this kind of thing in Verilog would be to use the $readmem[b|h] system task to read the memory contents from a file. The filename to be used for this could be a parameter, like what he was trying to do with the `include. If the data needs to be part of the source file, the $sreadmem[b|h] system task allows reading the data from a string instead of a file. Setting a parameter to such a long string might not work well in your tool, but should technically work.Article: 53152
Hello we are an ASIC/FPGA company currently understaffed but with a very limited budget; so I wonder under what circumstances and what type of projects(non crucial?) we could consider outsourcing to some(which?) developing country team? Thanks MAArticle: 53153
"TI" <anglomont@yahoo.com> wrote in message news:18a34598.0303041845.33b150a0@posting.google.com... > Hello > we are an ASIC/FPGA company currently understaffed but with a very > limited budget; so I wonder under what circumstances and what type of > projects(non crucial?) we could consider outsourcing to some(which?) > developing country team? > Thanks > MA If you're located in the U.S., you might consider NOT outsourcing. You'll typically get the job done in twice the time, half as well, and no less financial resources. Not to mention contributing to the massive problem of wealth and skilled professionals declining in this country. People in other countries often, to put it bluntly, falsify their qualifications and try to Google out the answers afterwards. You WILL find American engineers willing to do your project for the sweat-shop pay you hope to shell out. Many are doing projects for free, in the hopes of expanding their experience and landing a real job.Article: 53154
Correction to Brad Eckert's posting: > > Altera uses a third party synthesis tool with Quartus, so licensing > > isn't so simple. AKAIK the Mentor evaluation license lasts for 30 > > days. Quartus II has native HDL (VHDL, Verilog) synthesis capabilities. Therefore you can perform design entry, synthesis, place and route entirely within the integrated Quartus II environment without a third party synthesis tool. These capabilities are available in the free Quartus II Web Edition software. - Subroto Datta Altera Corporation "siriuswmx" <wangmanxi@yahoo.com> wrote in message news:4528663b.0303040432.1af8f98@posting.google.com... > Thank you . > I prefer the chip APEX20K , but it is FPGA or CPLD, How to > differentiate FPGA from CPLD? and are there mang differences of the > programming between FPGA and CPLD ? > :) > brad@tinyboot.com (Brad Eckert) wrote in message > > > Both companies claim to have the lowest cost FPGAs. 8-) > > > > I haven't used Altera, so I can't make a good comparison. But, > > installing ISE Webpack was very easy. I got the CD and a product key > > from Xilinx for free, and it will run forever. The next thing I knew I > > was pushing buttons and synthesizing and fitting VHDL. Too cool. > > > > Altera uses a third party synthesis tool with Quartus, so licensing > > isn't so simple. AKAIK the Mentor evaluation license lasts for 30 > > days.Article: 53155
It's really not that hard to meet the DCM's input jitter reqs. It poses some limitations when cascading DCM's, but just be aware of it and plan ahead. The company I work for is a very large user of Xilinx, and have shipped many Virtex-II's on our boards. No major problems -- but we did our homework. Put the logic in to detect when the DCM loses lock. Make sure you don't exceed the SSO limits. Keep the input jitter down. Take advantage of the numerous features of the DCM. No worries. Bob "Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3E64DC3C.3F5A20C0@xilinx.com... > Hakon, > > Well, if the noise is less than what we specify (ie 200 mV peak to peak) > there are no problems (at least from the noise).... > > If the input jitter or noise is far worse than what we specify, then you > should take that into account, and either fix the jitter/noise, or make a > design that can reset itself when the DCM unlocks due to excessive input > jitter, and tolerate the occasional resets due to operating out of > specifications. > > Quite simply, if you exceed the jitter input specification, do not expect > the DCM to remain locked. > > As for hundreds, let us say rather that millions of pcbs have been shipped > that use the DCM, and this is not a problem that we see occurring in the > field except in a very few selected cases; which turn out to be due to > excessive noise or bad signal integrity in the initial design and we get > them solved. Every time we solve a problem, we post it as an answer, so > that our hotline (and the customer) doesn't have to keep guessing at what > might be wrong. > > The fact that there are so many 'answers' for the DCM just means they are > a popular and useful feature, that gets used a lot, and people are always > finding new ways to break them and exceed the specifications. > > Austin > > Hakon Lislebo wrote: > > > Hi all of you! > > I have seen a lot of postings related to DCM's unlocking because of > > ground bounce and jitter on the input clock to the DCM. I also had a > > problem with that on a prototype. Buffering the input clock solved > > that because the problem was crosstalk from other signals. > > > > My concern is this... the DLL need a reset when it loses lock and > > there seemes to be several problems that leeds to a DCM loosing lock. > > If you have a design that shall run for years without restart, there > > is a great chance that the DLL will unlock and corrupt the data > > transmission or whatever it does. Personally I intend to make an > > auto-reset based on the status signals from the DLL. In most > > application notes from Xilinx they tie DCM RESET to GND, should't they > > at least make a footnote that warn you about this possible situation? > > A design may work in the lab for a few days, but what about the noisy > > environment of the customers? > > > > What do you think? Do you have the guts to send out hundreds of PBA's > > with DLL RESET tied to GND? What does the Xilinx guys says about this? > > > > Regards > > Håkon Lislebø > >Article: 53156
"TI" <anglomont@yahoo.com> wrote in message news:18a34598.0303041845.33b150a0@posting.google.com... > Hello > we are an ASIC/FPGA company currently understaffed but with a very > limited budget; so I wonder under what circumstances and what type of > projects(non crucial?) we could consider outsourcing to some(which?) > developing country team? > Thanks > MA How long is a piece of string? Questions to ask... -just how 'non-crucial' is it? -what's your budget? -who will write the specifications and contract? -can you manage the contract over the distance? -language difficulties? -what's Plan B for if/when the outsourcing fails? -would you gain more medium/long term if you built up in-house skills? etc etc And don't forget the other poster's comment that US-based people exist who could do your task - why go ex-country when you don't have to? You're in dangerous territory anyway without adding more difficulties in. KenArticle: 53157
Gimme job. I do it for old tin cans and used coffee grinds. Cheap enough, mister? "TI" <anglomont@yahoo.com> wrote in message news:18a34598.0303041845.33b150a0@posting.google.com... > Hello > we are an ASIC/FPGA company currently understaffed but with a very > limited budget; so I wonder under what circumstances and what type of > projects(non crucial?) we could consider outsourcing to some(which?) > developing country team? > Thanks > MAArticle: 53158
"Steven Sharp" <sharp@cadence.com> wrote in message news:3a8e124e.0303041745.73aaf9fa@posting.google.com... > > This is not possible. The `include directive is effectively done > before the file compiles, and changes the source code that gets > compiled, just as if you had copied the text in with an editor > before compiling. It can't be changed later in the process, any > more than the source code can be changed at that point. > > There are ways of getting different RAM contents into different > modules in Verilog. However, from the reference to "a text file > of comments", I gather that your tool has some kludge mechanism > of its own that uses comments for this. This would make it very > clumsy to do what he wants to do. If you meant something else, > you should explain it. > > The normal way of doing this kind of thing in Verilog would be to > use the $readmem[b|h] system task to read the memory contents from a > file. The filename to be used for this could be a parameter, like > what he was trying to do with the `include. If the data needs to > be part of the source file, the $sreadmem[b|h] system task allows > reading the data from a string instead of a file. Setting a > parameter to such a long string might not work well in your tool, > but should technically work. $readmem would work for simulation, but not synthesis. The only synthesizable way to initialize a blockRAM in a Xilinx that is is to use comments or a particular syntax that the synthesizer passes on to the place&route tool. The FPGA synthesizers aren't yet smart enough to use $readmem; they just ignore it completely.Article: 53159
On Wed, 05 Mar 2003 03:33:19 GMT, "Bob" <nimby1_not_spmmm@earthlink.net> wrote: >It's really not that hard to meet the DCM's input jitter reqs. It poses some >limitations when cascading DCM's, but just be aware of it and plan ahead. > >The company I work for is a very large user of Xilinx, and have shipped many >Virtex-II's on our boards. No major problems -- but we did our homework. > >Put the logic in to detect when the DCM loses lock. Make sure you don't >exceed the SSO limits. Keep the input jitter down. Take advantage of the >numerous features of the DCM. No worries. Differential (e.g. LVDS, PECL) inputs also help. Allan. >Bob > > > >"Austin Lesea" <austin.lesea@xilinx.com> wrote in message >news:3E64DC3C.3F5A20C0@xilinx.com... >> Hakon, >> >> Well, if the noise is less than what we specify (ie 200 mV peak to peak) >> there are no problems (at least from the noise).... >> >> If the input jitter or noise is far worse than what we specify, then you >> should take that into account, and either fix the jitter/noise, or make a >> design that can reset itself when the DCM unlocks due to excessive input >> jitter, and tolerate the occasional resets due to operating out of >> specifications. >> >> Quite simply, if you exceed the jitter input specification, do not expect >> the DCM to remain locked. >> >> As for hundreds, let us say rather that millions of pcbs have been shipped >> that use the DCM, and this is not a problem that we see occurring in the >> field except in a very few selected cases; which turn out to be due to >> excessive noise or bad signal integrity in the initial design and we get >> them solved. Every time we solve a problem, we post it as an answer, so >> that our hotline (and the customer) doesn't have to keep guessing at what >> might be wrong. >> >> The fact that there are so many 'answers' for the DCM just means they are >> a popular and useful feature, that gets used a lot, and people are always >> finding new ways to break them and exceed the specifications. >> >> Austin >> >> Hakon Lislebo wrote: >> >> > Hi all of you! >> > I have seen a lot of postings related to DCM's unlocking because of >> > ground bounce and jitter on the input clock to the DCM. I also had a >> > problem with that on a prototype. Buffering the input clock solved >> > that because the problem was crosstalk from other signals. >> > >> > My concern is this... the DLL need a reset when it loses lock and >> > there seemes to be several problems that leeds to a DCM loosing lock. >> > If you have a design that shall run for years without restart, there >> > is a great chance that the DLL will unlock and corrupt the data >> > transmission or whatever it does. Personally I intend to make an >> > auto-reset based on the status signals from the DLL. In most >> > application notes from Xilinx they tie DCM RESET to GND, should't they >> > at least make a footnote that warn you about this possible situation? >> > A design may work in the lab for a few days, but what about the noisy >> > environment of the customers? >> > >> > What do you think? Do you have the guts to send out hundreds of PBA's >> > with DLL RESET tied to GND? What does the Xilinx guys says about this? >> > >> > Regards >> > Håkon Lislebø >> >> >Article: 53160
Hi My Name is E.Blaschek I use a Mac-Notebook for my private use, Intel and SUN Based CPU Computers at work. I did think over this Problem for a few months. There is a software package that Emulates a Intel Based CPU on a Mac. Virtual PC 3.x from Connectix Take a look at http://www.macwindows.com/VPC3.html There are some other Emulators too, but as a lack of time i had a glance on this one. You can choose between to have different Operating systems. There are Win 98B Win2000 Win-Xp and Linux I would be glad to hear from You With best regards "Tomas" <tmlo@networks.nera.no> wrote in message news:87f5aba4.0303040322.570bb649@posting.google.com... > Hi all, > > I am considering the future hardware platforms for our designs. As our > groups have a wide experience with unix environments (we have been > using Solaris for a while, now), we would like to continue in this > world. > > Basically all the EDA tools we need run for either Solaris, HP and > some of them now, Linux. I am not going to list all the pro's and > con's of these platforms, we have already heard enough about it. > > What I am mostly curious about is the feasibility of Mac based FPGA > design. Mac Os X is a nice and SUPPORTED Unix OS, and the Xservers > from Apple are not too expensive compared to equivalent Intel boxes... > And with the rumored advent of the 970 chips from IBM they might > become even more interesting. > > Of course none of EDA tools we use (Modelsim, Leonardo, Synplify, > Xilinx Alliance...) have native versions for Mac OS X. > > What do you all think about this? Should we press the EDA vendors to > come up with yet-another-supported-platform? > > Regards, > TomasArticle: 53161
The newer SPartan2e devices XC2S400e and XS2S600e are unknown to the EDK3.1 (SP3). Installation of the XC2S400/600 device files for ISE5.1 doesn't help. Any hints ? AndreasArticle: 53162
> What I am mostly curious about is the feasibility of Mac based FPGA > design. Mac Os X is a nice and SUPPORTED Unix OS, and the Xservers > from Apple are not too expensive compared to equivalent Intel boxes... > And with the rumored advent of the 970 chips from IBM they might > become even more interesting. > > Of course none of EDA tools we use (Modelsim, Leonardo, Synplify, > Xilinx Alliance...) have native versions for Mac OS X. > > What do you all think about this? Should we press the EDA vendors to > come up with yet-another-supported-platform? Yes, I am definitely interested in seeing more on OS X. I keep on asking Xilinx and Altera about it, but everybody out there should be pushing too to make things happen. In the meantime, I am working with some free and open source tools: For editing and as simple IDE, I am using jEdit. jEdit becomes really useful with a few (also free) plugins: I recommend adding CodeBrowser, Console, Drag and Drop, Error List, Mac OS, Project Viewer and QuickNotepad to it. jEdit may be found here: http://www.jedit.org/ For simulation I am using Icarus Verilog. The status of the simulator is pretty good and it compiles easily under OS X. Icarus may be found here: http://www.icarus.com/eda/verilog/ As waveform viewer I am using GTKwave. It is working, though you might be missing a few features from your favourite simulator. GTKwave compiles easily under OS X and runs with X11. Find GTKwave here: http://www.cs.man.ac.uk/amulet/tools/gtkwave/ I am keeping my flow together with a Makefile which I trigger from jEdit's Console plugin. I am currently working on porting IVI to OS X, a graphical frontend for Icarus. IVI is based on Tcl/Tk so it should be possible to make it a native Aqua application... but there is still some work to do. Find IVI here: http://ivi.sourceforge.net/ Some other work is going on here, I am not sure about the current status: http://epicentertech.net/html/current_projects.html While the above mentioned tools will not bring synthesis and implementation tools to Mac OS X, it should still be enough to do most of the development work on the Mac. I am currently running the Xilinx tools on Windows XP. The PC is connected to my Mac with the Remote Desktop, and I have all files on my Mac shared to the PC via Samba. This makes the whole system at least usable. If you are interested in supporting the development/ port of these tools, if you know about further interesting projects on OS X, or if you need a little assistance to get things going on OS X, drop me a mail. Best regards Felix _____ Dipl.-Ing. Felix Bertram Email: fbertram at emagic dot deArticle: 53163
> I'm using the LeonardoSpectrum that comes with the Altera software > subscription. Is there a way to run it on the command line without > going through the GUI? (Mostly I want to use a Makefile to manage > the synthesis flow.) Hi Lis, you use tcl-Scripting with LeonardoSpectrum either from the GUI (File -> run Script) or in your case from the command line by calling leonardo like this: spectrum.exe -file my_script.tcl. You can generate scripts by using the commands logged in exemplar.his after systhesis using the gui. Or you can write your own more efficient scripts with the commands documented in Leonardo's reference manual. As there are different licences for Loenardo I can not tell whether scripting is supported in the version provided by altera. ErikArticle: 53164
Dear all, I would connect an hard-drive to the PCMCIA interface of my board. Is there anybody that can suggest how to do with a simple fpga? I know that a Fpga is too much but we would use to do other interfaces for the board. Thanks in Advance Regards BrazilArticle: 53165
Generally an RTL model, right? No timing info? "Puneet" <pugupta@vt.edu> wrote in message news:3E637F31.40501@vt.edu... > check out this link. It has some info on BFM's > > http://www.tempusf.com/DesignCon_2002.pdf > > cheers > Puneet > > geeko wrote: > > Anybody familiar with the term Bus Functional Model (BFM).Is any BFM is > > available for AHB (free or low cost).Is the devlopment of a BFM is complex . > > Comments > > > > > > > > > > > > >Article: 53166
You can compile the unisim/simprim source that is in the xilinx directory into an Aldec library.
Goran wrote:
> Thanks, Ray.
> But how can I update libraries? I contacted people in Aldec support,
> and they didn't give me any clear answer. They just told me it would
> be if I buy new edition ( $4K for Xilinx edition).
> My idea is to start developing some serious stuff in FPGAs for
> company I work in, but I first have to show "some" results with what
> we already got, before I start pursuading my chief to buy some real
> stuff.
> Thanks,
> Goran
>
> Ray Andraka <ray@andraka.com> wrote in message news:<3E640E13.EB3569B6@andraka.com>...
> > XST does a fine job, much better than foundation did. You will be happy with it. You can use your Aldec for both
> > pre-PAR and post route simulations. Aldec 3.2 is getting a bit long in the tooth now, the current version is 5.2. Just
> > make sure your unisim and simprim libraries have been updated and you should be fine though. For what it is worth, the
> > later editions of Aldec fixed a few annoying bugs in 3.2, increased the simulation speed considerably, and added
> > features. You'd probably find the update to be well worth the money when you can afford it.
> >
> > Goran wrote:
> >
> > > kevinbraceusenet@hotmail.com (Kevin Brace) wrote in message news:<cc7b0b5f.0302231456.ce5e3f9@posting.google.com>...
> > >
> > > Kevin,
> > > Thanks for answer.
> > >
> > > > Goran,
> > > >
> > > > Which Xilinx part are you planning to target?
> > >
> > > Spartan IIe, smaler Virtex (mainly because multipliers).Below 300K
> > > gates.
> > >
> > > > As long as you are targeting Xilinx devices below 300K system gates or
> > > > you don't have to target a 2.5V Virtex device, you may want to try the
> > > > free ISE WebPACK first before paying for ISE BASE-X.
> > > > Unlike ISE BASE-X users, ISE WebPACK users won't have access to FPGA
> > > > Editor or CORE Generator, but if those tools aren't important to you,
> > > > you should be fine with ISE WebPACK.
> > >
> > > I would like to use CORE Generator. I think it's a nice thing and ISE
> > > baseX doesn't seem to expencive. I don't like paying every year,
> > > but...
> > >
> > > > Regarding ModelSim XE, you may want to try ModelSim XE-Starter
> > > > first before paying for ModelSim XE.
> > > > Yes, ModelSim XE-Starter has a 500 statements limit, but what that
> > > > really means is that the simulation speed will drop after that limit,
> > > > and the simulator will still continue to run past that limit.
> > > > In the past, I have simulated a design that exceeded the 500
> > > > statements limitation by 40,000 lines, but ModelSim XE-Starter
> > > > completed the simulation fine.
> > > > However, it took quite a time to complete because I was doing a Post
> > > > P&R simulation of a design, and a Post P&R simulation is inherently
> > > > very slow compared to an RTL simulation.
> > >
> > > The problem is we have some older version of Aldecs ActiveVHDL, I
> > > think 3.2. I did lot of behavioral simulations on this one, and I like
> > > it. My question is can I import post place & route design from ISE and
> > > perform simulation in ActiveVHDL 3.2? I'm beginer in this, so really
> > > need help!
> > >
> > > > I also agree with Spam Hater that XST's synthesis quality is
> > > > good, so unless you don't mind paying $8,000 for a third party
> > > > synthesis tool, I will just use XST.
> > >
> > > Lot of people are saying XST is OK. Since I mind paying that much I'll
> > > go with XST.
> > >
> > > Regards,
> > > Goran
> > >
> > > >
> > > >
> > > > Kevin Brace (If someone wants to respond to what I wrote, I prefer if
> > > > you will do so within the newsgroup.)
> > > >
> > > >
> > > >
> > > > goran@net.yu (Goran) wrote in message news:<3c0f6336.0302221215.1ab0ed0d@posting.google.com>...
> > > > > Hi all,
> > > > > I work in small, development company, and we would like to start some
> > > > > more advanced FPGA designs (we are now using Xilinx FPGAs for simple
> > > > > glue logic only). My question is what tools we need to complete medium
> > > > > sized projects on Spartan IIe & smaller Virtex members.
> > > > > I learned (on Xilinx web site) that ISEbaseX would be OK?
> > > > > Does "one year license" that you buy from Xilinx mean your software
> > > > > stops working after one year, or you just don't have access to
> > > > > updates?
> > > > > If we purchase ModelSim XE does the same license apply?
> > > > > Can we use another VHDL simulator for post place & route simulation?
> > > > > We have, for example, Active VHDL, can we use it?
> > > > > How does XST behave, do we have to buy other synthezis tool to compile
> > > > > anything more advanced?
> > > > > Thanks in advance,
> > > > > Goran.
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 53167ok thank you very much You just confirm me what i was thinking (genetic FPGA only works with the Celoxica) but i thought there wes a way to make it work with the virtexDS. I understand now why i got the error : can't load SRAM !!!! i'll manage to get answers from the jbits yahoo news letter. I didn't even know there was on dedicated to Jbits ;-) anyway thank you again for your help A+.Panzo "Alex Carreira" <aycarrei@shaw.ca> a écrit dans le message de news: b41i02$45i$1@nserve1.acs.ucalgary.ca... > Hi Panzo, > > Although I have little experience with Genetic FPGA for JBits, I believe > that the following two pieces of information from > ...\JBits2.8\doc\GeneticFPGA\GeneticFPGA.html will be of interest to you: > > "The Virtex Device Simulator does not support the Global Set Reset > functionality nor provide support for the SRAMs. It is suggested that > GeneticFPGA be used with the Celoxica RC1000pp board." > > "The API to the user code has changed. User code generated for previous > versions will not work with this version. The user code should be either > updated or previous versions should be maintained." > > After reading the GeneticFPGA.html file, it would seem that it is not > possible to run GeneticFPGA without a Celoxica board (see the requirements > section) in JBits 2.8. Perhaps it is possible with the VirtexDS in earlier > versions of the tool, as the section "Changes to Version 2.8" might suggest. > > Also, you might try posting this message on the JBits newsgroup at yahoo > groups and reviewing the messages there as I recall some discussion about > this subject a few months ago. (You might also wish to subscribe to > jbits@yahoogroups.com from www.yahoo.com) > > Hope this helps, > > Alex Carreira > > > > > "panzo" <panzo@wanadoo.fr> wrote in message > news:b3i2nh$3dr$1@news.cict.fr... > > Hi, > > > > I'm lookin for someone who has some experience with Jbits tool , > especially > > the genetic hardware part. I need help with some examples provided with > the > > Genetic FPGA classes from the Jbits library. > > I can't get work the examples named Prec1x1, 2x2 ... and following > > I work with the virtex simulator VirtexDS configured as the XCV100 board. > > The compiler says that the CoreTemplate class throws the exception : > "Device > > XCV50 was specified, but Device XCV1000was targetted". I wonder if the > > genetic FPGA is able to work with another board than the Rc1000pp board > > (XCV1000). > > If i configure my virtexDS as XCV1000 then the compiler says a little > > farther that it could not load the SRAM onto the device. > > > > If you have succeeded to make it work yourself, please help me !!! > > > > A+.Panzo > > > > > >Article: 53168
Can anyone please suggest how can a square root function be implemented in a Altera Apex20K device. Is there any free megafunction for this purpose available.Article: 53169
"Sujatha" <sujatha.sriram@philips.com> wrote > Can anyone please suggest how can a square root function > be implemented in a Altera Apex20K device. Is there any > free megafunction for this purpose Aw, c'mon, give us a clue! Floating-point, fixed-point, integer? How many bits? How fast do you need it to be? How much FPGA real-estate can you afford to spend on this function? What do you intend to do with the extra fraction bits you'll get? Depending on the answers to these questions, you may end up using lookup tables, CORDIC, successive-approximation, polynomial approximations... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 53170
Is the ADC connected to your FPGA working properly? From what you described, you are sampling a 32MHz signal with a 4MHz (32MHz/8) sampling frequency. I am not sure what you are trying to do. Where did you measure the output? Is it the digital output of the FPGA or the output of your DAC? If it is the output of DAC, make sure the DAC is working properly. Jim Wu "Noddy" <g9731642@campus.ru.ac.za> wrote in message news:1046759282.172014@skink.ru.ac.za... > The actual hardware receives white noise samples...in simulation I try to > use a random sequence of input samples. The input frequency is a white noise > source, filtered through an analogue LP filter with cutoff 32 MHz, whilte > the cutoff of the LPF is 2MHz... this problem has nothing to do with signal > attenuation! > > adrianArticle: 53171
"Steven John Buckley" <buckley@zetnet.co.uk> wrote > I have the task of replacing a bunch of ALTERA > EP310 PLDs for a new design but only have the > JED files for them. I need the equation for them. > I have scanned the NET but can only find > JED2EQN.EXE which does not have the EP310 in the library. > I don't care about the format of the equations EQN,CUPL etc. > Does anyone know of a simple utility around that will take > the EP310 JED files and output something that tells me what > the damn things do. EP310s are fairly simple things and it may be easier to go the other way - find out what the circuit as a whole does, and re-engineer it in a more up-to-date technology. Otherwise you're only engaged in painstaking regeneration of someone else's bugs :-) However, if you really must... I had a look at the library files for JED2EQN and I reckon it wouldn't be too hard to reverse-engineer it and add a new library entry for the EP310. That's the sort of thing that I used to love doing when I was a youngster with a good eye for detail, and I hate doing now that I'm an old fogey who expects his software to do the work instead! Do you expect to be able to divine the devices' functionality from the Boolean equations? It can be hard to separate trees from forest. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 53172
"Brendan Lynskey" <brendan@comodogroup.com> wrote in message news:LJk9a.10170$Vx2.774245@wards... > Generally an RTL model, right? No timing info? Not necessarily an RTL model. It can be written in HDL, or C, or any other languages, as long as it correctly describes the behavior of the bus and is able to interact with your DUT. Jim Wu jimwu88NOOOSPAM@yahoo.comArticle: 53173
I'd just like to hear some opinions and experiences with using the Xilinx EDIF flow for blockbox instantiation; for instance, dropping in IP produced by Core Generator. Is this flow pretty smooth? What are the common hang-ups? How well does it work with third-party synthesis tools? The reason I'm asking is that we are considering direct FPGA synthesis of the Confluence design language--Virtex-II would be the first supported platform. But instead of full chip synthesis, we plan to generate component EDIF netlists similar to that produced by Core Generator. This would allow platform optimized Confluence IP to integrated with a standard HDL flow. I'd appreciate any opinions. Regards, Tom -- Tom Hawkins tom1@launchbird.com Launchbird Design Systems, Inc. http://www.launchbird.com/Article: 53174
Either the development software, or the software that comes with the programmer, should be able to display the fuse map of the design. With the help of the data sheet, you should be able to read the equations right off the fuse map. David "Steven John Buckley" <buckley@zetnet.co.uk> wrote in message news:2003030413563069639@zetnet.co.uk... > Not sure if this is the right place but here goes! > I have the task of replacing a bunch of ALTERA > EP310 PLDs for a new design but only have the > JED files for them. I need the equation for them. > I have scanned the NET but can only find > JED2EQN.EXE which does not have the EP310 in the library. > I don't care about the format of the equations EQN,CUPL etc. > Does anyone know of a simple utility around that will take > the EP310 JED files and output something that tells me what > the damn things do. > Any help will be gratefullt received. > > Regards > Steve >
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