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Woah, please excuse the poor spelling. It was quite late when I wrote that, but the information still holds :) Tony "Tony M" <tonym_98@hotmail.com> wrote in message news:uURR9.8391$zV2.2218514491@newssvr10.news.prodigy.com... > I depends on which version of the chip you have and number of gates and the > speed of your programming system and the programming method (serial? select > i/o parallel? jtag?). > > Read the tech notes on programming the chips. > > A quick example might be the Virtex 300k gate chip, with a config clock of > 50 MHz, using SelectMAP programming mode. > > It can be programmed at up to 50mhz without having to worry about a 'wait > i'm processing' signal from the virtex chip. As noted in the tech docs, the > bit stream size is IIRC 297860 bytes. > Using SelectMAP 8-bit interface you can send over 1 byte per cclk > (configuration clock) for a rate of 50 megabytes per second. doing the > math 297860 bytes / (50 MBps) = 5.9572 ms. add a few uS before and after to > erase and start programming as well as init the device after programming, > again these #'s are in the tech doc. > > Tony > > > "Sumanth Donthi" <thetallman63@yahoo.com> wrote in message > news:b43a630c.0301042013.275fc342@posting.google.com... > > hi! > > > > How can you determine the reconfiguration time of the Xilinx > > virtex/virtex E FPGA and atmel AT40K FPGA? > > > > Thanks, > > Sumanth Donthi > >Article: 51176
I may as well follow up to share the price info I obtained by calling BP: BP 1400 (5V devices): $1495 BP 1600 (to 1.8V): $4995 Individual PLCC modules: $200-$300 Universal PLCC module: $1000 Universal TSOP module: $450 Modules work with all BP univeral programmers. These prices are definitely lower than DATA I/O programmers, although all the DATA I/O units program lower-voltage devices. Also, software and device updates are free for life, unlike Data I/O which is $1300/year. If you want to automatically embed serial numbers, you have to buy a software add-on, at an additional charge, although the person I spoke with didn't think this is still the case. Dave <dfnr2@yahoo.com> wrote in message news:<m34r8yao2s.fsf@yahoo.com>... > Would anyone who recently bought a BP-1200 care > to post some prices for the 1200, any of the extra modules, any > upgrades, and the software upgrade to generate serial numbers. > > Also, is it possible to write your own little program to generate > serial numbers, and have the free BP software call it, or do you still > have to pay for an "advanced features" package?Article: 51177
Hi! Thank you for the reply Tony. Is Technical notes here refers to application notes? can you send me the link that has these numbers please... thanks, Sumanth Donthi "Tony M" <tonym_98@hotmail.com> wrote in message news:<uURR9.8391$zV2.2218514491@newssvr10.news.prodigy.com>... > I depends on which version of the chip you have and number of gates and the > speed of your programming system and the programming method (serial? select > i/o parallel? jtag?). > > Read the tech notes on programming the chips. > > A quick example might be the Virtex 300k gate chip, with a config clock of > 50 MHz, using SelectMAP programming mode. > > It can be programmed at up to 50mhz without having to worry about a 'wait > i'm processing' signal from the virtex chip. As noted in the tech docs, the > bit stream size is IIRC 297860 bytes. > Using SelectMAP 8-bit interface you can send over 1 byte per cclk > (configuration clock) for a rate of 50 megabytes per second. doing the > math 297860 bytes / (50 MBps) = 5.9572 ms. add a few uS before and after to > erase and start programming as well as init the device after programming, > again these #'s are in the tech doc. > > Tony > > > "Sumanth Donthi" <thetallman63@yahoo.com> wrote in message > news:b43a630c.0301042013.275fc342@posting.google.com... > > hi! > > > > How can you determine the reconfiguration time of the Xilinx > > virtex/virtex E FPGA and atmel AT40K FPGA? > > > > Thanks, > > Sumanth DonthiArticle: 51178
http://direct.xilinx.com/bvdocs/publications/ds003.pdf "Sumanth Donthi" <thetallman63@yahoo.com> wrote in message news:b43a630c.0301050916.fd5e065@posting.google.com... > Hi! > Thank you for the reply Tony. Is Technical notes here refers to > application notes? can you send me the link that has these numbers > please... > > thanks, > Sumanth Donthi > > > "Tony M" <tonym_98@hotmail.com> wrote in message news:<uURR9.8391$zV2.2218514491@newssvr10.news.prodigy.com>... > > I depends on which version of the chip you have and number of gates and the > > speed of your programming system and the programming method (serial? select > > i/o parallel? jtag?). > > > > Read the tech notes on programming the chips. > > > > A quick example might be the Virtex 300k gate chip, with a config clock of > > 50 MHz, using SelectMAP programming mode. > > > > It can be programmed at up to 50mhz without having to worry about a 'wait > > i'm processing' signal from the virtex chip. As noted in the tech docs, the > > bit stream size is IIRC 297860 bytes. > > Using SelectMAP 8-bit interface you can send over 1 byte per cclk > > (configuration clock) for a rate of 50 megabytes per second. doing the > > math 297860 bytes / (50 MBps) = 5.9572 ms. add a few uS before and after to > > erase and start programming as well as init the device after programming, > > again these #'s are in the tech doc. > > > > Tony > > > > > > "Sumanth Donthi" <thetallman63@yahoo.com> wrote in message > > news:b43a630c.0301042013.275fc342@posting.google.com... > > > hi! > > > > > > How can you determine the reconfiguration time of the Xilinx > > > virtex/virtex E FPGA and atmel AT40K FPGA? > > > > > > Thanks, > > > Sumanth DonthiArticle: 51179
m.bonny@tu-bs.de (Talal) wrote in message news:<74512307.0301041410.cd891ec@posting.google.com>... > Hello All, > Every time i try to place and rote my design, I get this error: > > ERROR:Place:106 - Could not find an automatic placement for the following > components: > clkp of type GCLK IOB is unplaced. > initilization_dll0 of type DLL is placed at DLL2. > initilization_dll1 of type DLL is placed at DLL1. > initilization_bufg2 of type GCLK BUFFER is placed at GCLKBUF2. > initilization_bufg1 of type GCLK BUFFER is placed at GCLKBUF0. > initilization_bufg0 of type GCLK BUFFER is placed at GCLKBUF1. > ERROR:Place:107 - Xilinx requires using locate constraints to preplace such > connected GCLK/GCLKIO/DLL components. > > > Any one knows the solution? > > Talal Hello All, I found the solution: Some versions of the software require all SSLT2 I/Os to be manually placed. so I have to place clkp manully in a pin which is from the type GCLK IOB such as: A16, D17, AL16 or AK16 (if the device is Virtex). so I have to add to the .ucf file this line: NET clkp LOC = A16; we have to consider that the Related GCLK/GCLKIO/DLL components should be placed on the same edge of the chip if possible and Not all configurations may allow this Regards TalalArticle: 51180
dfnr2@yahoo.com (David) writes: > BP 1400 (5V devices): $1495 > BP 1600 (to 1.8V): $4995 Oops, I got the model numbers wrong. It's BP 1200 (5V devices): $1495 BP 1400 (to 1.8V): $4995 I don't know what came over me. DaveArticle: 51181
"Chen Wei Tseng" <chenwei.tseng@xilinx.com> a écrit dans le message news: 3E14A64A.4B28F4B0@xilinx.com... > Jeff, > > Please add user options to the .UDO file that HDL bencher wrote out. Sorry, I don't understand what you say. Could you explain it in detail? I have not found which programm uses .UDO file. Thanks > > Regards, Wei >Article: 51182
I'm trying to get a board working that has a XC5202 and an 80188 variant chip working together in asynchronous perhipheral mode. Just a single chip, no chains. I've taken the .bit file, and after skipping the header am literally pushing the bytes direct to the XC5202, and it all goes OK up till about byte 51 (its always at the same place, but I'm not at the bench at the mo, and the memory has faded a little), whereupon the /INIT pin drops, indicating a framing error. The same bitstream, if fed serially by the same processor to the same XC5202, works just fine. I've read xapp090 many times and done just about everything in there, except put a logic analyser on DOUT (LA is U/S _again_); however, putting a counter on there and running the first few bytes in slow gives the right number of transitions, so I think that DOUT is correct, but am not absolutely certain at this time. Certainly, I'm getting the right number of CCLK pulses to match the number of bytes sent. The timing diagrams for the processor seem to be acceptable to the Xilinx timing diagrams. So I'm wondering if there is a something I dont know here; is there something I need to do to the bitstream to make it acceptable in parallel mode? I've not got as far as worryiong about extra writes at the end yet (for the length count feature), as it breaking down early on. Has anybody got some advice? Thanks in advance.Article: 51183
when I use altera's epc2 chip to download my program,but byteblaster cann't identify the epc2!Article: 51184
Peter Alfke wrote: > > rickman wrote: > > > I understand the simplicity. I was not suggesting that you tristate the > > output. I was suggesting that you use a control to switch the > > resistance between the input and output. If you don't change the > > resistance you have a poor compromise for the resistor value. > > > > As I said in the other post, the series resistance is set to a value > > equal to the trace impedance minus the output impedance of the driver. > > A parallel impedance is set equal to the trace impedance. Unless your > > output driver has an inherent output impedance that is near zero, the > > method you suggest will result in a poor match to one, the other or both > > resistors. > > Rick, I have to correct you: > When you use DCI (digitally controlled impedance), the output impedance is exactly > the way you program it. It is NOT the sum of two impedances or resistors. The output > transistor ( the one pulling High as well as the other one pulling Low) are > controlled to each have the appropriate resistance (whenever each one is activated), > and the user should make that equal to the characteristic impedance of the line. > Now you see that we have perfect series termination, and also perfect parallel > termination. > The beauty of a servo-controlled internally-defined output impedance... :-) > > Peter Alfke, Xilinx Applications Yes, I see what you are saying. My mistake. I was ignoring the impedance of the output transistor in the parallel termination as if the resistor were directly to ground. Since the series termination is selected to match the total output impedance to the trace, the parallel impedance would be the same match to the trace impedance. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 51185
Under which OS? Mine works fine under WinXP. Maybe try mk_custom_sdk in bash shell. Matjaz "Peter Wtorek" <umwtorek@cc.umanitoba.ca> wrote in message news:au8mu4$hhm$2@canopus.cc.umanitoba.ca... > Hello, > > Having a small problem when generating a SOPC core using the SOPC > Builder application. > > After I press "Generate", the system begins building the binary files. > It runs into a problem when running the "nios-convert" application. > The following errors are generated: > > # 2002.12.23 21:13:53 (*) cd d:/quartus/testproj ; nios-convert > --outfile=nios_dev_board_flash_0_contents.srec --address_low=16384 > --address_high=32768 > Can't locate strict.pm in @INC (@INC contains: > /cygdrive/d/altera/excalibur/sopc_builder_2_5/bin/perl_lib:/cygdrive/d/alter a/excalibur/sopc_builder_2_5/bin/europa:/cygdrive/d/altera/excalibur/sopc_bu ilder_2_5/bin: > .) at - line 3. > BEGIN failed--compilation aborted at - line 3. > # mk_custom_sdk: WARNING 512 cd d:/quartus/testproj ; nios-convert > --outfile=nios_dev_board_flash_0_contents.srec --address_low=16384 > --address_high=32768 > ERROR: Could not build Peripheral Contents for nios_0 > > Error in processing. System NOT successfully generated. > > As you can see, the perl interpreter cannot find strict.pm, although it > is indeed located within: > > /cygdrive/d/altera/excalibur/sopc_builder_2_5/bin/perl_lib > > So the @INC array is correct, but it cannot find the proper perl > module. Any help here? Thanks. >Article: 51186
123 wrote: > when I use altera's epc2 chip to download my program,but > byteblaster cann't identify the epc2! You have to do 'multidevice JTAG chain' configuration and then 'detect configuration' If have an FPGA and an EPC2, the sequence matters. What FPGA is there too ? According to what picture did you do the configuration ? Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 51187
Hi. A few years ago lots of people seemed to want to 'go contracting' and make piles of the good stuff, but fewer people seem to want to now. I hear that this is because of some change in the tax laws. Could anyone explain this to me, please? Also - what would an individual have to do to set himself up as a contractor? Thanks in advance!Article: 51188
There was a recent change (IR35) to catch people who were effectively being employed by a single company, but are trading as a one-man limited company for tax reasons. I believe this only affects people working mostly on-site for a single company, and using that company's equipment etc. If you want to set up as a freelance designer/developer, using your own equipment/premises, this does not affect you. To set yourself up, there is not a great deal you need to do in terms of legal stuff etc.- you need to decide whether to be a sole trader or limited company, and as your customers will be other companies you should get VAT registered, as you will then be able to claim back VAT spent on equipment etc., and it will cost your customers no more as they can claim it back. I'd suggest using a trading name that does not suggest you are a one-man band - "Widget projects" is probably better than "Fred Bloggs consultancy". This can be useful when dealing with suppliers, getting samples etc. Although you are probably specifying parts to be used in production, you are not the person buying, which is what distributors are interested in! On Mon, 6 Jan 2003 11:10:15 -0000, "Brendan Lynskey" <brendan@comodogroup.com> wrote: >Hi. > >A few years ago lots of people seemed to want to 'go contracting' and make >piles of the good stuff, but fewer people seem to want to now. > >I hear that this is because of some change in the tax laws. Could anyone >explain this to me, please? > >Also - what would an individual have to do to set himself up as a >contractor? > >Thanks in advance! >Article: 51189
"Thomas Kurth" <thomas.nospam@gmx.de> wrote in message
news:MPG.187f6d7072fbd7d5989683@news.cis.dfn.de...
> Heyho Andy,
>
> I've read all the thread (since now) and think it is a good option to tie
> them to GND. But it maybe useful to tie some of them via a resistor
> (might even be 0 Ohm) to GND. Like that you have the possibility to
> connect easily any testsignals or signals that you forgot in your layout.
> Just take the resistor of and you get another accessible IOO of your
> FPGA. I always do this, it makes debugging more easy. Just think about
> putting an internal signal on the pin in order to analyze it... It helped
> me often...
The good point is a testpoint. You can leave them open, and if you don't
need them anymore, use them as output to ground or Vcc so they will not
float.
>
> I wish you all a happy, successful and healthy new year! ("Happy new
> year, Miss Sophy" for those who know "Dinner for one" :o) )
>
> Be readin' ya,
>
> Thomas
>
> --
>
> No matter if you are going on-piste or off-piste just hit the slope and
> stay healthy!
>
> For email-reply replace "nospam" with "kurth".
Article: 51190
Hi Prashant,
In your 'Code A' you should include 'C' in the sensitivity
list of the process statement. Otherwise, 'B' will only be updated on
rising edges of 'A', I believe.
I've found that this sort of code often gives different
results between synyhesis and simulation, so be careful!
cheers, Symsx.
prashantj@usa.net (Prashant) wrote in message news:<ea62e09.0301021035.77494be8@posting.google.com>...
> Hi all,
>
> I read an article recently which mentioned that an inference of a
> latch due to an incomplete IF statement is an asynchronous piece of
> code. I agree with that. But if I had this piece of code within a
> process which triggers @ the rising edge of a clk, would it still be
> considered async ? I would think not.
>
> for e.g.
> ----------------------------------------------------
> Code A
>
> process(A)
> begin
> if (A = 1) then
> B <= C;
> end if;
> end process;
> ----------------------------------------------------
>
> ----------------------------------------------------
> Code B
>
> process(clk)
> begin
> if clk'EVENT and clk = '1' then
> if (A = 1) then
> B <= C;
> end if;
> end if;
> end process;
> ----------------------------------------------------
>
> I would assume Code B to be synchronous, while code A is async. Am I
> correct ?
>
> Thanks,
> Prashant
Article: 51191Mike Harrison <mike@whitewing.co.uk> wrote in message news:aipi1vc3706s8ce33o560omudhbub07def@4ax.com... > There was a recent change (IR35) to catch people who were effectively being employed by a single > company, but are trading as a one-man limited company for tax reasons. I believe this only affects > people working mostly on-site for a single company, and using that company's equipment etc. This affected most people contracting. Someone with a series of 6 or 7 contracts with different companies throughout a year could still be caught by IR35. See http://www.pcg.org.uk/index.html -> Issues -> IR35 for more details. The PCG is worth joining if you do end up contracting. > If you want to set up as a freelance designer/developer, using your own equipment/premises, this > does not affect you. > > To set yourself up, there is not a great deal you need to do in terms of legal stuff etc.- you need > to decide whether to be a sole trader or limited company, Many clients prefer to work with a Limited Company. This isn't hard to set up, you can buy one off the shelf or start one yourself, most accountants will be able to help you with this. You'll need to find yourself an accountant to prepare your end of year accounts etc. If you're setting a company up from scratch see... http://www.companies-house.gov.uk/ -> Company Information to check any name you want to use. > and as your customers will be other > companies you should get VAT registered, as you will then be able to claim back VAT spent on > equipment etc., and it will cost your customers no more as they can claim it back. There's a threshold of ~£55K over which you have to register for VAT, but as Mike said it's worth doing anyway (it's free and there's not much paperwork). One thing to beware is that the contracting market (IT especially) in the UK is currently at a very low ebb. I would research your market and make sure there's work about before you jump. If you're able/willing to work in Europe things are currently a bit brighter. Nial Stewart. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewart.co.ukArticle: 51192
Hello,
I have a synchronous system, but there is a parameter that comes (n bits
long) that comes from external world. This value is stored int input buffer
(register). The master device that provides this value also provides a
strobe signal for the register. I don't know whether this STOBE signal
should be LATCH (active high) or FF (load a value on L2H trasition). I have
another question. Is there any problem when data is being stored into
register and read simultaneously? This should lead to inconsistent state
when some of the bits read from the register are updated while others still
arn't. Which is a standard way to synchronise data load? Asynchronous
handshking?
_______ ____________________
| | | |
VALUE ==+ REG | | System with clock|
| +--->| |
STROBE --+ | | |
|_______| | |
| |
|____________________|
Article: 51193> BP 1200 (5V devices): $1495 The 1200 can ONLY program 5V devices? I don't believe that's true... Here are the pin driver specs from their web site: Analog & Digital: 84, located on 6 circuit boards Digital: up to 36, located in small chassis on top of BP-1200 Voltage: 0 to 25.00V, 25mV steps Current: 0-1A, 12mA resolution Slew rate: 0.001 to 2500V/ms Timing: 1ms - 1s, +1ms, +0.01% Clocks: 1MHz to 16 MHz, any pin Protection: overcurrent shutdown, power failure shutdown Independence: each analog pin may be set to a different voltage And it says the voltage is 0-25V, so I'd believe from that it can program ANY voltage between those voltages...and if it only programmed 5V devices, I'd be a bit upset given the spec seems to say differently. AustinArticle: 51194
Hi all, in order to reduce the product cost I design a configuration solution using master serial mode for a spartan-II(E) fpga with a serial data flash from either ATMEL or from SST. It doesn't matter. The only thing that is needed is a 74LV165 for the command byte enabling READ ARRAY MODE for the SPI device and two or threee Tiny Logic buffer's. However, since the serial data flash is reprogrammable I'am looking for a ISP SPI programming solution through the parallel port of a PC. Has anybody of you allready made this minimum of software to program the SPI in circuit? markusArticle: 51195
Hello all, I have some combinatorial logic that I want to constrain in a Xilinx device to minimize the propagation delay end to end. I tried this: NET "S(1)" TNM_NET = "group1"; NET "S(6)" TNM_NET = "group2"; TIMESPEC "TScarry" = FROM "group1" TO "group2" 6 ns; and XST complains it cannot find the nets S(1) and S(6). Is this the proper way to do it? I went into the floor planner and poked around and figured out that my net names are changed by the tool, as they are not in the design at all. I tried the Keep constraint, to try and coerce the tool into keeping my name, and it still complains. So, the bottom line questions: Is this the correct approach? How do I determine correctly what names my nets have been given? ClydeArticle: 51196
"Austin Franklin" <austin@da98rkroom.com> wrote in message news:v1j7ltgh2ekqd3@corp.supernews.com... > > BP 1200 (5V devices): $1495 > > The 1200 can ONLY program 5V devices? I don't believe that's true... > > Here are the pin driver specs from their web site: > > Analog & Digital: 84, located on 6 circuit boards > Digital: up to 36, located in small chassis on top of BP-1200 > Voltage: 0 to 25.00V, 25mV steps > Current: 0-1A, 12mA resolution > Slew rate: 0.001 to 2500V/ms > Timing: 1ms - 1s, +1ms, +0.01% > Clocks: 1MHz to 16 MHz, any pin > Protection: overcurrent shutdown, power failure shutdown > Independence: each analog pin may be set to a different voltage > > > And it says the voltage is 0-25V, so I'd believe from that it can program > ANY voltage between those voltages...and if it only programmed 5V devices, > I'd be a bit upset given the spec seems to say differently. > > Austin I sit corrected! They NOW claim they ONLY support 5V devices with this product (BP-1200), though their web site does NOT say this. They say "support TO 5V', and "Voltage 0 to 25V" and "Supports virtually every device available". I bought my BP-1200 years ago with the understanding that it was a UNIVERSAL programmer, and it DID support 3.3V devices at one time...but they now claim they don't support them any more. I'm pissed. I can understand it not supporting 1.5V devices with the BP-1200, as it is an older unit, and possibly even 2.5V devices, but not supporting 3.3V devices, especially since it DID support them at one time seems wrong. I have to say I have been VERY happy with the programmer, and their support, though they were REALLY slow coming out with the Windows driver. I will contact them and see what my options are. This thing cost me something like $5k when I bought it, with the 84PLCC adapter...and I'm not happy they are removing support for 3.3V devices so I have to now spend more money to get support for them...when I though I already HAD support for them. AustinArticle: 51197
Some tools do not like to see literals in port maps. I've gotten around this problem in the past by adding a couple of signals, calling them logic0 and logic1, and assigning them values of '0' and '1' respectively. If you place these two signal assignments before your component mapping, you can then use the signals in your port maps instead of the literals '0' and '1'. Hope this helps. JoeArticle: 51198
see http://support.xilinx.com/support/techxclusives/MovingData-techX16.htm Peter Alfke valentin tihomirov wrote: > Hello, > I have a synchronous system, but there is a parameter that comes (n bits > long) that comes from external world. This value is stored int input buffer > (register). The master device that provides this value also provides a > strobe signal for the register. I don't know whether this STOBE signal > should be LATCH (active high) or FF (load a value on L2H trasition). I have > another question. Is there any problem when data is being stored into > register and read simultaneously? This should lead to inconsistent state > when some of the bits read from the register are updated while others still > arn't. Which is a standard way to synchronise data load? Asynchronous > handshking? > > _______ ____________________ > | | | | > VALUE ==+ REG | | System with clock| > | +--->| | > STROBE --+ | | | > |_______| | | > | | > |____________________|Article: 51199
Brendan Lynskey wrote: > Hi. > > A few years ago lots of people seemed to want to 'go contracting' and make > piles of the good stuff, but fewer people seem to want to now. I heard that this was because of the recession. I was told by someone from a recruitment agency that deals with both contractors and permanent staff that this is a really bad time to be a contractor. One explanation is that companies will only lay-off permanent staff when they have to because of the cost and potential legal repercussions. Contract staff are easier to get rid of because there is no promise to maintain employment in the first place. Therefore, when a company is short of cash, the first jobs to go are the contract jobs. Andy -- Andy Rushton, Research Fellow, ECS Department, Southampton University address: rm 3053, Mountbatten Building (53) phone: 023 8059 6665 http://www.ecs.soton.ac.uk/~ajr1
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