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"Peter Ormsby" <faepetedeletethis@mediaone.net> wrote in message news:Scp57.2161$X6.230331@typhoon.mn.mediaone.net... > Jon, > > Speaking from my experience of designing (commercial) avionics for several > years (although not in the last three or so), here's what I know about FPGAs > and the FAA and airframe manufacturers. > > The FAA doesn't like FPGAs in level A or even level B avionics boxes. Actel > does a great bit of their business in these types of products because their > OTP anti-fuse parts are not susceptable to SEU (Single Event Upsets - > high-energy cosmic particles that can cause an SRAM memory or configuration > cell to switch states). Redundancy and run-time testing can address some of > the concerns, but all-in-all, the FAA and Boeing and Airbus and the many > Regional/Business airframe mfgrs are uncomfortable with FPGAs in > flight-critical applications. > Fortunately we are only safety involved, and mission rather than flight critical. > Xilinx has it's Q-PRO parts which are only good in cost-is-no-issue designs > (they're mighty expensive). Altera has a Hardcopy solution that takes your > FPGA design and converts it into a ASIC-like solution that is non-SEU > susceptable, but you need to buy 5000 or more (depending on size) and pay an > NRE in the $100,000 - $200,000 range. > I suspect that if the going get's tough Actel may see some more buisness !! > I know of no flight-critical box that has been certified on a commercial, > regional, or business aircraft with an FPGA's reliability guarenteed by > reading-back the configuration. My experience is only with one of the two > big US avionics mfgrs and one of the tier-two mfgrs, but I would be very > interested in hearing of a counter-example (for non-military, commercial > projects). Maybe someone currently at Honeywell or Rockwell Collins would > have some info on the latest thoughts on this subject. > > -Pete- > JonArticle: 33201
Why would you want to use anything else than the JTAG port. On the http://www.jamisp.com/ website there is lots of documentation and sample C code on how to program MAX devices through the JTAG port using embedded processors. It is very well documented and STAPL (Standard Test And Programming Language) is a JEDEC standard. It is also possible to program MAX devices in a prallel mode through several of it's I/O pins. The specification for this however is only available to programming hardware manufacturers and anyway not suitable for in-system programming with an embedded processor. You would need to control many I/O pins simultaneously and isolate them from the rest of your design during programming. Furthermore there's no siginificant difference in programming time. The limiting factor is the programming pulse and it doesn't make a big difference whether you shift in serial data through the JTAG port or apply them in parallel through I/O pins. When using the JTAG port for both programming and board level testing you just need to come up with a solution so that you can control the complete JTAG chain from both your embedded processor and you test hardware. Regards Wolfgang http://www.elca.de Dionissis Efstathiou <eyden@mhl.tuc.gr> wrote in message news:3b557fdb.0@ermis... > Hi everyone, > > I was wondering if anyone can tell me how a MAX device > can be programmed apart from using JTAG. I know that we can do show > with the bitblaster (or byteblaster) but the thing is that while the > bitblaster > has 2 configuration modes (Passive Serial - JTAG) it only uses JTAG in order > to program MAX devices. > > I'm trying to program a MAX device (not one in specific) via > an embeded processor WITHOUT using the JTAG port. > > Thanks in advance > Dionysis. > >Article: 33202
If I were in your position, my first move would be to troubleshoot and correct the LVDS signal at the end of the cable. Are there any stubs in the transmission lines? Are there horrible impedance mismatches? Are the differential pairs routed side-by-side corrrectly? Is the LVDS source able to source enough current to match the end termination? Is the LVDS pair single-sourced or multiple-sourced? Does the end termination match the transmission line impedance (typically 100-120 ohms for twisted pair or ribbon cable), etc. etc. Doin't accept anecdotal "evidence" of signal problems. If you are responsible for receiving the signals, you need to see first-hand what the signal condition is. If the signal is "disturbed", any quick fix is likely to fail when the signal becomes (inevitably) slightly *more* disturbed. It si very difficult to design an interface for a system that can't be considered "stable". You need to understand what the signal conditions are (and why), so you understand how much (and how little) the system is likely to vary from board to board, from moment to moment, etc. Bob Elkind, the e-team fpga/design consulting. "Stéphane" wrote: > Hi, > > I have to interface an 30 meters cable which is a simple cable. > It is used to transfert video data from a CCD, it is LVDS, the max rate is > 40 Mhz. > I have to design the reception card, which is in fact the real time video > treatment card. > I have an Apex 400EFC672-2x on it, so I'd like to use it to acquire the data > directly from the cable. > > The fact is that signal at my side of the cable are very perturbed, I don't > know exactly what they look like but I was told there is a lot of, skew, > jitter, and voltages are disturbed. The clock is also transmitted on the > cable in LVDS protocol and I have to get the FPGA's clock out of it. > > My question is : > Are the APEX's LVDS I/O directly compatible with such signals ? > The main problem is the common mode which seems to be to small. > > Does anyone has already done such a thing ? > > Thanks. > > Stephane.Article: 33203
OK, here's another volley... Ray Andraka wrote: > bob elkind wrote: > > > Hmmm, are you saying Altera doesn't have decent support also? > > I've dealt with support from both, and I can honestly say (And if you search > the archives, you'll find I've said it before) that Xilinx's support, while > not perfect, sets a standard the others should strive to achieve. I can't say > the same for Altera's. I don't know how often Ray has needed Altera's support vs. Xilinx's support. Or how familiar Ray is with Altera's products vs. Xilinx's products. I admit that (in the last 4 years) I've been designing primarily with Altera devices. I don't have a lot of recent experience with Xilinx's tech support. I have two observations: 1. I don't *need* Altera tech support very often. You can take this statement any way you care to. 2. When I have needed Altera tech support, one of two scenarios take place: 2.a The information I need is readily available in 3 minutes or less (including hold time) or... 2.b The "answer" is *not* readily available, the tech support guy (includes females) suggests I email in the design files, I say "thank you", and then I find the stupid coding mistake within the next 20 minutes. I feel like a stupid ass sometimes, but that's something I have to learn to deal with. You would have to read Austin's original post to understand why I am defending Altera's tech support (rather than smearing anyone else's tech support). Bottom line is (in all likelihood) both Altera and Xilinx have pretty good tech support, *WAY* better than Microsoft (can we agree on this?!). > > > Not just the > > > features (although again, I feel we are now three generations ahead > > > there, too). > > > > Neither the 2XCS30 nor the 1K30 are the "feature rich" glam parts. > > These are the cost/performance devices for both companies. > > The XC2S30 has all the features of the virtex device, including clock DLLs and > memory. Compared to VirtexE, it's major differences are that it is missing > the extra i/o standards, has 4 instead of 8 DLLs, and has a limited selection > of packages. It is also faster than the slowest speed grade virtex part. Not > too shabby for not being the "feature rich glam part". Again, go to Austin's posting to understand my statement in context. The original poster probably doesn't need or want the devices that makes Austin say (on Xilinx's behalf) "...we are now three generations ahead...". Here is what I mean by the "feature rich glam devices": X company: http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?BV_SessionID=@@@@1695245710.0995533998@@@@&BV_EngineID=cccdaclmhmifghlcflgcefndfgldfmh.0&ioid=-8265&isoid=-8901&itype=2&iLanguageID=1&iCountryID=1&sSecondaryNavPick=Devices&sGlobalNavPick=PRODUCTS (this is a whompin long URL, but it refers to Virtex II overview page) A company: http://www.altera.com/products/devices/mercury/mcy-index.html (Mercury family) http://www.altera.com/products/devices/excalibur/exc-index.html (Excalibur embedded [ARM | NIOS | MIPS] processor http://www.altera.com/products/devices/apex/apx-index.html (Apex 20Kx family) Compared to any of these, the 2XCS30 and 1K30 are, most definitely, the price-conscious product line offerings of the X and A companies. No LVDS, no CAMs, no embedded processors, no quad port RAMs, etc. etc. When you're shopping for a Dodge or a Chevy sedan, how much weight do you want to give to a guy in a plaid jacket talking about how much the Cadillac SouthStar or the Ram Turbo Magnum or the Corvette Super Hemi GPS technologies compel you to buy a Dodge vs. Chevy? [note: all these terms are purely pulled out of thin air, and apologies to auto industry professional wearing anything polyester or plaid]. > > Barring a teeny design, I would tend to ignore the schematic option. > > AHDL is *so* easy to use, any advantage schematic entry may have > > is quickly overcome by the efficiencies of HDL editing (specifically > > AHDL). > > If someone is trying to learn how to design in FPGAs, I _strongly_ encourage > them to do their first few designs in schematics. This forces them closer to > the underlying architecture, and there is less temptation to code it like > software. Once you learn how to design to the FPGA, then learn the HDL and > figure out how to make it produce the hardware you envision. HDLs give you > alot of power for parameterizing code, simulation and archiving, but they also > make it very easy to abstract yourself into one of those "feature rich glam > parts" where one of the cheap low end ones would have done fine. For a one > time project, it also avoids learning both FPGA design and HDLs at the same > time. AHDL design language gets you pretty close to the the low level of the device technology, maintains pretty good "power", and avoids 90% of the frustration level of VHDL. Don't forget, schematic libraries can be a minor tar baby unto themselves. For a newbie, AHDL is a really good starting point. I'd steer my own offspring into AHDL first, to build confidence, before suggesting they tackle VHDL on their first design. And I still think schematics are (more or less) a dead end, with AHDL being a better alternative.. > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com Ray has a lot of FPGA designs behind him. I have a fair number of FPGA designs on my hard drive, as well. What should be clear to the casual observer is that there are often many different and entirely reasonable approaches/path to solve the same (or similar) problem. Reasonable and experienced designers often choose different approaches and/or design tools. What's important is that you can find at least one path or solution that you can depend on to work for you. Hopefully, the X vs. A religion war hasn't overtaken this thread; and through all the assertions that have been made, some useful information has been conveyed. -- Bob Elkind, the e-team FPGA/design consultingArticle: 33204
Hi, I have a little problem which I hope someone may be able to solve. I'm passing a complex signal through an FIR and FIR+HILBERT low pass filter, and want to take the 4MSB of the 17/18bit, bipolar (DC=0) output (actually, the filter output only ever uses 15 bits incl. sign bit, so I discard the top padded sign bits). Now, the problem is, when you take the 4MSB of a positive value, the modulus of the maximum value you get will be less than that of a negative value. If you consider a signal hovering about 0. Whenever it goes above 0, the 4MSB give you zero. When it goes below, you get -1. This has caused me to get a DC offset of 0.5 in my signal. Can anyone suggest a solution. All I am doing to get my 4MSB is to take the four relevant output lines from the filter output bus. Thanks (in advance) AdrianArticle: 33205
SAF wrote: > > Thant's absolutely mad. I checked the prices on Amazon, BooksaMillion > and BarnesandNoble, and they're all too high. If you want, try > ordering them from Amazon.co.uk (www.amazon.co.uk), the price there is > close to what I got them for. Thanks for the tip! > > Never thought I'd see the day where something was cheaper here than in > the US! :) > > Gonzalo Arana <gonzaloa@sinectis.com.ar> wrote in message news:<3B538661.B1F956@sinectis.com.ar>... > > Hi, > > > > SAF wrote: > > > > > > OK, > > > > > > After spending 3 hours in the biggest bookshops in town (the > > > world-famous Foyles, Waterstones and some new joint), I managed to > > > find the following two titles, which I bought: > > > > > > Yalamanchili, Sudhakar (2001) "Introductory VHDL: From Simulation to > > > Synthesis" includes Xilinx Student Edition 2.1i - Only £25! (about > > > $37) It seems a pretty good book too. > > > > Is it this one (ISBN: 0130809829)? > > http://www.amazon.com/exec/obidos/tg/stores/detail/-/books/0130809829/contents/ref=pm_dp_ln_b_2/104-5678861-7531964 > > > > > > > > Zwolinski, Mark (1997) "Digital System Design with VHDL" - £30 (about > > > $45) Good because it stradles the digital systems and VHDL borders, > > > explaining both. > > > > Is it this book (ISBN: 0201360632)? > > http://www.amazon.com/exec/obidos/tg/stores/detail/-/books/0201360632/contents/ref=pm_dp_ln_b_2/104-5678861-7531964 > > > > > > > > > You got them really cheap! > > Good for you!Article: 33206
Hi all, I've got an AHDL state machine thing that reads a word from a lpm_ram_dq, adds or subtracts an increment, and stores the result back. However, it won't work, like the ram just stays full of zeros. Is there any way to see the 'previous' ram location in the waveform editor or simulation? --RussellArticle: 33207
--------------067F8BDFF66FC8AE378E1D48 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit I don't usually call tech support until I have built enough of a case so as to not waste their time with stupid mistakes and I have checked the on-line answers for similar queries. As a result, my calls are usually on something that has broken the tool, or to report a bug in part of the tool that most users don't use. Both are good (much better than software companies, including some of the EDA tools companies), both still have room for improvement, but I have usually gotten a better response from Xilinx. There is something to be said for making a phone call in response to an email support request, even if it is just to say "we got your email, and we don't have a solution yet". Altera has greatly improved their on-line knowledge base from non-existent to a useful resource. Xilinx's on-line base has gotten big enough to be a little unwieldy when searching for a common term, which can make it hard to find the information you are looking for sometimes. I will admit that I have done more Xilinx than Altera as of late, mostly because of the better expert control over the implementation and the chip features that favor DSP. bob elkind wrote: > OK, here's another volley... > > Ray Andraka wrote: > > > bob elkind wrote: > > > > > Hmmm, are you saying Altera doesn't have decent support also? > > > > I've dealt with support from both, and I can honestly say (And if you search > > the archives, you'll find I've said it before) that Xilinx's support, while > > not perfect, sets a standard the others should strive to achieve. I can't say > > the same for Altera's. > > I don't know how often Ray has needed Altera's support vs. Xilinx's support. > Or how familiar Ray is with Altera's products vs. Xilinx's products. > I admit that (in the last 4 years) I've been designing primarily with Altera > devices. I don't have a lot of recent experience with Xilinx's tech support. > > I have two observations: > > 1. I don't *need* Altera tech support very often. You can take this statement > any way you care to. > > 2. When I have needed Altera tech support, one of two scenarios take place: > > 2.a The information I need is readily available in 3 minutes or less (including > hold time) or... > > 2.b The "answer" is *not* readily available, the tech support guy (includes > females) suggests I email in the design files, I say "thank you", and then I > find the stupid coding mistake within the next 20 minutes. I feel like a stupid > ass sometimes, but that's something I have to learn to deal with. > > You would have to read Austin's original post to understand why I am > defending Altera's tech support (rather than smearing anyone else's tech > support). Bottom line is (in all likelihood) both Altera and Xilinx have pretty > good tech support, *WAY* better than Microsoft (can we agree on this?!). > > > > > Not just the > > > > features (although again, I feel we are now three generations ahead > > > > there, too). > > > > > > Neither the 2XCS30 nor the 1K30 are the "feature rich" glam parts. > > > These are the cost/performance devices for both companies. > > > > The XC2S30 has all the features of the virtex device, including clock DLLs and > > memory. Compared to VirtexE, it's major differences are that it is missing > > the extra i/o standards, has 4 instead of 8 DLLs, and has a limited selection > > of packages. It is also faster than the slowest speed grade virtex part. Not > > too shabby for not being the "feature rich glam part". > > Again, go to Austin's posting to understand my statement in context. > The original poster probably doesn't need or want the devices that makes > Austin say (on Xilinx's behalf) "...we are now three generations ahead...". > > Here is what I mean by the "feature rich glam devices": > > X company: > http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?BV_SessionID=@@@@1695245710.0995533998@@@@&BV_EngineID=cccdaclmhmifghlcflgcefndfgldfmh.0&ioid=-8265&isoid=-8901&itype=2&iLanguageID=1&iCountryID=1&sSecondaryNavPick=Devices&s > (this is a whompin long URL, but it refers to Virtex II overview page) > > A company: > http://www.altera.com/products/devices/mercury/mcy-index.html (Mercury family) > http://www.altera.com/products/devices/excalibur/exc-index.html (Excalibur embedded [ARM | NIOS | MIPS] processor > http://www.altera.com/products/devices/apex/apx-index.html (Apex 20Kx family) > > Compared to any of these, the 2XCS30 and 1K30 are, most definitely, the > price-conscious product line offerings of the X and A companies. No LVDS, > no CAMs, no embedded processors, no quad port RAMs, etc. etc. > > When you're shopping for a Dodge or a Chevy sedan, how much weight do you > want to give to a guy in a plaid jacket talking about how much the Cadillac > SouthStar or the Ram Turbo Magnum or the Corvette Super Hemi GPS > technologies compel you to buy a Dodge vs. Chevy? [note: all these terms > are purely pulled out of thin air, and apologies to auto industry professional > wearing anything polyester or plaid]. > > > > Barring a teeny design, I would tend to ignore the schematic option. > > > AHDL is *so* easy to use, any advantage schematic entry may have > > > is quickly overcome by the efficiencies of HDL editing (specifically > > > AHDL). > > > > If someone is trying to learn how to design in FPGAs, I _strongly_ encourage > > them to do their first few designs in schematics. This forces them closer to > > the underlying architecture, and there is less temptation to code it like > > software. Once you learn how to design to the FPGA, then learn the HDL and > > figure out how to make it produce the hardware you envision. HDLs give you > > alot of power for parameterizing code, simulation and archiving, but they also > > make it very easy to abstract yourself into one of those "feature rich glam > > parts" where one of the cheap low end ones would have done fine. For a one > > time project, it also avoids learning both FPGA design and HDLs at the same > > time. > > AHDL design language gets you pretty close to the the low level of the device > technology, maintains pretty good "power", and avoids 90% of the frustration > level of VHDL. Don't forget, schematic libraries can be a minor tar baby unto > themselves. For a newbie, AHDL is a really good starting point. I'd steer my > own offspring into AHDL first, to build confidence, before suggesting they > tackle VHDL on their first design. And I still think schematics are (more or > less) a dead end, with AHDL being a better alternative.. > > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > Ray has a lot of FPGA designs behind him. > > I have a fair number of FPGA designs on my hard drive, as well. > > What should be clear to the casual observer is that there are often many > different and entirely reasonable approaches/path to solve the same (or > similar) problem. Reasonable and experienced designers often choose different > approaches and/or design tools. What's important is that you can find at least > one path or solution that you can depend on to work for you. > > Hopefully, the X vs. A religion war hasn't overtaken this thread; and through > all the assertions that have been made, some useful information has been > conveyed. > > -- Bob Elkind, the e-team FPGA/design consulting -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com --------------067F8BDFF66FC8AE378E1D48 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> I don't usually call tech support until I have built enough of a case so as to not waste their time with stupid mistakes and I have checked the on-line answers for similar queries. As a result, my calls are usually on something that has broken the tool, or to report a bug in part of the tool that most users don't use. Both are good (much better than software companies, including some of the EDA tools companies), both still have room for improvement, but I have usually gotten a better response from Xilinx. There is something to be said for making a phone call in response to an email support request, even if it is just to say "we got your email, and we don't have a solution yet". Altera has greatly improved their on-line knowledge base from non-existent to a useful resource. Xilinx's on-line base has gotten big enough to be a little unwieldy when searching for a common term, which can make it hard to find the information you are looking for sometimes. I will admit that I have done more Xilinx than Altera as of late, mostly because of the better expert control over the implementation and the chip features that favor DSP. <br> <p>bob elkind wrote: <blockquote TYPE=CITE>OK, here's another volley... <p>Ray Andraka wrote: <p>> bob elkind wrote: <br>> <br>> > Hmmm, are you saying Altera doesn't have decent support also? <br>> <br>> I've dealt with support from both, and I can honestly say (And if you search <br>> the archives, you'll find I've said it before) that Xilinx's support, while <br>> not perfect, sets a standard the others should strive to achieve. I can't say <br>> the same for Altera's. <p>I don't know how often Ray has needed Altera's support vs. Xilinx's support. <br>Or how familiar Ray is with Altera's products vs. Xilinx's products. <br>I admit that (in the last 4 years) I've been designing primarily with Altera <br>devices. I don't have a lot of recent experience with Xilinx's tech support. <p>I have two observations: <p>1. I don't *need* Altera tech support very often. You can take this statement <br>any way you care to. <p>2. When I have needed Altera tech support, one of two scenarios take place: <p>2.a The information I need is readily available in 3 minutes or less (including <br>hold time) or... <p>2.b The "answer" is *not* readily available, the tech support guy (includes <br>females) suggests I email in the design files, I say "thank you", and then I <br>find the stupid coding mistake within the next 20 minutes. I feel like a stupid <br>ass sometimes, but that's something I have to learn to deal with. <p>You would have to read Austin's original post to understand why I am <br>defending Altera's tech support (rather than smearing anyone else's tech <br>support). Bottom line is (in all likelihood) both Altera and Xilinx have pretty <br>good tech support, *WAY* better than Microsoft (can we agree on this?!). <p>> > > Not just the <br>> > > features (although again, I feel we are now three generations ahead <br>> > > there, too). <br>> > <br>> > Neither the 2XCS30 nor the 1K30 are the "feature rich" glam parts. <br>> > These are the cost/performance devices for both companies. <br>> <br>> The XC2S30 has all the features of the virtex device, including clock DLLs and <br>> memory. Compared to VirtexE, it's major differences are that it is missing <br>> the extra i/o standards, has 4 instead of 8 DLLs, and has a limited selection <br>> of packages. It is also faster than the slowest speed grade virtex part. Not <br>> too shabby for not being the "feature rich glam part". <p>Again, go to Austin's posting to understand my statement in context. <br>The original poster probably doesn't need or want the devices that makes <br>Austin say (on Xilinx's behalf) "...we are now three generations ahead...". <p>Here is what I mean by the "feature rich glam devices": <p>X company: <br><a href="http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?BV_SessionID=@@@@1695245710.0995533998@@@@&BV_EngineID=cccdaclmhmifghlcflgcefndfgldfmh.0&ioid=-8265&isoid=-8901&itype=2&iLanguageID=1&iCountryID=1&sSecondaryNavPick=Devices&sGlobalNavPick=PRODUCTS">http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?BV_SessionID=@@@@1695245710.0995533998@@@@&BV_EngineID=cccdaclmhmifghlcflgcefndfgldfmh.0&ioid=-8265&isoid=-8901&itype=2&iLanguageID=1&iCountryID=1&sSecondaryNavPick=Devices&s</a> <br><a href="http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?BV_SessionID=@@@@1695245710.0995533998@@@@&BV_EngineID=cccdaclmhmifghlcflgcefndfgldfmh.0&ioid=-8265&isoid=-8901&itype=2&iLanguageID=1&iCountryID=1&sSecondaryNavPick=Devices&sGlobalNavPick=PRODUCTS">(this is a whompin long URL, but it refers to Virtex II overview page)</a> <p><a href="http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?BV_SessionID=@@@@1695245710.0995533998@@@@&BV_EngineID=cccdaclmhmifghlcflgcefndfgldfmh.0&ioid=-8265&isoid=-8901&itype=2&iLanguageID=1&iCountryID=1&sSecondaryNavPick=Devices&sGlobalNavPick=PRODUCTS">A company:</a> <br><a href="http://www.altera.com/products/devices/mercury/mcy-index.html">http://www.altera.com/products/devices/mercury/mcy-index.html</a> (Mercury family) <br><a href="http://www.altera.com/products/devices/excalibur/exc-index.html">http://www.altera.com/products/devices/excalibur/exc-index.html</a> (Excalibur embedded [ARM | NIOS | MIPS] processor <br><a href="http://www.altera.com/products/devices/apex/apx-index.html">http://www.altera.com/products/devices/apex/apx-index.html</a> (Apex 20Kx family) <p>Compared to any of these, the 2XCS30 and 1K30 are, most definitely, the <br>price-conscious product line offerings of the X and A companies. No LVDS, <br>no CAMs, no embedded processors, no quad port RAMs, etc. etc. <p>When you're shopping for a Dodge or a Chevy sedan, how much weight do you <br>want to give to a guy in a plaid jacket talking about how much the Cadillac <br>SouthStar or the Ram Turbo Magnum or the Corvette Super Hemi GPS <br>technologies compel you to buy a Dodge vs. Chevy? [note: all these terms <br>are purely pulled out of thin air, and apologies to auto industry professional <br>wearing anything polyester or plaid]. <p>> > Barring a teeny design, I would tend to ignore the schematic option. <br>> > AHDL is *so* easy to use, any advantage schematic entry may have <br>> > is quickly overcome by the efficiencies of HDL editing (specifically <br>> > AHDL). <br>> <br>> If someone is trying to learn how to design in FPGAs, I _strongly_ encourage <br>> them to do their first few designs in schematics. This forces them closer to <br>> the underlying architecture, and there is less temptation to code it like <br>> software. Once you learn how to design to the FPGA, then learn the HDL and <br>> figure out how to make it produce the hardware you envision. HDLs give you <br>> alot of power for parameterizing code, simulation and archiving, but they also <br>> make it very easy to abstract yourself into one of those "feature rich glam <br>> parts" where one of the cheap low end ones would have done fine. For a one <br>> time project, it also avoids learning both FPGA design and HDLs at the same <br>> time. <p>AHDL design language gets you pretty close to the the low level of the device <br>technology, maintains pretty good "power", and avoids 90% of the frustration <br>level of VHDL. Don't forget, schematic libraries can be a minor tar baby unto <br>themselves. For a newbie, AHDL is a really good starting point. I'd steer my <br>own offspring into AHDL first, to build confidence, before suggesting they <br>tackle VHDL on their first design. And I still think schematics are (more or <br>less) a dead end, with AHDL being a better alternative.. <p>> -Ray Andraka, P.E. <br>> President, the Andraka Consulting Group, Inc. <br>> 401/884-7930 Fax 401/884-7950 <br>> email ray@andraka.com <br>> <a href="http://www.andraka.com">http://www.andraka.com</a> <p>Ray has a lot of FPGA designs behind him. <p>I have a fair number of FPGA designs on my hard drive, as well. <p>What should be clear to the casual observer is that there are often many <br>different and entirely reasonable approaches/path to solve the same (or <br>similar) problem. Reasonable and experienced designers often choose different <br>approaches and/or design tools. What's important is that you can find at least <br>one path or solution that you can depend on to work for you. <p>Hopefully, the X vs. A religion war hasn't overtaken this thread; and through <br>all the assertions that have been made, some useful information has been <br>conveyed. <p>-- Bob Elkind, the e-team FPGA/design consulting</blockquote> <p>-- <br>-Ray Andraka, P.E. <br>President, the Andraka Consulting Group, Inc. <br>401/884-7930 Fax 401/884-7950 <br>email ray@andraka.com <br><A HREF="http://www.andraka.com">http://www.andraka.com</A> <br> </html> --------------067F8BDFF66FC8AE378E1D48--Article: 33208
Hong,
The DDS version 3.1 (which supports Virtex2) is available for download from the IP center on the Xilinx website, just download IP update number 4. Here's the URL for the IP center: http://www.xilinx.com/ipcenter/index.htm
Cheers,
Ciaran
Hong wrote:
> Antonio,
> We think that the DDS is not currently supported Virtex2, I might be wrong?
> While you are in the Xilinx CORE Generator Program, try this:
> Under Project option, check the "family", make sure it is not set to Virtex2? (virtex or other is fine.) DDS (Direct Digital Synthesis) Verson 2.0 should be ready to use in the Modulation Building Block. No ideas on the Virtex2? Anyone?
> Good lucks,
> Hong
Article: 33209That is a truncation error. Add the dc offset in before truncating. In otherwords, add 1/2 of your intended output LSB weight to the output before you drop the LSBs. This will greatly reduce the truncation error, but does not completely eliminate it (you get a slight bias of approximately the 1/2 the LSB before truncation) due to always rounding .5 the same way, you have to round to even at the expense of more complexity to eliminate that) Noddy wrote: > Hi, > > I have a little problem which I hope someone may be able to solve. > > I'm passing a complex signal through an FIR and FIR+HILBERT low pass filter, > and want to take the 4MSB of the 17/18bit, bipolar (DC=0) output (actually, > the filter output only ever uses 15 bits incl. sign bit, so I discard the > top padded sign bits). > > Now, the problem is, when you take the 4MSB of a positive value, the modulus > of the maximum value you get will be less than that of a negative value. If > you consider a signal hovering about 0. Whenever it goes above 0, the 4MSB > give you zero. When it goes below, you get -1. This has caused me to get a > DC offset of 0.5 in my signal. > > Can anyone suggest a solution. All I am doing to get my 4MSB is to take the > four relevant output lines from the filter output bus. > > Thanks (in advance) > Adrian -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33210
"Noddy" <g9731642@campus.ru.ac.za> wrote in message news:995542039.649648@turtle.ru.ac.za... > Hi, > > I have a little problem which I hope someone may be able to solve. > > I'm passing a complex signal through an FIR and FIR+HILBERT low pass filter, > and want to take the 4MSB of the 17/18bit, bipolar (DC=0) output (actually, > the filter output only ever uses 15 bits incl. sign bit, so I discard the > top padded sign bits). > > Now, the problem is, when you take the 4MSB of a positive value, the modulus > of the maximum value you get will be less than that of a negative value. If > you consider a signal hovering about 0. Whenever it goes above 0, the 4MSB > give you zero. When it goes below, you get -1. This has caused me to get a > DC offset of 0.5 in my signal. > > Can anyone suggest a solution. All I am doing to get my 4MSB is to take the > four relevant output lines from the filter output bus. > > Thanks (in advance) > Adrian > I'm not sure I fully understand your question. It seems like you're truncating the signal. Alternatively, you can round the signal (add 1/2 lsb before dropping the unwanted bits) or apply error feedback (delay the dropped bits by one sample period and add them into the next sample). Rounding will remove your offset. EFB will also remove the offset and "whiten" the spectrum of the resulting quantizing noise.Article: 33211
Hi, Does anyone have experience with systemC synthesis tools for FPGAs. What works best ? VivArticle: 33212
This is a multi-part message in MIME format.
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Hi,
I tried to make my own uart model. I wanted something much easier to
use than a 16550, more flexible (5, 6, 7 or 8 data bits; 1, 2 stop bits,
any baudrate, etc.), and of course, designed to be built into an FPGA.
Well, I wrote it, simulated it and (apparently) works great. When I run
it ('looping' RX with TX), I have theese strange problems:
1) When I send from a PC to the FPGA a sequence of characters
(ie: echo aaa >/dev/cua0), I read (cat /dev/cua0): aXXa.
In hexa: I send: 61 61 61 0a
I get: 61 58 58 e1
2) That kind of problem is noted when I send to the FPGA bytes whoose
LSB is 1. I tried sending one million of ascii characters, all of them
with LSB = 0, and I got NO errors.
3) I get none of theese errors when I simulate the entire entity.
I know the problem is on the receiver (uartrx.vhd), because I did sent
from the FPGA (uarttx.vhd)
a sequence of 'a' (in ascii) and it worked just as it should be.
Could someone please help me?
Any suggestions on the coding style would be welcome.
If I get this work right, I will give away this set of files for free (I
believe to opencores.org).
Thank you very much in advance,
Gonzalo Arana
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filename="testuart.vhd"
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
-- testuart
--
-- Define una entity para probar el transmisor/receptor.
-- Transmite en forma continua una letra 'a':
-- 01100001 (61)
--------------------------------------------------------------------------------
entity testuart is
Port ( clock : in std_logic;
datain: in std_logic;
reset: in std_logic;
dataout : out std_logic;
outleds: out std_logic_vector(3 downto 0);
crc_error: out std_logic);
end testuart;
architecture behavioral of testuart is
-- Test uarttx-uartrx entity.
component uart
port (
parallell_in : in std_logic_vector(7 downto 0);
parallell_in_enable : in std_logic;
parallell_in_read : out std_logic;
serial_out : out std_logic;
parallell_out : out std_logic_vector(7 downto 0);
parallell_out_enable : out std_logic;
parallell_out_read : in std_logic;
serial_in : in std_logic;
bits7 : in std_logic;
parity : in std_logic;
even : in std_logic;
stopbits : in std_logic;
clock : in std_logic;
reset : in std_logic;
estadotx : out std_logic_vector(1 downto 0);
estadorx : out std_logic_vector(1 downto 0);
crc_error : out std_logic;
byte_lost_error : out std_logic);
end component;
component divclock
port (
clock : in std_logic;
reset : in std_logic;
salida : out std_logic;
dividox : in std_logic_vector (23 downto 0);
clockenable : in std_logic);
end component;
component counter4
Port (outs: out std_logic_vector(3 downto 0);
ins: in std_logic_vector(3 downto 0);
load: in std_logic; -- sinchronous load
reset: in std_logic; -- asincrhonous reset
clk: in std_logic; -- clk
ce: in std_logic; -- clk enable
dir: in std_logic);
end component;
signal clock9600: std_logic; -- clock a 9600Hz
signal tx2rx: std_logic_vector(7 downto 0); -- del transmisor al receptor
signal tx2rx_strobe: std_logic; -- si cargo o no un valor en el contador
signal ledvalue: std_logic;
signal estadotx : std_logic_vector(1 downto 0);
signal estadorx : std_logic_vector(1 downto 0);
signal out_serial_data : std_logic_vector(7 downto 0); -- byte que voy a ir
-- sacando
signal outled1,outled2,outled3,outled4 : std_logic;
signal tx_byte_enable, tx_byte_read,
rx_byte_enable, rx_byte_read : std_logic;
signal tx_byte, rx_byte, tempbyte : std_logic_vector(7 downto 0);
signal tempbyte_enable : std_logic;
type estado_t is (IDLE, WAITTX, WAIT1);
signal state : estado_t;
signal tx_avail: std_logic;
signal byte_lost_error : std_logic;
begin
-- out_serial_data <= "10000110";
-- out_serial_data <= "01100001";
-- Loop
-- purpose: Reads the result of Rx and places it on Tx
-- type : sequential
-- inputs : clock, reset, rx_byte, rx_byte_enable, tx_byte_read
-- outputs: rx_byte_read, tx_byte, tx_byte_enable
-- purpose: Changes the state of the loop state machine
-- type : sequential
-- inputs : clock, reset, nextstate
-- outputs: state
Rx2Tx: process (clock)
begin -- process Rx2Tx
if reset = '1' then
state <= IDLE;
outleds <= x"0";
elsif clock'event and clock = '1' then -- rising clock edge
case state is
when IDLE =>
outleds <= "1110";
if rx_byte_enable = '1' then
rx_byte_read <= '1';
tx_byte <= rx_byte;
tx_byte_enable <= '1';
state <= WAITTX;
end if;
when WAITTX =>
outleds <= "1101";
if tx_byte_read = '1' then
state <= WAIT1;
rx_byte_read <= '0';
tx_byte_enable <= '0';
end if;
when WAIT1 =>
outleds <= "1011";
if rx_byte_enable = '0' then
state <= IDLE;
end if;
when others => outleds <= "0111"; state <= IDLE;
end case;
end if;
end process Rx2Tx;
--** CODIGO PARA SIMULAR
-- clock9600 <= clock;
--** CODIGO PARA SINTETIZAR
--** 50e6 / (9600 * 16) = 325.52
--** => tengo que dividir al clock de 50MHz por 326.
--** 326 - 4 = 322
--** 322 = 101000010
buildclock9600 : divclock port map (
clock => clock, salida => clock9600, reset => reset,
dividox => "000000000000000101000010", clockenable => '1');
Rs232uart : uart port map (
parallell_in => tx_byte,
parallell_in_enable => tx_byte_enable,
parallell_in_read => tx_byte_read,
serial_out => dataout,
parallell_out => rx_byte,
parallell_out_enable => rx_byte_enable,
parallell_out_read => rx_byte_read,
serial_in => datain,
bits7 => '0',
parity => '0',
even => '0',
stopbits => '0',
clock => clock9600,
reset => reset,
estadorx => estadorx,
estadotx => estadotx,
crc_error => crc_error,
byte_lost_error => byte_lost_error);
end behavioral;
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filename="uart.vhd"
--------------------------------------------------------------------------------
-- UART
-- This file describes and implements a Full Duplex RS-232 UART.
-- It uses 2 entities: uarttx (uarttx.vhd), and uartrx (uartrx.vhd)
-- This entity is designed to be used with serial pins mapped onto FPGA-pins
-- and the parallell interface to be within the FPGA.
--
-- D C E D T E
--
-- -----------------------------------------------------
-- |
-- ,-------------------------
-- parallell_in(7 downto 0) ---> | ______ TX ________\ | ---> serial_out
-- data_in_enable ---> | TX / |
-- parallell_in_read <--- | |
-- | U A R T |
-- | |
-- parallell_out(7 downto 0) <--- | /______ RX ________ | <--- serial_in
-- parallell_out_enable <--- | \ RX |
-- `-------------------------'
-- ^ ^ ^ ^ ^ |
-- | | | | | |
-- I N S I D E T H E F P G A | | | | | | O U T S I D E
-- | | | | | |
-- | | | | | | T H E
-- bits7 --------------------------' | | | | |
-- parity ----------------------------' | | | | F P G A
-- even ------------------------------' | | |
-- clock --------------------------------' | |
-- stopbits ----------------------------------' |
-- |
-- ------------------------------------------------------'
--
-- The clock signal must have a frequency 4 times greater than the bit rate.
-- bits7: '1' => each byte has 7 bits of data (6 downto 0)
-- '0' => each byte has 8 bits of data (7 downto 0)
-- parity: Parity is sent on each byte sent and expected on each byte
-- received.
-- even: This signal has meaning only if parity = '1'.
-- '1' => even parity
-- '0' => odd parity
-- Even(odd) parity:
-- The parity bit should has a value such that the entire word
-- (including this bit) has an even(odd) amount of ones.
-- stopbits: '0' -> 1 bit de stop
-- '1' -> 2 bits de stop
-- If an incoming byte fails the parity check, it is silently discarded
-- For details on implementation, refer to uart{rx,tx}.vhd
--------------------------------------------------------------------------------
-- Untested features:
-- Parity generation
-- Parity validation
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity uart is
port (
-- parallell to serial (tx)
-- inside interface (parallell)
parallell_in : in std_logic_vector(7 downto 0);
parallell_in_enable : in std_logic; -- it tells the UART that the data
-- on parallell_in are valid
parallell_in_read : out std_logic; -- parallell_in has been read
-- outside interface (serial)
serial_out : out std_logic;
-- serial to paralel (rx)
-- inside interface (paralel)
parallell_out : out std_logic_vector(7 downto 0);
parallell_out_enable : out std_logic; -- it tells the FPGA that the data
-- present in parallell_out are valid
parallell_out_read : in std_logic; -- parallell out has been read
-- outside interface (serial)
serial_in : in std_logic;
-- config signals (global to both interfaces)
bits7 : in std_logic;
parity : in std_logic;
even : in std_logic;
stopbits : in std_logic;
-- clock (global). It should be 4xbit rate
clock : in std_logic;
reset : in std_logic;
estadotx : out std_logic_vector(1 downto 0);
estadorx : out std_logic_vector(1 downto 0);
-- Errores en la recepcion
crc_error : out std_logic;
byte_lost_error : out std_logic);
end uart;
architecture behavioral of uart is
component uartrx
port (
data_in : in std_logic;
clock : in std_logic;
bits7 : in std_logic;
parity : in std_logic;
even : in std_logic;
reset : in std_logic;
data_out_enable : out std_logic;
data_out_read : in std_logic;
crc_error : out std_logic;
byte_lost_error : out std_logic;
data_out : out std_logic_vector(7 downto 0);
estado : out std_logic_vector(1 downto 0));
end component;
component uarttx
port (
data_in : in std_logic_vector(7 downto 0);
data_in_read : out std_logic;
data_out : out std_logic;
clock : in std_logic;
bits7 : in std_logic;
parity : in std_logic;
even : in std_logic;
reset : in std_logic;
stopbits : in std_logic;
data_in_enable : in std_logic;
estado : out std_logic_vector(1 downto 0));
end component;
-- senal y contador que uso para generar el clock del transmisor
signal count : std_logic_vector(3 downto 0);
component counter4
port (outs: out std_logic_vector(3 downto 0);
ins: in std_logic_vector(3 downto 0);
load: in std_logic; -- sinchronous load
reset: in std_logic; -- asincrhonous reset
clk: in std_logic; -- clock
ce: in std_logic; -- clock enable
dir: in std_logic); -- direccion 0: down 1: u
end component;
begin -- behavioral
clockdivider : counter4 port map (
outs => count,
ins => "0000",
load => '0',
reset => reset,
clk => clock,
ce => '1',
dir => '1');
tx : uarttx port map (
data_in => parallell_in, data_out => serial_out,
clock => count(3), bits7 => bits7, parity => parity,
even => even, reset => reset, stopbits => stopbits,
data_in_enable => parallell_in_enable, estado => estadotx,
data_in_read => parallell_in_read);
rx : uartrx port map (
data_in => serial_in, data_out => parallell_out(7 downto 0),
clock => clock, bits7 => bits7, parity => parity,
even => even, reset => reset, data_out_enable => parallell_out_enable,
estado => estadorx, crc_error => crc_error, data_out_read => parallell_out_read,
byte_lost_error => byte_lost_error);
End behavioral;
--------------46D7868C33BEF09E97CAA97D
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name="uartrx.vhd"
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filename="uartrx.vhd"
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
------------------------------------------------------------------------------------
-- UART RX (version 0.0):
-- Entidad que implementa la parte receptora de una UART RS-232.
-- El diagrama descriptivo que aparece a continuacion explica en forma detallada
-- como funciona (supone 7 bits de datos, sin paridad y solo se muestra un bit
-- de stop)
--
-- stt bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 stp
-- ______ _______ _______ _______ _______ _______ _______ _______ _______
-- | | | | | | | | |
-- | | | | | | | | |
-- |_______|_______|_______|_______|_______|_______|_______|_______|
--
--
-- IDLE |STTBIT
--
-- El clock suministrado debe tener una frecuencia 16 veces mayor que la de bits.
-- Ej, si estamos a 9600 bits/s (9600 baudios), clock debe ser de 76800 Hz (8 x
-- 76800).
-- Cuando termina de recibir un byte, pone el byte recibido en data_out y done en 1.
-- Cuando se termina de recibir el bit de start del proximo byte, done vuelve a 0.
-- crc_error: se puede utilizar como clock para un contador de la cantidad de errores
-- de crc.
entity uartrx is
port (
data_in : in std_logic; -- serial data in
clock : in std_logic; -- clock
bits7 : in std_logic; -- si los datos vienen en 7 bits
parity : in std_logic; -- si los datos vienen con paridad
even : in std_logic; -- si vienen con paridad par
reset : in std_logic; -- resetea el estado de la uartrx
data_out_enable : out std_logic; -- done = '1' => data_out es valido
data_out_read : in std_logic; -- data_out has been read
data_out : out std_logic_vector(7 downto 0); -- datos recibidos
crc_error : out std_logic; -- indica si hubo un error de crc
byte_lost_error : out std_logic; -- clock for a counter of overruns
estado : out std_logic_vector(1 downto 0)); -- estado que muestro afuera
end uartrx;
architecture behavioral1 of uartrx is
-- Cada bit se samplea 8 veces, pero se toma la decision del valor (0 o 1) en
-- base a 3 muestras (primera, ultima y alguna del medio).
-- Cuando toma el valor de un bit, lo pone en el shift register de salida.
-- Necesito un shift register para ir guardando los datos que voy sacando.
-- shift_register_data_out(8) tiene el ultimo bit recibido
-- shift_register_data_out(0,1,2) tiene el primer bit recibido
signal shift_register_data_out : std_logic_vector (8 downto 0);
-- Ademas, tengo que ir contando la cantidad de bits que me han llegado
signal shift_register_data_out_enable : std_logic_vector (8 downto 0);
-- Otro shift register para ir guardando las muestras
-- shift_register_samples(16) tiene la muestra mas antigua
-- shift_register_samples(0) tiene la muestra mas nueva
signal shift_register_samples : std_logic_vector (16 downto 0);
-- Otro para ver que posiciones del shift register anterior tienen datos validos.
signal shift_register_samples_enable : std_logic_vector(16 downto 0);
-- Si estoy recibiendo un byte o haciendo nada.
signal receiving_byte : std_logic;
-- De todas las muestras que tengo, de alguna forma tengo que decidir entre la
-- mejor decicion
signal bestchoice : std_logic;
-- Paridad calculada para el byte recibido.
signal pi7, pi8 : std_logic; -- paridad impar de 7/8 bits de datos
-- Si ya se leyo la salida
signal did_read_parallel_out : std_logic;
begin -- behavioral1
pi7 <= shift_register_data_out(1) xor shift_register_data_out(2) xor
shift_register_data_out(3) xor shift_register_data_out(4) xor
shift_register_data_out(5) xor shift_register_data_out(6) xor
shift_register_data_out(7);
pi8 <= shift_register_data_out(1) xor shift_register_data_out(2) xor
shift_register_data_out(3) xor shift_register_data_out(4) xor
shift_register_data_out(5) xor shift_register_data_out(6) xor
shift_register_data_out(7) xor shift_register_data_out(8);
bestchoice <= (shift_register_samples(1) and shift_register_samples(3)) or
(shift_register_samples(3) and shift_register_samples(7)) or
(shift_register_samples(7) and shift_register_samples(1));
-- purpose: Samplea y va generando el vector de salida shift_register_data_out
-- type : sequential
-- inputs : clock, reset, data_in
-- outputs: shift_register_data_out
SampleAndRead: process (clock, reset)
begin -- process SampleAndRead
if reset = '1' then -- asynchronous reset (active high)
shift_register_data_out <= "000000000";
shift_register_data_out_enable <= "000000000";
shift_register_samples_enable <= "00000000000000000";
shift_register_samples <= "00000000000000000";
receiving_byte <= '0';
data_out_enable <= '0';
crc_error <= '0';
estado <= "11";
data_out <= "00000000";
did_read_parallel_out <= '1'; -- supongo que ya puedo escribir en la
-- salida paralelo
byte_lost_error <= '0';
elsif clock'event and clock = '1' then -- rising clock edge
-- tomo la muestra de data_in
shift_register_samples <= shift_register_samples(15 downto 0) & data_in;
-- Latchup data_out_read
if did_read_parallel_out = '0' and data_out_read = '1' then
did_read_parallel_out <= '1';
end if;
if receiving_byte = '0' then
-- si todavia no recibi el bit de start
if shift_register_samples_enable(16) = '1' and
shift_register_samples = "10000000000000000" then
-- si acabo de recibir el bit de start. =>
receiving_byte <= '1';
shift_register_samples_enable <= "00000000000000001";
shift_register_data_out_enable <= "000000000";
shift_register_data_out <= bestchoice & shift_register_data_out (8 downto 1);
estado <= "10";
crc_error <= '0';
else
shift_register_samples_enable <= shift_register_samples_enable(15 downto 0) & '1';
end if;
else
-- si estoy recibiendo un byte, y recibi el ultimo bit (el bit pasado
-- fue el ultimo)
if (bits7 = '1' and parity = '0' and shift_register_data_out_enable (2) = '1') or
(bits7 = '1' and parity = '1' and shift_register_data_out_enable (1) = '1') or
(bits7 = '0' and parity = '1' and shift_register_data_out_enable (0) = '1') or
(bits7 = '0' and parity = '0' and shift_register_data_out_enable (1) = '1') then
receiving_byte <= '0'; -- ya termine de recibir el byte
-- si no tengo errores de paridad, considero que vino sin problemas
if (parity = '0') or (parity = '1' and
((bits7 = '0' and even = '0' and pi8 = shift_register_data_out(0)) or
(bits7 = '0' and even = '1' and not pi8 = shift_register_data_out(0)) or
(bits7 = '1' and even = '0' and pi7 = shift_register_data_out(1)) or
(bits7 = '1' and even = '1' and not pi7 = shift_register_data_out(1))))
then
if did_read_parallel_out = '1' then
data_out_enable <= '1';
did_read_parallel_out <= '0';
byte_lost_error <= '0';
data_out <= shift_register_data_out(8 downto 1);
else
byte_lost_error <= '1';
end if;
else
crc_error <= '1';
end if;
end if;
-- si estoy recibiendo un byte, y termine con este bit =>
if shift_register_samples_enable(15) = '1' then
shift_register_data_out <= bestchoice & shift_register_data_out (8 downto 1);
shift_register_data_out_enable <= '1' & shift_register_data_out_enable(8 downto 1);
shift_register_samples_enable <= "00000000000000001";
estado <= "01";
data_out_enable <= '0';
else
shift_register_samples_enable <= shift_register_samples_enable(15 downto 0) & '1';
end if;
end if;
end if;
end process SampleAndRead;
end behavioral1;
--------------46D7868C33BEF09E97CAA97D
Content-Type: text/plain; charset=us-ascii;
name="uarttx.vhd"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="uarttx.vhd"
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity uarttx is
Port ( data_in: in std_logic_vector(7 downto 0);
data_in_read: out std_logic;
data_out: out std_logic;
clock: in std_logic;
bits7: in std_logic; -- si los datos son de 7 u de 8 bits
parity: in std_logic; -- si hay paridad (no paridad: 0, paridad 1)
even: in std_logic; -- en caso que haya paridad, si es par (par: 1, impar: 0)
reset: in std_logic;
stopbits: in std_logic; -- 0: 1 bit de stop, 1: 2 bits de stop
data_in_enable: in std_logic;
estado: out std_logic_vector(1 downto 0)); -- estado del transmisor
end uarttx;
architecture behavioral of uarttx is
signal shiftcount : std_logic_vector(11 downto 0); -- guarda 1111111 , y cuando shiftea, agrega un 0
-- (para saber cuando termino de shiftear)
signal shiftregister : std_logic_vector(11 downto 0); -- shift register que uso para tx 8 datos, stt+2stp+paridad
signal decisor : std_logic_vector(3 downto 0); -- cadena de bits que uso para decidir
signal pp8 : std_logic; -- paridad par (8 bits de datos)
signal pi8 : std_logic; -- paridad impar (8 bits de datos)
signal pp7 : std_logic; -- paridad par (7 bits de datos)
signal pi7 : std_logic; -- paridad impar (7 bits de datos)
-- signal slowdown_reg : std_logic_vector(3 downto 0);
-- component counter4
-- Port (outs: out std_logic_vector(3 downto 0);
-- ins: in std_logic_vector(3 downto 0);
-- load: in std_logic; -- sinchronous load
-- reset: in std_logic; -- asincrhonous reset
-- clk: in std_logic; -- clk
-- ce: in std_logic; -- clk enable
-- dir: in std_logic);
-- end component;
begin
data_out <= shiftregister (0) when shiftcount(0) = '1' else '1';
decisor <= bits7 & parity & even & stopbits;
-- slowdown : counter4 port map (
-- outs => slowdown_reg,
-- ins => "0000",
-- load => '0',
-- reset => reset,
-- clk => clock,
-- ce => '1',
-- dir => '1');
-- purpose: Manages the shift register
-- type : combinational
-- inputs : clock
-- outputs: data_out
main: process (clock)
begin -- process main
if reset='1' then
shiftcount <= "000000000000";
shiftregister <= "000000000000";
data_in_read <= '0';
estado <= "11";
elsif clock'event and clock = '1' then
if shiftcount(1) = '1' then -- if the shift register is holding data
shiftregister <= '0' & shiftregister(11 downto 1);
shiftcount <= '0' & shiftcount(11 downto 1);
data_in_read <= '0';
estado <= "00";
elsif data_in_enable = '1' then -- if the shift register is empty, and I
-- have new data
estado <= "11"; -- reading data
data_in_read <= '1'; -- it is like saying "hey FPGA, i'm done
-- with my 8 bits input.
pp8 <= not pi8;
pp7 <= not pi7;
pi7 <= data_in(0) xor data_in(1) xor data_in(2) xor data_in(3) xor
data_in(4) xor data_in(5) xor data_in(6);
pi8 <= data_in(0) xor data_in(1) xor data_in(2) xor data_in(3) xor
data_in(4) xor data_in(5) xor data_in(6) xor data_in(7);
case decisor is
-- 8N1
when "0000" | "0010" => shiftregister <= "001" & data_in(7 downto 0) & '0';
shiftcount <= "001111111111";
-- 8N2
when "0001" | "0011" => shiftregister <= "011" & data_in(7 downto 0) & '0';
shiftcount <= "011111111111";
-- 8O1
when "0100" => shiftregister <= "01" & pi8 & data_in(7 downto 0) & '0';
shiftcount <= "011111111111";
-- 8O2
when "0101" => shiftregister <= "11" & pi8 & data_in(7 downto 0) & '0';
shiftcount <= "111111111111";
-- 8E1
when "0110" => shiftregister <= "01" & pp8 & data_in(7 downto 0) & '0';
shiftcount <= "011111111111";
-- 8E2
when "0111" => shiftregister <= "11" & pp8 & data_in(7 downto 0) & '0';
shiftcount <= "111111111111";
-- 7N1
when "1000" | "1010" => shiftregister <= "0001" & data_in(6 downto 0) & '0';
shiftcount <= "000111111111";
-- 7N2
when "1001" | "1011" => shiftregister <= "0011" & data_in(6 downto 0) & '0';
shiftcount <= "001111111111";
-- 7O1
when "1100" => shiftregister <= "001" & pi7 & data_in(6 downto 0) & '0';
shiftcount <= "001111111111";
-- 7O2
when "1101" => shiftregister <= "011" & pi7 & data_in(6 downto 0) & '0';
shiftcount <= "011111111111";
-- 7E1
when "1110" => shiftregister <= "001" & pp7 & data_in(6 downto 0) & '0';
shiftcount <= "001111111111";
-- 7E2
when others => shiftregister <= "011" & pp7 & data_in(6 downto 0) & '0';
shiftcount <= "011111111111";
end case;
end if; -- shiftcount(0) = '1'
end if; -- clock
end process main;
end behavioral;
--------------46D7868C33BEF09E97CAA97D
Content-Type: text/plain; charset=us-ascii;
name="divclock.vhd"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="divclock.vhd"
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
-- divclock
--
-- Dado un contador de 24 bits con reset asincronico, lo utiliza para dividir
-- la frecuencia del clock de entrada.
-- El valor de dividox es:
-- dividox = Fclock/Fsalida - 4
-- si dividox es impar, se redondeara al entero inmediato inferior.
--------------------------------------------------------------------------------
entity divclock is
port (clock : in std_logic; -- clock entrante (el que divido por lo
-- que me dice 'dividox'
reset: in std_logic; -- reset. Es asincronico
salida: out std_logic; -- el clock dividido por lo que se pide
dividox: in std_logic_vector(23 downto 0); -- x cuanto divido la
-- frecuencia del clock entrante
clockenable: in std_logic); -- countenable (del clock de entrada)
end divclock;
architecture test of divclock is
component counter24
Port (outs: out std_logic_vector(23 downto 0);
reset: in std_logic; -- asincrhonous reset
clk: in std_logic; -- clock
ce: in std_logic); -- clock enable
end component;
signal resetcnt: std_logic;
signal count: std_logic_vector (23 downto 0);
signal cuentohasta : std_logic_vector (23 downto 0);
signal tmpvec : std_logic_vector (23 downto 0);
signal salida_reg : std_logic;
begin -- test
-- hago que cuente desde cero hasta el valor que quiero
--** ins <= "111100001111000011110000";
--**cuentohasta <= "000000000001010001011000";
-- El contador lo uso para saber cuando invertir la salida, por lo que lo debo
-- usar para contar medio periodo.
cuentohasta (23 downto 0) <= '0' & dividox (23 downto 1);
--** cuentohasta <= "000000000000101000101011";
salida <= salida_reg;
cnt : counter24 port map (outs => count, reset => resetcnt, clk => clock, ce => clockenable);
-- purpose: dado un contador de 24 bits, divide al clock entrante x un factor
-- type : sequential
-- inputs : clock, globalreset, count
-- outputs: reset
BuildReset: process (clock, reset)
begin -- process BuildReset
if reset = '1' then -- asynchronous reset (active low)
resetcnt <= '1';
salida_reg <= '0';
elsif clock'event and clock = '1' then -- rising clock edge
if count = cuentohasta then
resetcnt <= '1';
salida_reg <= not salida_reg;
else
resetcnt <= '0';
end if;
end if;
end process BuildReset;
end test;
--------------46D7868C33BEF09E97CAA97D
Content-Type: text/plain; charset=us-ascii;
name="counter24.vhd"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="counter24.vhd"
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter24 is
Port (outs: out std_logic_vector(23 downto 0);
reset: in std_logic; -- asincrhonous reset
clk: in std_logic; -- clk
ce: in std_logic); -- clk enable
end counter24;
architecture behavioral of counter24 is
component counter4
Port (outs: out std_logic_vector(3 downto 0);
ins: in std_logic_vector(3 downto 0);
load: in std_logic; -- sinchronous load
reset: in std_logic; -- asincrhonous reset
clk: in std_logic; -- clk
ce: in std_logic; -- clk enable
dir: in std_logic);
end component;
signal count24: std_logic_vector (23 downto 0);
signal clocks : std_logic_vector(5 downto 1);
begin
outs <= count24;
clocks(5) <= not count24(19);
clocks(4) <= not count24(15);
clocks(3) <= not count24(11);
clocks(2) <= not count24(7);
clocks(1) <= not count24(3);
counterno0: counter4 port map (outs => count24(3 downto 0), load => '0', ins => "0000",
reset => reset, clk => clk, ce => ce, dir => '1');
counterno1: counter4 port map (outs => count24(7 downto 4), load => '0', ins => "0000",
reset => reset, clk => clocks(1), ce => ce, dir => '1');
counterno2: counter4 port map (outs => count24(11 downto 8), load => '0', ins => "0000",
reset => reset, clk => clocks(2), ce => ce, dir => '1');
counterno3: counter4 port map (outs => count24(15 downto 12), load => '0', ins => "0000",
reset => reset, clk => clocks(3), ce => ce, dir => '1');
counterno4: counter4 port map (outs => count24(19 downto 16), load => '0', ins => "0000",
reset => reset, clk => clocks(4), ce => ce, dir => '1');
counterno5: counter4 port map (outs => count24(23 downto 20), load => '0', ins => "0000",
reset => reset, clk => clocks(5), ce => ce, dir => '1');
end behavioral;
--------------46D7868C33BEF09E97CAA97D
Content-Type: text/plain; charset=us-ascii;
name="counter4.vhd"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="counter4.vhd"
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter4 is
-- 4-bit synchronous counter with count enable,
-- asynchronous reset and synchronous load
Port (outs: out std_logic_vector(3 downto 0);
ins: in std_logic_vector(3 downto 0);
load: in std_logic; -- sinchronous load
reset: in std_logic; -- asincrhonous reset
clk: in std_logic; -- clock
ce: in std_logic; -- clock enable
dir: in std_logic); -- direccion 0: down 1: up
end counter4;
architecture behavioral of counter4 is
signal count : std_logic_vector (3 downto 0); --:= "0000"; -- cuenta actual
signal din: std_logic_vector (3 downto 0);
begin
outs <= count;
din <= ins;
process (CLK, RESET)
begin
if RESET='1' then
COUNT <= "0000";
elsif CLK='1' and CLK'event then
if LOAD='1' then
COUNT <= DIN;
elsif CE='1' then
if DIR='1' then
COUNT <= COUNT + 1;
else
COUNT <= COUNT - 1;
end if;
end if;
end if;
end process;
end behavioral;
--------------46D7868C33BEF09E97CAA97D--
Article: 33216> I'm trying to get one source base which compiles on both > architectures. Hi, Martin oh, this is not the way xilinx and altera want you work on your design! BTW: to get the best results ( delay/area ) you are better to take the extra time to use the components in the x and a libs. In very some cases you may write a common hdl-wrapper for this components. In your design you can use this API. Mind, this does not help for the real design work - x-chips and a-chips are different. michael strothjohannArticle: 33217
Hi Vivian, Vivian schrieb: > Does anyone have experience with systemC synthesis tools for FPGAs. > What works best ? > > Viv afak, systemC is in beta-stage 1.x/2.0 ( just leaving the alpha-stage ) and still a moving target - so i wouldnt recommend anyone to develop a synthesis tool using it. i'm sorry about that. michael strothjohannArticle: 33218
Hi excuse the double post. my fault. Michael StrothjohannArticle: 33220
I thought that SystemC was intended only as a descriptive language - not as a language for synthesis. "Michael Strothjohann" <strothjohann@rheinahrcampus.de> wrote in message news:3B56FAC7.CCF1E503@rheinahrcampus.de... > Hi > > excuse the double post. > my fault. > > Michael StrothjohannArticle: 33221
In the MAX+plus II simulator you can display a waveform for every single word of all memories used. So in your case you would just select the first memory word that you expect the statemachine to write to and watch it during simulation. The name of the node in the SCF file would be e.g. for a word at address 21 (decimal) in some memory: |mem:1|lpm_ram_dq:lpm_ram_dq_component|altram:sram|content21_[7..0] In the SCF file just go to insert node, select Memory Word as type and hit the List button: If the window is to small to show the whole name, just select a line and you'll see the complete name at the top under "Node Name". You can also use wildcards like *ram*21_* to list and find the memory words you're looking for. - Wolfgang http://www.elca.de Russell Shaw <rjshaw@iprimus.com.au> wrote in message news:3B56DA58.EB88D436@iprimus.com.au... > Hi all, > > I've got an AHDL state machine thing that reads a word from > a lpm_ram_dq, adds or subtracts an increment, and stores the > result back. > > However, it won't work, like the ram just stays full of zeros. > > Is there any way to see the 'previous' ram location in the > waveform editor or simulation? > > --RussellArticle: 33222
> Maybe something like:
>
> SUBDESIGN test(
> CLK,RST: input;
> Dout[3..0]: output;
> )
>
> variable
> cntr[3..0]: DFF;
>
> BEGIN
> cntr[].clk=CLK&!(cntr[]==H"f");
> cntr[].clrn=!RST;
> cntr[]=cntr[]+1;
>
> Dout[]=cntr[];
> END;
>
> or like:
>
> SUBDESIGN test(
> CLK,RST: input;
> Dout[3..0]: output;
> )
>
> variable
> cntr[3..0]: DFF;
>
> BEGIN
> cntr[].clk=CLK;
> if(RST)
> then
> cntr[]=0;
> elseif(cntr[]!=H"f")
> then
> cntr[]=cntr[]+1;
> else
> cntr[]=cntr[];
> end if;
>
> Dout[]=cntr[];
> END;
>
> Anyone have a verilog example?
>
> --Russell
For a synchronous reset, saturable 4 bit counter:
module SatCntr ( Clk, Rst, Dout );
input Clk, Rst;
output [3:0] Dout;
reg [3:0] Dout;
wire [4:0] next_count;
always @(posedge Clk)
if( ~next_count[5] )
Dout <= next_count;
assign next_count = (Rst ? 5'h0 : {1'b0,Dout})
+ (Rst ? 5'h0 : 5'h1 );
endmodule
The reset syntax is geared for the Xilinx architecture (what I've been
designing with recently) and the use of the "wire" for combinatorial
logic lets the carry-out from the top stage work as an enable for the
registers. Total design size: 4 flops, no extra LUTs for the compare.
When Rst goes active, the next_count goes zero enabling the Dout load
even if the counter was previously saturated.
Article: 33223On 18 Jul 2001 07:44:25 -0700, achlys4now@yahoo.com (Achlys) wrote: >> Is this FIFO asynchronous, i.e., are the read and write clocks >> mutually asynchronous? If so, and if you're meeting static timing, >> I'd bet on a problem in the control logic. A resynchronization >> problem isn't going to show up as a static timing error, but it >> certainly can sink your design. >> >> Bob Perlman > >Thanks for the info but I've done the due diligence on the design. >Again it's not temperature related (as I'd expect for timing problems >assuming enough IC's are screened). I also know about the timing files >- we spent several weeks figuring out those timing problems before >Xilinx "remembered" the speed file issue. > >I understand that Xilinx has recalled stock from distributors for >rescreening. Something about metal particle defects shorting routing >channels around BRAM's - this would explain why certain parts work w/ >certain bit files. And why the failures are of the "hard" type - not >intermittent as in a timing related failure. Thanks for the tip. If you find out more, please post. Bob PerlmanArticle: 33224
On Tue, 17 Jul 2001 14:58:06 -0500, "David Wright" <dwright@srtorque.com> wrote: >Has anyone had a working logic design in VHDL other than a few Cypress and >Xilinx insiders? > >Logic was never this complicated before! > >What a total waste of human intelligence. > >It is far easier to build with discrete MSI/LSI parts or code in computer >language than get even something simple into a small CPLD or FPGA. > > > The Xilinx schematic entry process (using just the Foundation software) is easy to use... just like connecting a bunch of TTL cans. If you can get your hands on the Libraries Guide handbook, it's even easier. For some reason, Xilinx makes it very hard to get this book, and it hasn't been updated in a long time. If you're a visual person (as opposed to a language person) schematic entry is the way to go. You can *see* all the logic in a flash, as opposed to reading and decoding hundreds of pages of arcane text. I like my engineers to use schematic entry. That way, when they have a problem, I can flip through their schematics, understand their structure, and generally spot their bugs in a couple of minutes. John
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