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Hi all, I am using an accumulator to accumulate N samples. I have a seperate counter to N which, when reached, will reset the accumulator back to zero to begin accumulation again. My only problem is that the accumulator misses one sample in this reset as it goes back to zero. I initially used a synchronous clear pin, but after spotting the problem, tried to use an asynchronous pin. My N counter goes high for one clockperiod to reset, so I tried AND gating it with the clock period (both inverted and non inverted) to only reset for half a clock period - this still doesn't work and the accumulator still insists on going back to zero for one clock period. Any ideas? AdrianArticle: 33351
Hi,
I need a Register chain of 402 Flip Flops, but the compiler make an
error.
Is there any way to program so many Flip Flops? I Use Altera ACEX1K
Family (EP1K100FC484-1)
Here my VHDL-Code:
Library ieee;
USE ieee.std_logic_1164.all;
Library altera;
USE altera.maxplus2.all;
entity register_out is
port(
clk,RST,SO : in std_logic;
Sout : out std_logic);
end register_out;
architecture rtl of register_out is
signal FF1 : std_logic_vector (401 downto 0);
begin
posedge : process (RST, clk)
begin
if (RST = '0') then
FF1 <=(FF1'range => '0');
elsif (CLK'event and CLK ='1') then
FF1 <= SO & FF1 (FF1'length-1 downto 1);
end if;
end process;
Sout <= FF1 (0);
end rtl;
Thanks,
Marc
Article: 33352marc wrote in message <3B5D48AA.57E80125@web.de>... >Hi, >I need a Register chain of 402 Flip Flops, but the compiler make an >error. >Is there any way to program so many Flip Flops? I Use Altera ACEX1K >Family (EP1K100FC484-1) See LRM section 9.7 for Generate statement. It's very simple. Jyke.Article: 33353
Rick Filipkiewicz a écrit : > No real criticism Daniel but I've heard this sort of thing a > lot but I reckon the length thing is basically voodoo. I've > run 3x 3 meter Centronics extension cables + the Parallel-3 & > configured CPLDs with not problem (back in the early days of > the JTAG programmer when it didn't run on Win95 I had to do > this to reach the NT box on the far side of the office). Actually, removing the capacitors did not solve anything. I found another Xilinx-made cable so I gave up trying to make the homemade one work. -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 33354
You can also get a BGA to PGA adapter and have the part mounted on the adapter by a shop that has the equipment to do it right. One of my customers did that a while back, I think he said it cost him around $50 to do. cyber_spook wrote: > Good Luck is all I can say - these can be a real pain in the... But find a board > builder with experance to place your part (recommendation - so you can kick them > when it don't work) However I found the folloing help full. Keep the part > towards the center of the board, Don't flood fill too think or unless you realy > need to (this will all pull heat away). Now this I cant remember - somthing to > do with the pad, you get copper or pre solderd ones if I remember. I think the > copper ones were better? Get your stuff X-rayed and JTAGed afterwords - At this > point its realy worth rembering that complex designs can be a lot easyer to > fault find with lots of boudary scan devices on your board. We found corner pins > the biggest problem, would not flow or cracked during the cool down. > > I the end we payed someone that knowns what they are doing - cost a lot less > that our own labour and time. > > Cyber_Spook_Man > > Anthony Ellis wrote: > > > This is not an FPGA question but I guess many of you may have designed > > FPGA's using similar technology and work for companies that have some advice > > to part with. > > > > We have a PCB designed for a 255 pin Ceramic BGA and are struggling to > > solder this correctly. Plastic BGA's are not an issue however. > > Obviously the ceramic absorbs the reflow energy but we haven't been able to > > find the correct technique to pre-heat the part. I guess we could measure > > the pre-heated component temperature if we had some idea about it's required > > value. > > > > Any help please. > > > > Thanks Anthony -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33355
Well, actually it seems that I put a jinx on my cable - just a few hour ago I noted first problem with it. Something went wrong during XC9572 CPLD programming and when I used my old 0,5m cable everything was ok. Sorry for trying to be wiser than Xilinx people. However the cable has 2m and I have used it around 50 times programming 3 different Xilinx devices (XC9500 family) and everything worked fine...until now. Maybe I had too much luck...? By the way. I'm working on new project where my CPLD is placed on PCI card. Can I somehow use PCI bus to program CPLD? This would be a gret help because I could change configuration without opening computer case. Where can I look for JTAG protocol and the proper software? Best regards Daniel Rick Filipkiewicz wrote: > Daniel Hañczewski wrote: > > > Hi, > > > > I have also made this cable and the only problem I met was cable length. > > Xilinx advices wire connection between JTAG header and Parallel III > > electronics to be "as short as possible" and between electronics and LPT > > port no longer than 2m. I have placed electronics inside standard DSUB25 > > connector and according to Xilinx's schematic JTAG-electronics cable length > > musn't exceed 0,5m. Finally I got rid of all 100pF capacitors connected to > > JTAG signal lines and now my cable has 2m and works without reservation. I > > haven't tried to make it longer... > > > > Regards > > Daniel > > > > No real criticism Daniel but I've heard this sort of thing a lot but I reckon > the length thing is basically voodoo. I've run 3x 3 meter Centronics extension > cables + the Parallel-3 & configured CPLDs with not problem (back in the early > days of the JTAG programmer when it didn't run on Win95 I had to do this to > reach the NT box on the far side of the office). > > Now our boards have the Xilinx P-III h/w on them & it only takes 2 extension > cables.Article: 33356
Hi Marc, your code is synthesizable by using Synplicity´s Synplify or SynplifyPro products. You can download an evaluation copy from Syplicity´s web-page (www.synplicity.com). PhilArticle: 33357
Never mind, just solved my problem!!Article: 33358
Using the New Silos-3 Demo Program (version 2001.100, build 398)
I open project exam1a.spj and click on Debug -> Go.
I get:
S I L O S Version 2001.100
DEMO COPY LIMITED TO 200 DEVICES AND 350 LINES OF HDL CODE
Copyright (c) 2001 by SIMUCAD Inc. All rights reserved.
No part of this program may be reproduced, transmitted,
transcribed, or stored in a retrieval system, in any
form or by any means without the prior written consent of
SIMUCAD Inc., 32970 Alvarado-Niles Road, Union City,
California, 94587, U.S.A.
(510)-487-9700 Fax: (510)-487-9721
Electronic Mail Address: "silos@simucad.com"
!file .sav="EXAM2A"
!control .sav=3
!control .enablecache
!control .savcell=0
!control .disk=1000M
Reading "exam2.v"
!con .ext=all
!con .fsim
!fmon .detail
!fcon .fmem=2
!slow .pct=100%
!shigh .all
!islow .all
!ishigh .pct=100%
!prep
Reading "C:\SILOS3\EXAMPLES\exam2.ss1"
Highest level modules (that have been auto-instantiated):
test_bench
11 total devices.
!fsim
error 5.398 : fault simulation requires running the hyperflt program file
fault simulation requires running the hyperflt program file
=================================================
"Srinivasan Venkataramanan" <svenka3@siliconsystems.co.in> wrote in message news:9jj0mj$ovr@news.or.intel.com...
> Hi Dave,
>
>
> "Dave Feustel" <dfeustel@mindspring.com> wrote in message
> news:9jhc90$g0p$1@nntp9.atl.mindspring.net...
> >
> > I downloaded the Silos demo program but it reports fatal errors when I try
> > to run any of the sample projects. I'd be willing to try the evaluation
> version
> >
>
> What kind of error does it report? I had a similar situation
> sometime ago and it said:
>
> " Said that I must select a device.
> I was using Silos III demo version."
>
> If this is the error that you have encountered I can sugegst a workaround,
> do let me know.
>
> Srini
>
>
>
Article: 33359I am attempting to install the Xilinx Foundation Software eval package On Windows 2000 Pro. When I enter the required registration id, the setup program displays a message saying that this software won't install with any other Xilinx software installed. Unfortunately the error message includes absolutely no information as to which other software package (or where it is on the disk) that the setup program finds offensive . I have checked the start programs menu, the top level C directory and the registry and I can find no sign of any software identified as from Xilinx. There is installed on this machine some software licenced from Atmel. There also is something from Mentor Graphics installed. Does anyone have any idea what software it is that the Xilinx setup program is complaining about? Thanks, Dave Feustel Fort Wayne, IndianaArticle: 33360
Can anyone recommend an IEEE1394 (Firewire) controller IP core.Article: 33361
marc <m200b@web.de> wrote > I need a Register chain of 402 Flip Flops, but the compiler make an > error. > Is there any way to program so many Flip Flops? I Use Altera ACEX1K > Family (EP1K100FC484-1) You could consider using one of the embedded dual-port memory blocks. Drive both the read and write address with the same modulo-402 counter. On each cycle, you will write a new bit at the same time you read the bit that was written 402 cycles previously. Or you could use a xilinx chip that has a 16-bit shift register built into each LUT.Article: 33362
Phil Hays schrieb: > > Also, it would be possible to measure a temperature rise from a known heat flow > (build a board with only the FPGA, and load a design that is intended only to > generate heat, and then directly measure the power to the board, and use this to > calibrate your board/test fixture for the real board. Hmm, good idea. -- MFG FalkArticle: 33363
On Mon, 23 Jul 2001 10:17:49 +0200, Nicolas Matringe <nicolas.matringe@IPricot.com> wrote: We have incorporated this logic into a few of our test sets. The biggest problem that we found is that the 74HC125 input buffers are very sensitive to input noise, producing glitches on the outputs. Glitches on CLK are bad news. I guess those capacitors on the HC125 outputs are supposed to be a fix for this, but they would have been more effective on the inputs. We added pairs (series connected) of 74ACT14 Schmitt trigger inverters in front of the HC125 inputs (DIN, CLK, and TMS_IN). We also added a 68pf cap to ground on the CLK input at the parallel cable connector. This circuit has worked flawlessly ever since, even with long cables. >Hi >I've built a Xilinx Parallel cable according to the schematics available >on Xilinx's site and it doesn't work. When I use the original cable >everything is fine so my board is OK. I looked at the signals with an >oscilloscope and everything seems normal (I see TDI, TCK and TMS toggle >on the board), except that TDO stays high. Any idea? =================================== Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.comArticle: 33364
Unfortunately, this is not a task that can be done in-house without the proper equipment. You will need a small reflow oven which is temperature controlled. Then just program in the reflow temperature profile that is specified by the BGA manufacturer. In addition, you also need to position the BGA precisely on the solder pads. An alternative is to send the BGA mounting job out to professional assembly shops and have them x-ray'ed afterwards for the first run. In this way, you'll save a lot of headache trying to debug your firmware on a defective or partially defective board. Edward Richmond, B.C. Canada On Sat, 21 Jul 2001 11:17:27 +0200, "Anthony Ellis" <xxxa.ellis@logicworks.co.za> wrote: >This is not an FPGA question but I guess many of you may have designed >FPGA's using similar technology and work for companies that have some advice >to part with. > >We have a PCB designed for a 255 pin Ceramic BGA and are struggling to >solder this correctly. Plastic BGA's are not an issue however. >Obviously the ceramic absorbs the reflow energy but we haven't been able to >find the correct technique to pre-heat the part. I guess we could measure >the pre-heated component temperature if we had some idea about it's required >value. > >Any help please. > >Thanks Anthony > > > > > >Article: 33365
Hi Nicolas, I have read this thread with interest as I was making a homebrew cable myself. Today it was completed and after adding a wire I had missed off (I should have checked my drawing), I was able to program a 95288XL CPLD. One thing I had to do first was a cable reset probably because my power-up was not perfect. The problem with the cable length also depends on the cable type. Ideally all lines should be idividually screened but this costs and if your dept is like mine we get the cheapest. Flat ribbon cable is a half-way-house as only the adjacent lines will cause a real problem. I also agree with a comment made that the capacitors should be on the input to the buffers. ----------- The problem I seem to have now is that I have programmed a XCV300 device but it asks for a .msk file before it can verify and I can't fine one anywhere. Can anybody help with this? Cheers Dave "Nicolas Matringe" <nicolas.matringe@IPricot.com> wrote in message news:3B5BDDAD.9DBA32BA@IPricot.com... > Hi > I've built a Xilinx Parallel cable according to the schematics available > on Xilinx's site and it doesn't work. When I use the original cable > everything is fine so my board is OK. I looked at the signals with an > oscilloscope and everything seems normal (I see TDI, TCK and TMS toggle > on the board), except that TDO stays high. Any idea? > > -- > Nicolas MATRINGE IPricot European Headquarters > Conception electronique 10-12 Avenue de Verdun > Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE > Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 33366
I read Francis's post, and thought maybe I had written it myself! I am having exactly the same frustration with WebPack. I am VERY new to FPGA's, and am beginning to think I've been hibernating for the last 10 years while this technology has been developing! I've read about how much easier it is to design in VHDL than in schematics, and if schematics are becoming as obsolete as vacuum tubes, then I'll have to learn VHDL. But, I can only learn it slowly, and, in the mean time, I need a good schematic editor to download my designs into a Spartan 2. If anyone can offer us some advise, please do! John francis_mtl@hotmail.com (Francis) wrote in message news:<9ca94df1.0107201117.50f28fd4@posting.google.com>... > Hi, > > I downloaded the latest version of WebPack and, while the schematic > editor is present, I can't find the libraries (except for the 9500 > CPLD family that I don't plan to use anyway). > > I thought it was a mistake, and tried to download/install it again > but the only schematics libraries that are included are the 9500 ones. > > How comes the Spartan II libraries are left out ? > > It is my understanding (I might be wrong) that the WebPack is supposed > to be an introductory package, designed to attract peoples who are > relatively new to FPGA design, and as such, being forced to learn > VHDL (seems to be a long, and somewhat frustrating/painful road) when > schematic is (at least for me) much easier & a lot more natural to use, > (at least for first / simple projects) looks like a nonsense. > > I understand that the free package can't include all (else, who would > buy the ISE software ?) and older or bigger devices are left out, but > schematic entry is a basic feature, and the fastest way someone new > to FPGA can evaluate Xilinx products. Putting it aside when the "A" > brand includes it in the free package seems odd. > > I know this is becoming a HDL world (I might get into it later), but > being forced to learn it upfront makes me pause, and I'm sure I'm not > the only one. > > Will we see the libraries in the next release ? > I really hope so. > > Francis.Article: 33367
or use a pair of modulo 2^n (where 2^n is the depth of the block ram) counters and delay the start of the read counter by 402 clocks. This uses more resources for a one-up delay, but if you have a bunch of identical delays, need to be able to reprogram the count modulus, and can't afford the wide distribution of a multibit programming word, it can help to keep the performance and routing density reasonable. Don Husby wrote: > marc <m200b@web.de> wrote > > I need a Register chain of 402 Flip Flops, but the compiler make an > > error. > > Is there any way to program so many Flip Flops? I Use Altera ACEX1K > > Family (EP1K100FC484-1) > > You could consider using one of the embedded dual-port > memory blocks. Drive both the read and write address > with the same modulo-402 counter. On each cycle, you > will write a new bit at the same time you read the bit > that was written 402 cycles previously. > > Or you could use a xilinx chip that has a 16-bit shift > register built into each LUT. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33368
marc wrote: > > Hi, > I need a Register chain of 402 Flip Flops, but the compiler make an > error. > Is there any way to program so many Flip Flops? I Use Altera ACEX1K > Family (EP1K100FC484-1) > Compiles fine for me once I take out the unused library references: --Library altera; --USE altera.maxplus2.all; The device has plenty of flops. What is the error? --Mike TreselerArticle: 33370
John Wertenbaker wrote:
>
> I read Francis's post, and thought maybe I had written it myself! I
> am having exactly the same frustration with WebPack. I am VERY new to
> FPGA's, and am beginning to think I've been hibernating for the last
> 10 years while this technology has been developing! I've read about
> how much easier it is to design in VHDL than in schematics,
It's only easy once you know how to do it.
> and if
> schematics are becoming as obsolete as vacuum tubes, then I'll have to
> learn VHDL.
Relax. Lots of folks are still using schematics.
> But, I can only learn it slowly,
That's the only way to learn it.
> and, in the mean time, I
> need a good schematic editor to download my designs into a Spartan 2.
> If anyone can offer us some advise, please do!
Webpack only supports schematics for small devices.
Foundation ISE and others cover Spartan 2.
--Mike Treseler
Article: 33371
Hi Francis,
I was in the same situation a year ago. No experience of HDL.
Out dept got into verilog and since than I have not looked back.
Firstly, HDL should be viewed as a different concept. (IMHO)
If you want to design in terms of schematic you can,
eg (Verilog)
// D-type
always @(posedge reset or posedge clock)
begin
if (reset) D=0;
else D=1
end
// Mux
assign MyMux = MyInput : Why ; MyOtherInput;
// logic
wire orgate = A || B;
So you copy from schematic and paste into verilog.
Using VHDL or verilog, well that's a different argument but you get the
picture?
Dave
"Francis" <francis_mtl@hotmail.com> wrote in message
news:9ca94df1.0107201117.50f28fd4@posting.google.com...
> Hi,
>
> I downloaded the latest version of WebPack and, while the schematic
> editor is present, I can't find the libraries (except for the 9500
> CPLD family that I don't plan to use anyway).
>
> I thought it was a mistake, and tried to download/install it again
> but the only schematics libraries that are included are the 9500 ones.
>
> How comes the Spartan II libraries are left out ?
>
> It is my understanding (I might be wrong) that the WebPack is supposed
> to be an introductory package, designed to attract peoples who are
> relatively new to FPGA design, and as such, being forced to learn
> VHDL (seems to be a long, and somewhat frustrating/painful road) when
> schematic is (at least for me) much easier & a lot more natural to use,
> (at least for first / simple projects) looks like a nonsense.
>
> I understand that the free package can't include all (else, who would
> buy the ISE software ?) and older or bigger devices are left out, but
> schematic entry is a basic feature, and the fastest way someone new
> to FPGA can evaluate Xilinx products. Putting it aside when the "A"
> brand includes it in the free package seems odd.
>
> I know this is becoming a HDL world (I might get into it later), but
> being forced to learn it upfront makes me pause, and I'm sure I'm not
> the only one.
>
> Will we see the libraries in the next release ?
> I really hope so.
>
> Francis.
Article: 33372Leon_Heller@hotmail.com (Leon Heller) wrote in message news:<6e111008.0107232202.7c627cab@posting.google.com>... Try: http://www.geocities.com/leon_heller/flex.html Geocities doesn't like people storing files. > LeonArticle: 33373
nk wrote: > > I am wondering what exactly is meant by "full vhdl and verilog support", because i keep getting "...not supported" kind of error messages with the webpack software. You have to make sure your code is synthesizable. --aArticle: 33374
Greg Neff wrote: > On Mon, 23 Jul 2001 10:17:49 +0200, Nicolas Matringe > <nicolas.matringe@IPricot.com> wrote: > > We have incorporated this logic into a few of our test sets. The > biggest problem that we found is that the 74HC125 input buffers are > very sensitive to input noise, producing glitches on the outputs. > Glitches on CLK are bad news. I guess those capacitors on the HC125 > outputs are supposed to be a fix for this, but they would have been > more effective on the inputs. > > We added pairs (series connected) of 74ACT14 Schmitt trigger inverters > in front of the HC125 inputs (DIN, CLK, and TMS_IN). We also added a > 68pf cap to ground on the CLK input at the parallel cable connector. > This circuit has worked flawlessly ever since, even with long cables. Interesting. Our - purely accidental - solution seems to be that we replaced the 'HC125s with LS125s. Or was it accidental ? I have a feeling that our ancient ca 1996/7 Parallel-III cable might not use the HC parts, these might have been added to program XL devices on pure 3V3 boards - I'll check.
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z