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I also use a 1 GHz with 512Mbytes of RAM. The RAM is very important so that the software doesn't have to use the hard-disk. ( About all my 512 Mbytes is occupied during a routing). Hakon Leon Heller <leon_heller@hotmail.com> wrote in message news:9mdvjc$2nh$1@plutonium.btinternet.com... > > > "H.L" <alphaboran@yahoo.com> wrote in message > news:9mcvnp$1r11$1@ulysses.noc.ntua.gr... > > Hello all, > > I am going to program a Xilinx FPGA for the first time. I wanna setup the > > synthesis tools on a pc, what must be the system's requirements for proper > > (and relatively fast) function? > > Thanks > > > > > > It obviously depends on the size and complexity of your design. I find a 1 > GHz Athlon with 512 Mbytes of RAM works quite well with the Xilinx and > Altera tools. > > Leon > -- > Leon Heller, G1HSM leon_heller@hotmail.con > http://www.geocities.com/leon_heller > Low-cost Altera Flex design kit: http://www.leonheller.com > > > >Article: 34501
Hi I sounds like the same problems i have had until i tried to understand how the CLB's are build. In the beginning of my design i just placed components from the libraries and was not able to get the speed i needed for several 33bit counters, RAM's and multiplexers using 4 different clocks for a design controlling 8GB SDRAM and Firewire-interface. Then i had a look into the predefined symbols and the CLB's swapping between schematics & FPGA-editor making me able to get the speed using LUT's, mux'es and the other basic CLB units which i preplaced making the timing-results much more predictable. The P&R has to start somewhere and the result will always be a qualified guess. My experince is that as a start one could use the libraries and then dig into the symbols for a better understanding before making your own symbols. We all have our best ways of implementing a design and the best way for me is to use schematics as i get a much clearer overall picture than by using VHDL so my design is completely schematic. Best regards IvarArticle: 34502
Moadl, > So I'm wondering if anyone out there has successfully implemented > a USB-interface in a Xilinx-FPGA or is this really something I > should do in another way? yes, we developed a USB Function Controller and implemented it in a Xilinx Virtex FPGA. The USB Core is about 200 slices, a combination of USB, an 8051 derivative, and glue logic is about 700 slices, so it is quite feasable. For further information, please refer to the following application note: http://www.trenz-electronic.de/down/an-usb-xsv.pdf For pricing of our cores, please refer to: http://www.trenz-electronic.de/ip/ipen4.htm A lot of people will argue, that implementing USB in an FPGA does not make sense, as there are cheap microcontrollers with USB out there. However, there are at least two scenarios, where an FPGA implementation of USB makes good sense: a) if you require high bandwidth isochronous transfers, you will need to attach your logic directly to the USB FIFOs, which is cumbersome with off-the-shelf chips. b) if you already have an FPGA on the board, the marginal cost of implementing USB in it may be well below the cost of adding another chip. Hope this helps, if you have further questions, please do not hesitate to contact me. Best regards Felix Bertram _____ Dipl.-Ing. Felix Bertram Trenz Electronic Duenner Kirchweg 77 D - 32257 Buende Tel.: +49 (0) 5223 49 39 755 Fax.: +49 (0) 5223 48 945 Mailto:f.bertram@trenz-electronic.de http://www.trenz-electronic.deArticle: 34503
Daniel, to store an XC2S200 design in non-volatile memory, you could either use Atmel's serial EEPROMs (AT17LVxx), or Xilinx' Flash PROMs (XC18V02). Price is about the same, but the latter are fully supported by the Xilinx tools. Typically, you will program the Flash PROM using JTAG, while the PROM configures the FPGA in Master Serial mode. Refer to the Xilinx Product Specification "XC18V00 Series of in-System Programmable Configuration PROMs". If you are looking for a Spartan-II Development System that is already providing Flash PROM, please refer to: http://www.trenz-electronic.de/prod/proden6.htm Hope this helps, best regards Felix Bertram _____ Dipl.-Ing. Felix Bertram Trenz Electronic Duenner Kirchweg 77 D - 32257 Buende Tel.: +49 (0) 5223 49 39 755 Fax.: +49 (0) 5223 48 945 Mailto:f.bertram@trenz-electronic.de http://www.trenz-electronic.de "Daniel Nilsson" <danielnilsson@REMOVE_THIShem3.passagen.se> wrote in message news:9mdha9$cpg$1@eol.dd.chalmers.se... > Hi. > I am not entirely new to pld's, but I have never worked with any kind of > fpga, and I wonder: > > I want to use something in the range XC2S200 in my design, I have seen > experiment boards equipped with this chip, that are programmed by xilinx > programmer cable, but these fpga:s don't store the bitfile internally AFAIK, > so some EEPROM has to be added? how is this done? how does programming then > work (and erase)?Article: 34504
lingbo wrote: > I want to ask a question about the synthesis and simulation. > After synthesis with the syplify, > how can i do a post-simulation. > And what must be noted in the process of synthesis and simulation(detailed ). > Thank you .Waiting for your reply. You need to include this command in your Tcl synth script (don't know how to do the GUI): set_option -write_verilog true [or write_vhdl] to give you a post-synth .vm netlist in Verilog [VHDL]. Compile this into your simulator & run it. For Synplify there's no need even to use the UNISIMS lib since the .vm file includes all the models.Article: 34505
Hello again,
thanks for the replies :-> It turned out I got myself into trouble on two
counts. One, the async design, and two, I tried to do things on both edges
of the system clock. After I fixed these two it did the trick. It did indeed
look as if the compiler had resolved the assignments to led_1 and led_0 to be
continous, regardless of sys_clk. I've appended the working code below for
the benefit of all those _other_ ;) lurking newbies out there.
What still has me slightly miffed though is the fact that it compiled and
programmed without any warnings whatsoever. No "incomplete sensitivity
list" or something similar as has been suggested.
Also, I came upon this interesting read about metastables, that clarified
things for me. I think I got the link from the ng somewhere.
http://www.fpga-faq.com/FAQ_Pages/0017_Tell_me_about_metastables.htm
http://www.interfacebus.com/Design_MetaStable.html
So, the lesson in here seems to be:
- do NOT use both edges of the system clock
- avoid asynchronous logic, or expect pain
- Altera's verilog compiler sucks
cheers,
Fred
--- 'shift_leds.v' code included below ---
module shift_leds(sys_clk, sys_rst_l, async_ser_clk, async_ser_dat,
led_3, led_2, led_1, led_0);
input sys_clk;
input sys_rst_l;
input async_ser_clk; // serial clock, in AVR clock-domain
input async_ser_dat; // serial data, in AVR clock-domain
output [7:0] led_3, led_2, led_1, led_0;
wire sys_clk;
wire sys_rst_l;
wire async_ser_clk, async_ser_dat;
reg [7:0] led_3, led_2, led_1, led_0;
reg [1:0] clk_syncer, dat_syncer; // dual-stage synchronizer
wire ser_clk, ser_dat;
reg last_ser_clk_neg;
wire ser_clk_negedge_detect_l;
assign ser_clk = clk_syncer[1];
assign ser_dat = dat_syncer[1];
assign ser_clk_negedge_detect_l = (last_ser_clk_neg | ser_clk);
always @(posedge sys_clk or negedge sys_rst_l) begin
if (~sys_rst_l) begin
clk_syncer <= 0;
dat_syncer <= 0;
last_ser_clk_neg <= 1;
led_1 <= 8'b11110000; // just a test-pattern
led_0 <= 8'b11001100;
end else begin
led_3 <= {8 {ser_clk}};
led_2 <= {8 {ser_dat}};
clk_syncer <= {clk_syncer[0], async_ser_clk};
dat_syncer <= {dat_syncer[0], async_ser_dat};
last_ser_clk_neg <= (~ser_clk);
if (~ser_clk_negedge_detect_l) begin
// negedge ser_clk
// right 2 are shift register with ser_dat input on the right
led_1 <= {led_1[6:0], led_0[7]};
led_0 <= {led_0[6:0], ser_dat};
end
end
end // always @ (posedge sys_clk or negedge sys_rst_l)
endmodule // shift_leds
Article: 34506khtsoi@pc90026.cse.cuhk.edu.hk wrote: > Hi, > I want to download a bitstream (*.bit file) to a Xilinx > FPGA (e.g. xcv600) through a DB9 serial cable (model: DLC4). > Must I use the tools provided by Xilinx? Is there any > possibility I can write a segment of codes to do this in > my application? Thanks in advnce! OK, this isn't exactly what you asked for, but perhaps it's of some use: [Xilinx FPGA Download Adapter & Linux-Software] http://members.surfeu.de/matthias.prinke/archives/xck.tar.gz FredArticle: 34507
Felix, Have you any plans to implement USB 2.0 in FPGA? Thanks, Dave Feustel Fort Wayne, Indiana USA "Felix Bertram" <fbertram@gmx.net> wrote in message news:9mfdo2$1s759$1@ID-31589.news.dfncis.de... > Moadl, > > > So I'm wondering if anyone out there has successfully implemented > > a USB-interface in a Xilinx-FPGA or is this really something I > > should do in another way? > > yes, we developed a USB Function Controller and implemented it in a Xilinx > Virtex FPGA. The USB Core is about 200 slices, a combination of USB, an 8051 > derivative, and glue logic is about 700 slices, so it is quite feasable. > > For further information, please refer to the following application note: > http://www.trenz-electronic.de/down/an-usb-xsv.pdf > For pricing of our cores, please refer to: > http://www.trenz-electronic.de/ip/ipen4.htm > > A lot of people will argue, that implementing USB in an FPGA does not make > sense, as there are cheap microcontrollers with USB out there. However, > there are at least two scenarios, where an FPGA implementation of USB makes > good sense: > a) if you require high bandwidth isochronous transfers, you will need to > attach your logic directly to the USB FIFOs, which is cumbersome with > off-the-shelf chips. > b) if you already have an FPGA on the board, the marginal cost of > implementing USB in it may be well below the cost of adding another chip. > > Hope this helps, if you have further questions, please do not hesitate to > contact me. > > Best regards > > Felix Bertram > _____ > Dipl.-Ing. Felix Bertram > Trenz Electronic > Duenner Kirchweg 77 > D - 32257 Buende > Tel.: +49 (0) 5223 49 39 755 > Fax.: +49 (0) 5223 48 945 > Mailto:f.bertram@trenz-electronic.de > http://www.trenz-electronic.de > > >Article: 34508
> > My suggestion is to look for the rising edge and generate a single registered > signal for one system clock period. When that one register is valid, enable > your count. Everything falls into place. > Thanks a lot, that's the right way. > Someone could provide a quick code snippet if you let us know your language - > verilog? vhdl? ahdl? > I have it done in VHDL already. JanArticle: 34509
For best portability, text-based vhdl/verilog has to be the best. Most people in industry are familiar with Modelsim for simulation. For rapid design entry, clear visual representation of the design and automated checking of connections between blocks, a graphical tool is great, but only its output is portable. The FSM entry is also very helpful for larger state machines. Renoir and Aldec are both comprehensive tools. For synthesis Synplify has to be the easiest to use and produces good results. Leonardo produces good results too, but is painful to use and often requires nasty scripts. Having used Renoir/Leonardo/Alliance flow and Aldec/Synplify/Alliance, I prefer the latter. (In my personal opinion, Renoir is a typical Mentor tool, being non-intuitive and slow to learn and use.)Article: 34510
On Mon, 27 Aug 2001 20:09:17 GMT, arast@inficom.com (Alex Rast) wrote: >In article <3b86ed56.46990212@news.compuserve.com>, 101551.3434@compuserve.com (Mark Taylor) wrote: >>On Fri, 24 Aug 2001 00:19:48 GMT, arast@inficom.com (Alex Rast) wrote: >> >>>This is one I think I've done before, so I probably just need my memory >>>jogged. I'm sure it's something that happens, and that you need, all the time. >>> >>>I've defined a hard macro, call it custommacro.nmc. .... Now, at least one of the nets connects to an >>>external pin and an internal route. One common example, for instance, is CLK. >>>You want the signal to be common to the internal CLB's of the macro and to >>>connect to external routes (in the case of CLK, to the global clock net). >>> >> >>As far as I know, nets could never be included in hard macros. >>(despite documentation suggesting otherwise, right back to before EPIC) > >No, I have no problem including a net in a macro. What I have difficulty doing >is routing an external net *to* the macro's internal net. > >>Just use the hard macro to configure slices/CLBs or whatever, >>then embed the macro within a soft macro >> (ie a schematic macro with RLOCS). >>The soft macro can contain all the routing. > >I don't think this would work, for 2 reasons. First, I *have* to have a >specific routing within the hard macro (indeed, the routing itself is a key >part of the design), so I can't afford to let the software take care of any >routing at the hardware level. Second, a lot of the things we're doing are >functions you simply can't enter properly in Schematic Editor, not because you >can't implement them on-chip, but because the programmers didn't anticipate >you'd be doing these kinds of functions. Just for giggles, I decided to input >the closest approximation to our macro you could do in Schematic Editor. The >resultant imlementation, in addition to being close but not exactly the same >in functionality, occupied 6 times as many CLB's! This is kind of the result I >was expecting, because it's clear the program doesn't think of or implement >resource reuse, i.e. using the same logic elements to implement multiple >functions, nor will it use multiple data paths within the same CLB, i.e. using >different data outputs to generate different function outputs. It thinks of a >CLB slice implementing one function. Are you thinking along some other line? >If so, can you clarify what your approach would be? > >Alex Rast >arast@inficom.com >arast@qwest.net Get rid of any general purpose routing within your hard macro. Keep all interconnections within a CLB. (These doesn't really count as nets at a low level) Ensure the number of macro pins is enough to complete all needed routing. Now you will have a hard macro, with perhaps somewhat more pins than you had before. When you instantiate this macro you will be able to complete ALL routing. (there won't be any strange nets for the software to complain about.) This approach has worked for me in the past. Bear in mind that the router is usually pretty good. It's just the mapping & placement that sometimes needs working on. The mapping & placement is totally defined by the given approach, so theres nothing much to foul up on afterwards. (unlike the M1 software) If you don't like the routing around an instance of the macro you can still change it. The routing will generally be optimal, unless you have RAMs within your macro. You can pretend (with very great care) that the RAMS are LUTs , which will allow excellent routing. You will then have to patch the RAMS back in later (perhaps using fpga_editor , or XDL if you have a large number of instances.) Note that XST (VHDL) sometimes doesn't keep RLOCS. This is a bug that I have recently complained about. If you are not using XST , you should have no problems. Best Regards, Mark Taylor 101551.3434@compuserve.com (immediately available for employment should you need help as regards digital hardware on Xilinx devices, or DSP or image processing or Software (NT/C/C++/Asm or uP 4 to 128 bit )Article: 34511
Dave, ----- Original Message ----- From: "Dave Feustel" <dfeustel@mindspring.com> Newsgroups: comp.arch.fpga Sent: Tuesday, August 28, 2001 1:07 PM Subject: Re: FPGA : USB in an FPGA, has anyone done it before? > Felix, > > Have you any plans to implement USB 2.0 in FPGA? yes, definitely. The transaction & protocol layer are more or less the same as USB 1.1, so this is not too critical. However, as reconstruction of the 480Mbps clock inside the FPGA is not feasable, we will use a UTMI compliant transceiver to do so. If you have any plans regarding USB 2.0 that we could be part of, please let me know. Best regards Felix _____ Dipl.-Ing. Felix Bertram Trenz Electronic Duenner Kirchweg 77 D - 32257 Buende Tel.: +49 (0) 5223 49 39 755 Fax.: +49 (0) 5223 48 945 Mailto:f.bertram@trenz-electronic.de http://www.trenz-electronic.deArticle: 34512
Felix, I've been looking for a 32/16/8 bit peripheral parallel interface using USB 2.0. I haven't found any at all. All I've been able to find is ATA IDE interfaces which I don't think I can twist into what I want. An FPGA implementation would be very handy. Dave Feustel "Felix Bertram" <fbertram@gmx.net> wrote in message news:9mg6rl$23oi6$1@ID-31589.news.dfncis.de... > Dave, > > ----- Original Message ----- > From: "Dave Feustel" <dfeustel@mindspring.com> > Newsgroups: comp.arch.fpga > Sent: Tuesday, August 28, 2001 1:07 PM > Subject: Re: FPGA : USB in an FPGA, has anyone done it before? > > > Felix, > > > > Have you any plans to implement USB 2.0 in FPGA? > > yes, definitely. The transaction & protocol layer are more or less the same > as USB 1.1, so this is not too critical. However, as reconstruction of the > 480Mbps clock inside the FPGA is not feasable, we will use a UTMI compliant > transceiver to do so. > > If you have any plans regarding USB 2.0 that we could be part of, please let > me know. > > Best regards > > Felix > _____ > Dipl.-Ing. Felix Bertram > Trenz Electronic > Duenner Kirchweg 77 > D - 32257 Buende > Tel.: +49 (0) 5223 49 39 755 > Fax.: +49 (0) 5223 48 945 > Mailto:f.bertram@trenz-electronic.de > http://www.trenz-electronic.de > > >Article: 34513
Philip Freidin ranted: > [Much valid ranting deleted] > For each of the optimizations that the P&R tools perform, there > are cases where the result is disastrous. One of the still most > compelling reasons to still use schematics, is that there are > reasonably easy ways to inhibit this behaviour. Take, for instance, Exemplar/Leonardo synthesizing Verilog for Virtex-2. It screws up on even the simplest of logic minimization. For example, if you give it: always @(posedge K) Q <= A^B^C^D; // no minimization required Leonardo will "optimize" this as two 4-input LUTS and an FDS. Not only does this use twice as many luts as needed, it increases cycle time, increases routing congestion, and makes the FDS unable to share a slice with a related flip flop. This is not an isolated case. Just about any logic that can be "de-optimized" in this manner will be. Take another example: always @(posedge K) Q[63:0] <= S ? X[63:0] : Y[63:0]; This will synthesize to 128 LUTs and 64 FDS. (The correct answer is 64 LUTS and 64 FD.) I would be far better off using a schematic. With Leonardo, any logic in the critical path has to be instantiated as LUT symbols. If using schematics is like programming in assembly language, then instantiating LUTs is like writing microcode. The people at Exemplar had no clue that this was happening (so they said). They apparently have no clue how to fix it since I submitted the bug report over a month ago. Bottom line: Leonardo is currently un-usable for Virtex-2 designs.Article: 34514
Dave, if you are looking for a stand-alone USB 2.0 device that interfaces to a parallel bus, you might check Cypress. Their FX-2 and SX-2 both interface over a parallel bus. You could also look into NetChips, they have a couple of parts out that interface over a parallel bus too. Cheers, Glen Atkins "Dave Feustel" <dfeustel@mindspring.com> wrote in message news:8%Ni7.7405$xb.5269943@news1.mntp1.il.home.com... > Felix, > > I've been looking for a 32/16/8 bit peripheral parallel interface using USB 2.0. > I haven't found any at all. All I've been able to find is ATA IDE interfaces > which I don't think I can twist into what I want. An FPGA implementation > would be very handy. > > Dave Feustel > > "Felix Bertram" <fbertram@gmx.net> wrote in message news:9mg6rl$23oi6$1@ID-31589.news.dfncis.de... > > Dave, > > > > ----- Original Message ----- > > From: "Dave Feustel" <dfeustel@mindspring.com> > > Newsgroups: comp.arch.fpga > > Sent: Tuesday, August 28, 2001 1:07 PM > > Subject: Re: FPGA : USB in an FPGA, has anyone done it before? > > > > > Felix, > > > > > > Have you any plans to implement USB 2.0 in FPGA? > > > > yes, definitely. The transaction & protocol layer are more or less the same > > as USB 1.1, so this is not too critical. However, as reconstruction of the > > 480Mbps clock inside the FPGA is not feasable, we will use a UTMI compliant > > transceiver to do so. > > > > If you have any plans regarding USB 2.0 that we could be part of, please let > > me know. > > > > Best regards > > > > Felix > > _____ > > Dipl.-Ing. Felix Bertram > > Trenz Electronic > > Duenner Kirchweg 77 > > D - 32257 Buende > > Tel.: +49 (0) 5223 49 39 755 > > Fax.: +49 (0) 5223 48 945 > > Mailto:f.bertram@trenz-electronic.de > > http://www.trenz-electronic.de > > > > > > > > >Article: 34515
Does anybody knows where to find Orcad symbol for Xilinx part ?Article: 34516
Hakon Lislebo wrote: > > I also use a 1 GHz with 512Mbytes of RAM. The RAM is very important so that > the software doesn't have to use the hard-disk. ( About all my 512 Mbytes is > occupied during a routing). > > Hakon Has anyone reading this had any experience with DDR Ram with PAR tools? The thought of a 1.4G Athlon with >512M DDR Ram appeals :-). Nial.Article: 34517
Just testingArticle: 34518
Hi -
we're seeing some 'interesting' behaviour in post-synthesis simulations
of our design for a Xilinx Virtex XCV2000E. We synthesised witout
problems with Synplify 6.3 then fed it to Alliance 3.3.
When we look in the vhdl netlist, we see that the latch in question is
instantiated as 'X_LATCH' components, connected up as you'd expect. The
problem is that when we run the simulation (VHDL netlist with SDF timing
info), after a while everything falls over because of the following
chain of events:
1./ On a rising system clock edge, a controlling state machine changes
state and generates an active enable ('pass') input to the latch (on
it's CLK input). Due to the logic in the state machine, this glitches
low briefly but then comes high again. In other words, after the clock
edge, it goes high, glitches low briefly, then remains at it's intended
high level.
2./ On that same edge, new data are fed to a fairly lengthy
combinational part of the circuit. The outputs of this are used as the
inputs to the bank of latches driven by that enable signal. So after a
while, the latch inputs settle at new values.
3./ Ultimately the situation is this. The latch enable input is active,
and the latch inputs have valid, new values. BUT the outputs of the
latch are undefined (VHDL 'X'), and have been so since shortly after the
glitch on the latch enable. And remain so forevermore.
Incidentally, the X_LATCHes are also connected to a global set/reset
signal, but this is inactive throughout.
This is pretty odd behaviour. The latch is enabled and should therefore
be passing the (perfecly good) values appearing at its inputs.
We've been able to view the .ncd and have a look at one of the slices
containing the offending latches, and it appears perfectly okay. The
enable signal is wired into the clock of one of the slice storage
elements, the data is wired into the data input OK, and the output is
also wired up ok. The storage element is set to be of type latch.
When we put the design into FPGA and try it that way, as far as we can
tell, it's behaviour agrees with that in the PS simulation, in that test
sets that run ok on the PS sim also run ok on the prototype, whilst test
sets that fail on the prototype also fail on the ps sim.
Things only fail when the signals in the system are such that the state
machine generates that glitch - but this should not be a problem for a
true level sensititive latch since the enable signal is always back on
in plenty of time.
So - what's going on? Is the bitfile not properly configuring the
storage element as a latch type? Is the implementation of a latch in
Virtex-E some odd kludge of an edge triggered cell which in some
circumstances can show odd synchronous behaviour? Are we missing
something really obvious?
Any light anyone can shed on this would be greatly appreciated.....
it's pretty disconcerting when you feed a standard component sensible
signals and it doesn't do what you expect...
----------------------------------------------------------------------
chris softley, phone: +44 (0)191 2225775
dept of electrical & email: c.i.softley@ncl.ac.uk
electronic engineering, computer arith/digital design/vhdl/dsp/
newcastle university, uk. approximation/perl/c++/asic/fpga/lns...
high speed logarithmic arithmetic: http://napier.ncl.ac.uk/hsla
Article: 34519Generate it from Xilinx's PAD or PIN file. It's under "tools -> generate part" menu item in OrCAD. It generates the base block which is necessary to edit, but it's better than nothing... Jan "Rémi SEGLIE" <remi.seglie@optrantechno.com> wrote in message news:9mgg8b$16ul$1@news6.isdnet.net... > Does anybody knows where to find Orcad symbol for Xilinx part ? > >Article: 34520
Chris Softley wrote: > > Hi - > we're seeing some 'interesting' behaviour in post-synthesis simulations > of our design for a Xilinx Virtex XCV2000E. We synthesised witout > problems with Synplify 6.3 then fed it to Alliance 3.3. > > When we look in the vhdl netlist, we see that the latch in question is > instantiated as 'X_LATCH' components, connected up as you'd expect. The > problem is that when we run the simulation (VHDL netlist with SDF timing > info), after a while everything falls over because of the following > chain of events: I would guess that you have a delay-dependent asynchronous race condition. I would consider latches in the synthesis output to indicate a design error. You might check for processes sensitive to signals other than clock and reset. State machine outputs should be registered as well. Good luck. --Mike TreselerArticle: 34521
Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote in message news:<qhn14od8yb.fsf@ruckus.brouhaha.com>...
> kevinbraceusenet@hotmail.com (Kevin Brace) writes:
> > Sure, there are some PCI boards that hardwire the decode
> > addresses, but again, according to Appendix G of PCI Local Bus
> > Specification Revision 2.2 states that only legacy devices (i.e., VGA,
> > IDE) can do that.
> > Actually, the legacy devices like VGA or IDE, and has a class code
> > that indicates such a device.
> > So, if you are not VGA, IDE, or other legacy devices that indicates a
> > legacy class code, you should not hardcode addresses, and if you do
> > so, you are violating the specification.
>
> What's wrong with making the PCI POST code display a legacy device, and
> using the appropriate legacy device class code? The use of port 80
> for a POST code has a longer legacy than either VGA or IDE. VGA wasn't
> introduced until 1987; I don't recall when IDE was introduced.
Although it is true that POST display port (I/O address 80H)
has been around longer than VGA or IDE, a Class Code doesn't exist for
such a device.
I read through the PCI Local Bus Specification Appendix D Class Codes
(Page 257 through 265), but there really isn't any appropriate Class
Codes for POST display card unlike VGA or IDE.
I suppose the POST display card should belong to Base Class 08h
(generic system peripherals), but Base Class 08h doesn't have a
Sub-Class or Interface dedicated to a POST display card.
Also, you should note that what I wrote originally was referring to
the question of someone trying to convert an ISA based card to a PCI
one that seems to use an I/O port and an IRQ, and not necessary
talking about the POST display card (topic changed at some point from
a POST display card to how to convert an ISA card to a PCI card).
I guess that if someone wants to build a PCI based POST display card,
it can be built, although it will violate the PCI specification
(hardcoding the I/O address without using a proper Class Code), but
since normally there will be only one such device on the PCI bus
(can't have two or more POST display card on the PCI bus because they
will try to claim the bus simultaneously causing signals to crash),
that won't cause any I/O port conflicts.
Regards,
Kevin
Article: 34522Hi again - I received this response by mail. I'm posting it because it might clear up a few more details of our problem... someone wrote: > I would guess that you have a delay-dependent > asynchronous race condition. We have valid signals at the inputs to a level sensitive latch which are settled and sitting there for an age (almost 1us). The enable signal is active throughout this entire time. So we have data and enable stable at the inputs to the so-called latch for almost 1us. The input isn't coming out. It should. A glitch on the enable which ocurred before the situation I just described seems, somehow, to be the cause of the problem. But this is still not correct behaviour for a level sensitive latch. > I would consider latches in the synthesis > output to indicate a design error. The latches are there very deliberately. They're not necessarily the most elegant of design solutions but in our system we need to keep the inputs at the head of a multicycle combinational path rock-steady, and for a plethora of reasons, we're unable to use edge triggered registers to do this, much as we'd like to. > You might check for processes sensitive > to signals other than clock and reset. > State machine outputs should be registered as well. We have, and they are ;-) Cheers, ChrisArticle: 34523
Dave Feustel wrote: > > Felix, > > I've been looking for a 32/16/8 bit peripheral parallel interface using USB 2.0. > I haven't found any at all. All I've been able to find is ATA IDE interfaces > which I don't think I can twist into what I want. An FPGA implementation > would be very handy. I thought Philips have a USB 2.0 <-> FIFO interface chip, that does CRC and Serialise /deserialise ( ie everything above the 16 bit parallel handshake ) ? -jg
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