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Peter Ormsby wrote: > > >From the FPGA point of view, this is not critical, as long as dont on of > > the two FPGA pins is a ground, VCC or dedicated pin. Unused IO pins are > > tristated by default (unlike Altera parts, where unused pins DRIVE a > > signal :-( > > > > -- > > MFG > > Falk > > > > I'm not sure where you got your information, but that last statement is just > plain WRONG. Not with Maxplus2 it's not. In most of the Altera devices I've used (compiled with Maxplus2) if a pin isn't assigned it is configured as an output and connected to a random internal net. Nial.Article: 33676
Now I 'm using Core Generator 2.1i . I follow the User Guide in Help but now I don't know clearly where to use the command get_model in this software ( in page 4-9 ) . I find out many things in the User Guide not like in the software. Please tell the way to extract file .v from Core Generator 2.1i. All helps will be appreciated. Your sincerely, LUUTHANHTRUNGArticle: 33677
> Since the XC2V6000 devices are about $8000 US each through distribution, maybe > contracting someone to make a board for you to your own specifications is a > cost effective way to achieve your goal. i) It is always better (and cheaper) to use of-the-shelf stuff when you need small quantities. Making my own board is the fall back. ii) The board is to be used as part of a general hardware acceleration platform so the specifications are very simple (lots of connections between the FPGAs). iii) The price for XC2V6000-4FF1152 is less than 3000US$ if you buy it from Insight. Cheers, Rotem. > > > Rotem Gazit wrote: > > > I'm looking for a prototyping board containing 3 (or more) XC2V6000 FPGAs. > > > > Thanks, > > > > Rotem. > Rotem Gazit MystiCom LTD mailto:rotemg@mysticom.com http://www.mysticom.com/Article: 33678
I can't get a signal out of Xilinx Virtex-II 2V100 and 2V40 with a correct duty cycle. I only see this problem in 1.5 and 2.5 voltages mode. I also see the problem on Xilinx Virtex-II Evaluation Kit with a 2V40. As output I use OBUF_LVCMOS15_F_16 for 1.5 V and OBUF_LVCMOS33_F_16. With a frequency about 100MHz is the duty cycle about 35/65. In the test I run the clock through a FF to make a 50/50 duty cycle and with no luck. It is always the high pulse that a shorter than the low, even if I invert the signal. We have asked Xilinx's Technical Support Office United Kingdom every day for two weeks and they can't answer the question they just ask irrelevant questions. For instance, they ask my to do an IBIS simulation on their Evaluation Kit with their chip. Is there any one that have seen a 50/50 duty cycle on a Xilinx Virtex-II 2V100 and 2V40 with about 100MHz and 1.5V I/O ? Is an Altera a better choice for high speed (150MHz) double data rate signals with 1.5 voltage, is there any one that can recommend an FPGA for this job ?Article: 33679
Martin Schoeberl wrote: > > > Interesting. I thought LPM was just an altera thing for AHDL. Are > > all device and tools vendors supporting LPM libraries? > > > > I guess its ok to use LPM functions in brand-neutral code then? > > I also thought that's good news. But I tried today to use LPMs > in Xilinx WebPack but it's not supported: > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= > 1&getPagePath=5163 > > So again two versions for A and X. LPM libraries would solve everyones problems. Wonder why some brands don't conform?Article: 33680
The UK's Educational ECAD User Group is running a workshop as usual in September. This 25th EEUG Workshop will be hosted at Cosener's House, Abingdon, UK on the 19th and 20th of September 2001. The topic for the workshop is "Computer based teaching, learning and assessment for Design Aspects of Electronics and Microelectronics" and it will discuss recent and future developments in this area. Full information is available at <http://www.eeug.org.uk/sep01/>, including a registration form, provisional programme and abstracts of the presentations. -- Tim Forcer tmf@ecs.soton.ac.uk Department of Electronics & Computer Science The University of Southampton, UK Posted on behalf of the EEUG committeeArticle: 33681
But I have no mapper report.Article: 33682
Hi all, I have a problem in my design.My design requests to use the ALTERA's EPM7064 to implement the address latch and the address decode from MCU anda extra SRAM.All my design is implemented with graphic editor.I used Altera's library(74373) to implement address latch.But some address are wrong in read and write the memory. Does anyone have a tip or idea?? Thankx, Jone StvenArticle: 33683
Tomek a écrit : > > But I have no mapper report. You should run it with the -detail option (or ask for a detailed report in the GUI: design/options/optimize and map "create detailed Map report") -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 33684
Yes i did....and it simulates it with no err or warnings..... but....it doesn't give me the right values for ma[] .... which should be the same as upad[].... that i'm feeding in thru the simulator..... instead it gives me some odd values for ma[] ... Could that be due to the clk.... or some delay... cuz... upad[] is an INPUT and ma[] is a dffe variable... so does that matter?? Abhimanyu Rastogi Russell Shaw <rjshaw@iprimus.com.au> wrote in message news:3B68A427.47ED3915@iprimus.com.au... > I can't see a problem. Have you fed it thru the maxplus2 simulator? > > Abhimanyu Rastogi wrote: > > > > Hi all, > > I haveing some trouble with this code I wrote... > > -- > ___ ___ > / /\ / /\ > / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ > /__/ / Victoria, Australia, Down-Under /__/\/\/ > \ \ / http://home.iprimus.com.au/rjshaw \ \/\/ > \__\/ \__\/Article: 33685
Falk <> writes: > So what the hell means > > - as output, driving an unspecified signal???? > I've also seen the same behaviour that Nial describes elsewhere in this thread... threw us off track for a *long* while. We now make a point of explicitly defining the state of all pins, used or unused. > Is there any use for that?? My opinion is, that the software has to > keep its hands of the pins, unless I tell them to do other. So unused > pins should be tristated by default (not after you set a tiny switch > hidden deep down in the 10th option menu :-( > Not nice default behaviour IMHO! Cheers, MartinArticle: 33686
stoneman41@mailcity.com (stoneman) writes: > Hi all, > > I have a problem in my design.My design requests to use the > ALTERA's EPM7064 to implement the address latch and the address decode > from MCU anda extra SRAM.All my design is implemented with graphic > editor.I used Altera's library(74373) to implement address latch.But > some address are wrong in read and write the memory. Does anyone have > a tip or idea?? > Could be a timing problem, difficult to tell without more info. Can you describe the circuit more? MartinArticle: 33687
I haven't been watching this board much lately so I aplogize if this has already been discussed. I heard from a Xilinx distributor yesterday that Xilinx is phasing out the Alliance tools in favor of the ISE package. Can anyone verify this? RJSArticle: 33688
FPGAs are being actively worked with at many universities here in the US. Check out Washington State University and New Mexico State University for starters. "edgar" <pound_euro@altavista.com> wrote in message news:91f37648.0107311030.7c271698@posting.google.com... > heya, > > > This year, I got my Bachelor in computer science. i wanted to > undertake a PhD in the fielld of FPGA, but i have been refused even > that i have my degree with a mark of 65%. > > when i asked the boss there, he told me this is a computer engineering > department and not computer science, i can't accepet you even if you > got 90%!!!! > > i have decided to join a software company, but still wondering on what > he means, > what is the differences between computer science and computer > engineering ? > > > Edgar SArticle: 33690
Use the Altera simulator to see what the datapath looks like as ma[] gets updated and data_word[] gets written to. You might be surprised to find that it "breaks" at some point and you can figure out easily why it happens if you see the events surrounding it. Altera's simulator always was a nice tool particularly for small designs. Abhimanyu Rastogi wrote: > I'm new at this... i thought DFFE or DFF would not make a moajor > difference.... but even after i change dffe to dff it still gives me the > same old values for ma[]..... if u want i can also attach the > correspondaing *.scf file.. > Abhimanyu > John_H <johnhandwork@mail.com> wrote in message > news:3B681795.ECEA1DDB@mail.com... > > You've defined ma[] as DFFE elements (D type flip flop with enable). > > Where's the enable? > > > > > > Abhimanyu Rastogi wrote: > > > > > Hi all, > > > I haveing some trouble with this code I wrote... > > > the pronblem i'm getting is with the values of ma[], wat i'm trying to > do is > > > copy the values od upad[] to ma[] and where ma[] is clocked with up_ale > and > > > it doesn't gimme the write vales after copying it to ma[]... > > > > > > Wat could be the problem? > > > > > > Many thx for the help... > > > > > > Abhimanyu..... > > > > > > Code:-- > > > > > > SUBDESIGN hib_card > > > ( > > > clk, reset :INPUT; > > > > > > --micro inputs ( they already exist ) > > > upad[7..0], /up_cs5, /up_rd, /up_wr, up_ale :INPUT; > > > > > > data_out, band_config[2..0] :OUTPUT; > > > ) > > > > > > VARIABLE > > > moore_state : MACHINE OF BITS (q1, q2, q3) WITH STATES ( > > > S0 = B"101", --hib_data2 > > > S1 = B"100", --hib_data1 > > > S2 = B"011", --hib_data0 > > > S3 = B"010", --hib_status > > > S4 = B"001", --pr_data > > > S5 = B"000"); --pr_status (ignoring the last 2 states for the moment) > > > > > > data_word[21..0] :DFFE; --for storing all 22 bits of address and data > > > ma[7..0] :DFFE; --for storing the data into the reg at every !up_ale > > > in_clk :DFFE; > > > hib :NODE; > > > status :NODE; > > > pll_sel :NODE; > > > p186_read :NODE; > > > p186_write :NODE; > > > hib_read_data2 :NODE; > > > hib_write_data2 :NODE; > > > hib_read_data1 :NODE; > > > hib_write_data1 :NODE; > > > hib_read_data0 :NODE; > > > hib_write_data0 :NODE; > > > hib_write_status :NODE; > > > > > > BEGIN > > > (ma[], data_word[]).clk = !up_ale; --clocks ma, data_word with up_ale, > so > > > that they change data at the same clock > > > ma[] = upad[]; -- saves data from the micro to altera > > > in_clk.clk = clk; > > > in_clk = !in_clk; > > > p186_read = !/up_cs5 & !/up_rd; --sets the flag to read from altera > > > p186_write = !/up_cs5 & !/up_wr; --sets the flag to write to altera > > > moore_state.clk = clk; > > > moore_state.reset = reset; > > > CASE moore_state IS > > > WHEN S0 => > > > hib = VCC; > > > status = GND; > > > data_out = VCC; > > > hib_read_data2 = p186_read & hib & !status; > > > hib_write_data2 = p186_write & hib & !status; > > > data_word[21..16] = ma[5..0]; > > > IF up_ale THEN > > > moore_state = S1; > > > ELSE > > > moore_state = S0; > > > END IF; > > > WHEN S1 => > > > hib = VCC; > > > status = GND; > > > data_out = VCC; > > > hib_read_data1 = p186_read & hib & !status; > > > hib_write_data1 = p186_write & hib & !status; > > > data_word[15..8] = ma[7..0]; > > > IF up_ale THEN > > > moore_state = S2; > > > ELSE > > > moore_state = S1; > > > END IF; > > > WHEN S2 => > > > hib = VCC; > > > status = GND; > > > data_out = VCC; > > > hib_read_data0 = p186_read & hib & !status; > > > hib_write_data0 = p186_write & hib & !status; > > > data_word[7..0] = ma[7..0]; > > > IF up_ale THEN > > > moore_state = S3; > > > ELSE > > > moore_state = S2; > > > END IF; > > > WHEN S3 => > > > hib = VCC; > > > status = VCC; > > > data_out = GND; > > > IF ma[4] THEN > > > band_config[2..0] = ma[2..0]; > > > pll_sel = VCC; > > > ELSE > > > pll_sel = GND; > > > END IF; > > > hib_write_status = p186_write & hib & status; > > > IF up_ale THEN > > > moore_state = S4; > > > ELSE > > > moore_state = S3; > > > END IF; > > > WHEN OTHERS => > > > moore_state = S0; > > > END CASE; > > > END; > >Article: 33691
That is correct Robert. The ISE GUI will replace Design Manager, but will have the same functionality. This is not true just yet, as ISE Alliance will have access to Design Manager (dsgnmgr.exe) through the %XILINX%/bin/nt sub-directory in the next major release. The default GUI, however, will be Project Navigator. I hope this helps. Best regards, Kamal Patel Robert Sefton wrote: > I haven't been watching this board much lately so I aplogize if this has > already been discussed. > > I heard from a Xilinx distributor yesterday that Xilinx is phasing out the > Alliance tools in favor of the ISE package. Can anyone verify this? > > RJSArticle: 33692
Hi, We are curently trying to port the XR16/Xsoc project (www.fpgacpu.org) to a VHDL targeted to the BurchEd Spartan II board (http://www.burched.com) We plan to make our work freely available, but are currently stuck on a problem. The design is a 16 CPU-SOC which interfaced to a parallel port. We have somes on-chip blockrams which serves as ROM, and off-chip asynchronous SRAM whiwh serves as main memory. Our problem is that we get frequent errors when accessing the off-chip SRAM banks. Generally a single bit wrong in a 16 bit data word every 200-300 access. All simulation (RTL,gate-level,post place and route) went fine. Right now, our system is clocked at 1Mhz far below its maximum frequency. Besides, the SRAM Write Enable command output signal is registered (although not in a IOB register) to avoid glitches which could cause wrong write operations. All IOB are configured with SLOW slew-rate and drive 12mA (default IOB config) We have been beating our heads on this problem for almost a week now, are there any experts around there to offer some tips/ideas/advices ? Thanks, StevenArticle: 33693
Ray Andraka schrieb: > > that has been confirmed by xilinx). Maybe he is using the DLL for both 1x and 2x > clocks and transferring the data between the domains on the same aligned edge > (data book says that's OK, but we've seen problems where unequal loading of the > clock trees has introduced enough skew to make a direct transfer between the > clock0 and clk2x domains unreliable--and that does not change with clock > frequency but will work in some parts and not in others and will work at some > locations but not others on the chip). Since he is unwilling to share his test Hey, what do I hear?? There can be some trouble when using the x1 clock and x2 clock of a DLL and treating them as synchronous?? NOOOOOOO. Iam currently working on a design, where I would like to divide a 28 MHz clock from an XO with the DLL by 4 and simultaneously double the 28 MHz to get 56 MHz. Both clocks go onto global clock buffers. The feedback of the DLL is feed by the 56 MHz clock net. Is this a save design?? Or is it better to use two DLLs, one for dividing down and one for doubling? Or better enter the FPGA with 56 Mhz and just divide by 8? -- MFG FalkArticle: 33694
Olaf Reichenbaecher schrieb: > > Hello all, > > just a simple question: I am concerned what might happen when > I put a Xilinx Virtex part on a board where two package pins > are connected to the same net. > In the FPGA definetely only one of the pins (inputs) is connected to > some logic / clock network. The other is left open / unused. > This is because we a using the same board for different versions > (with different pinouts) of this FPGA. >From the FPGA point of view, this is not critical, as long as dont on of the two FPGA pins is a ground, VCC or dedicated pin. Unused IO pins are tristated by default (unlike Altera parts, where unused pins DRIVE a signal :-( -- MFG FalkArticle: 33695
The BurchED Spartan board is only two layer, and has what seems to me is a fairly poor power/ground layout - I would be much happier to see a real ground 'plane' at least under the chip. Perhaps your problems are related - things happen really fast inside something like a Spartan II and if your decoupling is not perfect ... Dave [ In other respects I think that the board is useful and very good value for money - but if I were laying it out I'd have a solid ground under the chip proper, with all chip grounds connected directly to it, and then place decoupling caps round the edge of the chip on the underside, preferably connecting to a VCC power 'plane' directly under the ground 'plane', giving very short decoupling track lengths.] Dave "Steven Derrien" <sderrien@irisa.fr> wrote in message news:3B697EF9.E5BDF155@irisa.fr... > Hi, > > We are curently trying to port the XR16/Xsoc project (www.fpgacpu.org) > to a VHDL targeted to the BurchEd Spartan II board > (http://www.burched.com) > > We plan to make our work freely available, but are currently stuck on > a problem. The design is a 16 CPU-SOC which interfaced to a parallel > port. > > We have somes on-chip blockrams which serves as ROM, and off-chip > asynchronous > SRAM whiwh serves as main memory. Our problem is that we get frequent > errors when accessing the off-chip SRAM banks. Generally a single bit > wrong in a 16 bit data word every 200-300 access. > > All simulation (RTL,gate-level,post place and route) went fine. > Right now, our system is clocked at 1Mhz far below its maximum > frequency. > Besides, the SRAM Write Enable command output signal is registered > (although not in a IOB register) to avoid glitches which could cause > wrong write operations. > > All IOB are configured with SLOW slew-rate and drive 12mA (default IOB > config) > > We have been beating our heads on this problem for almost a week now, > are there any experts around there to offer some tips/ideas/advices ? > > Thanks, > > StevenArticle: 33696
"Rick Collins" <spamgoeshere4@yahoo.com> wrote in message news:3B67A4B4.29694DFF@yahoo.com... > I am adding some code to a verilog design for debug and I need to access > signals in a remote portion of the design. I have been told that there > is a way to do this in the form of > "top_level.mid_level.low_level.signal_name" where the level names are > module instance names. This works ok in simulation, but I can't get it > to work in synthesis. We are using Synplify. Is this not supported by > this tool? Is this not supported by any synthesis tool? Correct according to what I read last night in the book _Verilog Styles for Synthesis of Digital Systems_ by David Smith and Paul Franzon This book goes into a lot of detail about what doesn't work in synthesis mode. > If this is supported for synthesis, any idea what I am doing wrong? Also > is there a way to use a symbol for the top level part of the name since > we have a top level test bench in the case of simulation and the top > level module name has a unique instance name. Could I use a define such > as `TOP_LEVEL.mid_level... where TOP_LEVEL is a defined symbol? > > Maybe that is what is wrong. In my code I am using the top level module > name since there is no instance name. Is there something I am missing > about the top level name? How does the synthesizer know which module is > the top level? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 33697
david garnett wrote: > > The BurchED Spartan board is only two layer, and has what seems to me is a > fairly poor power/ground layout - I would be much happier to see a real > ground 'plane' at least under the chip. Perhaps your problems are related - > things happen really fast inside something like a Spartan II and if your > decoupling is not perfect ... Is this also a strong issue when the system is clocked below 1MHz ? (sorry I have very little knowledge of PCB layout issues) Thank you, Steven > Dave > > [ In other respects I think that the board is useful and very good value for > money - but if I were laying it out I'd have a solid ground under the chip > proper, with all chip grounds connected directly to it, and then place > decoupling caps round the edge of the chip on the underside, preferably > connecting to a VCC power 'plane' directly under the ground 'plane', giving > very short decoupling track lengths.] > > Dave > > "Steven Derrien" <sderrien@irisa.fr> wrote in message > news:3B697EF9.E5BDF155@irisa.fr... > > Hi, > > > > We are curently trying to port the XR16/Xsoc project (www.fpgacpu.org) > > to a VHDL targeted to the BurchEd Spartan II board > > (http://www.burched.com) > > > > We plan to make our work freely available, but are currently stuck on > > a problem. The design is a 16 CPU-SOC which interfaced to a parallel > > port. > > > > We have somes on-chip blockrams which serves as ROM, and off-chip > > asynchronous > > SRAM whiwh serves as main memory. Our problem is that we get frequent > > errors when accessing the off-chip SRAM banks. Generally a single bit > > wrong in a 16 bit data word every 200-300 access. > > > > All simulation (RTL,gate-level,post place and route) went fine. > > Right now, our system is clocked at 1Mhz far below its maximum > > frequency. > > Besides, the SRAM Write Enable command output signal is registered > > (although not in a IOB register) to avoid glitches which could cause > > wrong write operations. > > > > All IOB are configured with SLOW slew-rate and drive 12mA (default IOB > > config) > > > > We have been beating our heads on this problem for almost a week now, > > are there any experts around there to offer some tips/ideas/advices ? > > > > Thanks, > > > > StevenArticle: 33698
I am having *zero* success getting the Flexlm licensing process for Modelsim to work on my Windows 2000 Pro SP1 Dell system. This in spite of generous help from Model Technology. The first attempt to access Modelsim after each install results in a flexlm error message (latest is 'can't find license file') and an invalidated license. This happens both with Webpack Modelsim and also the full version of Modelsim on CDROM delivered directly from Model. To say that attempting to use Modelsim under these conditions is getting old fast would be a serious understatement. Does the Flexlm licensing and license validation procedure actually *work* on Windows 2000?Article: 33699
Russell Shaw wrote: > > > Interesting. I thought LPM was just an altera thing for AHDL. Are > all device and tools vendors supporting LPM libraries? LPM is mostly an altera initiative, but it is public source. > I guess its ok to use LPM functions in brand-neutral code then? If you have a vendor independent synthesis tool, AND you write the guts of your special function code in the LPM style, then the synth tool can find an appropriate device primitive to put in the gate level netlist. Note that in my example, I stripped out all off the string I/O junk from the edif.org library. For example, if I synth my example code from the top of this thread for brand X I get a single primitive: ram_dq_inclock_readaddclked_16_3_8 For the same code with brand A I get the single primitive: lpm_ram_dq_16_3_8_2_0 --Mike Treseler
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