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Try www.bookfinder.com It links to Alibris and others. I think it searches 1200 book search engines. Clyde Dave Feustel wrote: > Does anyone have a copy of the book listed below that they > > would be willing to sell? > > VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on > a Large RISC Processor Design > By Golze, Ulrich (other contributor) > Published by Springer-Verlag New York, Incorporated (February 1996) > ISBN: 3540600329 Number of pages: 358 > Binding: > Weight: 1.57 lbs. Dimensions: 9.53 in. by 6.39 in. by 1.19 in.Article: 33901
Still No Joy, but that's definitely a fun search engine. "Clyde R. Shappee" <clydes@world.std.com> wrote in message news:3B708882.43CFFADE@world.std.com... > Try www.bookfinder.com > > It links to Alibris and others. I think it searches 1200 book search engines. > > Clyde > > Dave Feustel wrote: > > > Does anyone have a copy of the book listed below that they > > > > would be willing to sell? > > > > VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on > > a Large RISC Processor Design > > By Golze, Ulrich (other contributor) > > Published by Springer-Verlag New York, Incorporated (February 1996) > > ISBN: 3540600329 Number of pages: 358 > > Binding: > > Weight: 1.57 lbs. Dimensions: 9.53 in. by 6.39 in. by 1.19 in. >Article: 33902
This is a multi-part message in MIME format.
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Does the "Quick Start Guide" found at =
http://toolbox.xilinx.com/docsan/2_1i/data/fndtn/fqs/fqs.htm also apply =
to the WebPACK package? If not is there an equivalent manual for the =
WebPACK?
Thank you
Berg
Peter Alfke wrote in message <3B7078B0.EDFEA735@xilinx.com>...
download it from=20
=
http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim.pdf=20
or=20
http://www.xilinx.com/support/sw_manuals/2_1i/download/xsisyn.pdf=20
Peter Alfke, Xilinx Applications=20
Dave Feustel wrote:=20
Could someone please post the URL for Xilinx's free 314-page =
design and sythesis guide?=20
Thanks.
------=_NextPart_000_002E_01C11F70.A363A7E0
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charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD W3 HTML//EN">
<HTML>
<HEAD>
<META content=3Dtext/html;charset=3Diso-8859-1 =
http-equiv=3DContent-Type><!doctype html public "-//w3c//dtd html 4.0 =
transitional//en">
<META content=3D'"MSHTML 4.72.3110.7"' name=3DGENERATOR>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT color=3D#000000 size=3D2>Does the "Quick Start =
Guide" found at=20
<A=20
href=3D"http://toolbox.xilinx.com/docsan/2_1i/data/fndtn/fqs/fqs.htm">htt=
p://toolbox.xilinx.com/docsan/2_1i/data/fndtn/fqs/fqs.htm</A>=20
also apply to the WebPACK package? If not is there an equivalent manual =
for the=20
WebPACK?</FONT></DIV>
<DIV><FONT color=3D#000000 size=3D2></FONT> </DIV>
<DIV><FONT size=3D2>Thank you</FONT></DIV>
<DIV><FONT size=3D2>Berg</FONT></DIV>
<DIV><FONT size=3D2></FONT> </DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 solid 2px; MARGIN-LEFT: 5px; PADDING-LEFT: =
5px">
<DIV>Peter Alfke<PETER.ALFKE@XILINX.COM> wrote in message <<A=20
=
href=3D"mailto:3B7078B0.EDFEA735@xilinx.com">3B7078B0.EDFEA735@xilinx.com=
</A>>...</DIV>download=20
it from=20
<P><A=20
=
href=3D"http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim=
.pdf">http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim.p=
df</A><A=20
=
href=3D"http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim=
.pdf"></A>=20
=20
<P><A=20
=
href=3D"http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim=
.pdf">or</A><A=20
=
href=3D"http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim=
.pdf"></A>=20
=20
<P><A=20
=
href=3D"http://support.xilinx.com/support/sw_manuals/2_1i/download/gensim=
.pdf">http://www.xilinx.com/support/sw_manuals/2_1i/download/xsisyn.pdf</=
A>=20
=20
<P>Peter Alfke, Xilinx Applications=20
<P>Dave Feustel wrote:=20
<BLOCKQUOTE TYPE =3D CITE>Could someone please post the URL for =
Xilinx's=20
free 314-page design and sythesis guide?=20
<P>Thanks.</P></BLOCKQUOTE></BLOCKQUOTE></BODY></HTML>
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Article: 33903"Dave Feustel" <dfeustel1@home.com> writes: > Does anyone have a copy of the book listed below that they > > would be willing to sell? > VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on > a Large RISC Processor Design > By Golze, Ulrich (other contributor) > Published by Springer-Verlag New York, Incorporated (February 1996) > ISBN: 3540600329 Number of pages: 358 > Binding: > Weight: 1.57 lbs. Dimensions: 9.53 in. by 6.39 in. by 1.19 in. I found a few at http://www.addall.com/New/BrowseCompare.cgi?isbn=3540600329 Looks like BOL UK might have one. I found the above site by typing the ISBN into Google. ColinArticle: 33906
>The best design tool-chain is one that has tools that:
>
>1) Don't force you into a GUI
>2) Come with complete and useful documentation to explain the various
>interesting options and switches
>3) Don't force you to use a GUI to generate constraints
>4) Don't force you to use a GUI to see if you've met timing constraints
>5) TELL YOU IF YOU'VE MET TIMING CONSTRAINTS (all of 'em) -- Lattice,
>are you listening?
>6) DON'T FORCE YOU TO USE A CERTAIN ARBITRARY DIRECTORY STRUCTURE. We
>have reasons for setting up our directory trees the way we do.
That's a pretty good list. But I think there is one more very
critical item...
Good documentation for the files so you can write your
own tool/hack to do something you think is important that
the tools don't do yet.
--
These are my opinions, not necessarily my employeers. I hate spam.
Article: 33907In article <9kovh0$ao1$1@cubacola.tninet.se>, danielnilsson@REMOVE_THIShem3.passagen.se says... > Hi. > I need to interface a XILINX XC95 (using 3.3 volts I/O) CPLD to a PC > parallell port. At how high frequency can I expect to transfer data > reliabily, and how should the interface to the CPLD be constructed (using 2 > or maybe 3.5 meter printer cable)? (I guess some simple RC net to eliminate > reflections?) > The main limitation will shurely not be the CPLD or the FPGA. ECP or EPP chips are sending at transfer rates lower then 1 MB/s, which gives you several 100 ns setup time at the CPLD. The main limitation is probabely the operation system on the PC and how you access the parallel port. On Windows NT and 2000 you can not access the HW directly. You need a driver, otherwise every access to the I/O ports will generate a interrupt and this will slow down your transfer rate CONSIDERABLY. There are simple drivers around which allow the access to specified I/O locations, eliminating the SW Trap. (I think one is called DIRECTIO). I have a EPROM simulator where the download times on a NT machine (P2/266) are around 5 minutes, when on an old 386 under DOS it downloads in less then a 60s. Having Schmitt/Triggers at the end of the lines it is a must. > The circuit is intended for a hobby project, and the reason for interfacing > the parallell port to a CPLD is to achieve higher rate when pumping serial > data through the JTAG port of a SA-1100 CPU. The reason I am not using a > FPGA to do the whole thing much better is price and availability (can anyone > tell me where to buy a cheap spartanXL in sweden? btw, is this chipset > supported by the jtag programmer for xc95, and by webpack?) > > > / Daniel Nilsson, M.Sc.EE student > -- Falser Klaus R&D Electronics Department Company : Durst Phototechnik AG Vittorio Veneto Str. 59 I-39042 Brixen Voice : +0472/810235 : +0472/810111 FAX : +0472/830980 Email : kfalser@IHATESPAMdurst.itArticle: 33908
Hi, "Tim" <tim@rockylogic.com.nospam.com> wrote in message news:997213083.16623.0.nnrp-08.9e9832fa@news.demon.co.uk... > Try www.alibris.com > > I have found Mick/Brick, Bell/Mudge/McNamara, and others via this site. > > But they don't have Mead/Conway. Any ideas on that one? > Through http://www.bookfinder.com/ (as suggested by someone else here) I found 3 copies of Mead/Conway (Used of-course). Good Luck. SriniArticle: 33909
Aare Tali a écrit : > Now I'm trying to use the same cable with Spartan-2 > 2S200-PQ208 and WebPack JTAG programmer 3.3WP8, and I can't > get even the device ID out of it. The only ID I got out of the > chip was 11111111... Hi You may have a cable length problme here. I had the very same problme a few weeks ago (I even posted here about it) and I fixed it by shortening the cable between the HC125s and the chip (it's about 3" -7.5cm- now) -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 33910
Hi All, i'm looking for a Description how i can build a Display Card for showing the Postcode from Bios on the PCI Bus. The Card must look for an I/O Write Access on Adress 80H and then display's the data on 2 7seg Display's as HEX. Thank You for any Idea. -- MfG W. Philippi Madex Electronic Components GmbHArticle: 33911
Hi, I've read the previous threads relating to source control for FPGA designs (RCS,CVS,CC etc. etc..) but would like to discuss more of a general topic around this.... Imagine a scenario where there are a number of FPGA designs, each using a number of library designs that themselves can be considered as discrete elements (but not chips). These library designs may be dependant upon other, lower level, library designs. It is possible for more than one chip to use the same library element. Now, if the chips, and libs, are archived in such a way that they have version numbers, then it is possible to have different releases of chips that use different releases of library elements. Also, two different chips may use the same library element, but use different archived (or released) versions of that element. Also, when a design is archived (or released, committed, call it what you want), then we essentially store everything .. not only the source, but the synthesis and (in this case) all the xilinx output files. One of the problems we envisage is that say a chip uses 100 library elements, we need to be able not only to checkout the relevant ones when checking out a chip, but also tell it which versions to checkout if we don't want the latest ... and to tell it which one should be checked for read or write. There's also the problem of design dependancy in that if I update a library element, I need a way of telling which other chips or library elements depends on that modified design. Now, I can envisage a set of scripts that will handle effective checking out and in of chips or libraries. Version tracking could be carried out using some kind of version file and scripting and allow information to be generated that indicates complete design dependancy ... but it's going to be quite alot of work in writing the scripts and we obviously don't want to re-invent the wheel.... On looking at the problem it seems to be a mix of concepts from rcs/vcs to some kind of database object management. Is anyone else doing this kind of thing or do most people work mainly at the source code revision level and handle higher level database management in more of a manual way? Thanks, Gary Cook.Article: 33912
Have you taken a look at Xilinx' new MicroBlaze processor?
http://www.xilinx.com/ipcenter/processor_central/microblaze.htm
The other possibilities are the diffused processors such as
the PowerPC in Xilinx and ARM9 in Altera.
http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Processor+Centr
al
"Jason Stratos Papadopoulos" <jasonp@y.glue.umd.edu> wrote in message
news:9jnstk$4lo$1@hecate.umd.edu...
> From: Jason Stratos Papadopoulos <jasonp@y.glue.umd.edu>
> Subject: prospects for a tiny FPGA supercomputer?
> Newsgroups: comp.arch.fpga
> Organization:
> Summary:
> Keywords:
> User-Agent: tin/1.4.2-20000205 ("Possession") (UNIX) (SunOS/5.7 (sun4u))
>
> Hello. Please pardon the following stack of ignorant questions from a
> software weenie. I know a little about hardware and a little more about
> computer architecture (picked up on the job).
>
> I was amazed when I found out about these guys, who apparently built
> their own little (integer only) vector processor which they intended
> to use for fixed point neural net training.
>
> http://www.icsi.berkeley.edu/real/spert/t0-intro.html
>
> This is a chip with a simple processor core, and 16 enormous vector
> registers (32 x 32-bit words each). The vector registers fed 8 words
> at a time to one of two clusters of 8 pipelined functional units each,
> and the chip had eight 16-bit integer multipliers. The PhD students on
> this project got HP to implement it in about 750,000 gates (1995
> technology), and it beat the pants off the expensive workstations of the
> day at the specialized tasks the chip was designed for.
>
> I was wondering if it would be possible to pack a 64-bit version of this
> kind of vector processor into latter-day programmable logic; specifically
> something with a group of 64-bit ALUs that could do adds, subtracts and
> 64 x 64 bit pipelined integer multiplies as fast as possible. A beast like
> this would be very useful for the very large integer convolutions I
> continually find myself doing, and for which conventional general-purpose
> processors are way too slow for my taste.
>
> If by some chance this is feasible, I've further deluded myself into
> believing that with enough patience I can actually design such a thing in
> my spare time and on a modest budget (say, a few thousand dollars), and
> maybe put it onto a PCB with some fast SRAM memory. Presto, a pygmy super-
> computer.
>
> Am I completely nuts here? Are there low-cost tools that can do a
> synthesis and/or place and route for what even to me sounds like a pretty
> ambitious design? What about tutorials on Verilog/VHDL? Finally, are there
> IP cores for little processors like an ARM7 or older MIPS that would fit
> into a big FPGA? What about processor cores that have a big blob of
> programmable logic on-chip and tons of I/O?
>
> Thanks in advance for any help (or talking me out of this),
> jasonp
>
> PS: Hi Keith!
Article: 33913On Wed, 08 Aug 2001 13:22:48 +0100, Gary Cook <gc@sonyoxford.co.uk> wrote: >I've read the previous threads relating to source control for >FPGA designs (RCS,CVS,CC etc. etc..) but would like >to discuss more of a general topic around this.... [snip description of the sort of thing I do in Clearcase at least a few times each week.] You set up a "view" which contains the appropriate versions of each element. When you are happy with your design, you can label all the elements (after you've checked them in, of course), and then you can always get that exact set of elements back by refering to them by that label. With Clearcase under NT, you can map a view to a drive letter. For example, on my laptop, I have my Z: drive looking at the latest version of everything. My Y: drive looks at my development branch for the particular set of files I'm working on at the moment. When I'm finished, I'll merge them to the main branch and label the lot. Oh, these particular files are shared by an international development team, and Clearcase synchronises everyones views correctly. Well, most of the time, anyway. It's expensive, but if you want to play with the big boys... Regards, Allan.Article: 33914
Hello,
In this code data_word[21..0] is a 22bit word DFF...and the values are
loaded into it at different !up_ale but it seem to not carry forward the
values which it gets from the first clock to the second clock..... like if
in the first clock i say data_word[21..16] = register[5..0] (here
register[7..0] = 00111000) and at the second clock i say data_word[15..8] =
register[7..0] (here register[7..0] = 11001100) and at the third clock i say
data_word[7..0] = register[7..0] (here register[7..0] = 10101010) ....So now
at the end my data_word[21..0] shoudl look like
(data_word[21..0] = 1110001100110010101010)
Ne kind of help would be appreciated.....
Here is the code:--
SUBDESIGN hib_card
(
up_ale, /up_cs5, /up_wr, /up_rd, clk :INPUT;
upad[7..0] :INPUT;
lb_word[7..0], band_config[2..0], data_out, ma[7..0] :OUTPUT;
)
VARIABLE
ma[7..0] :DFFE;
register[7..0] :DFFE;
data_word[21..0] :DFF;
pll_sel :NODE;
p186_read :NODE;
p186_write :NODE;
BEGIN
(ma[], data_word[]).clk = !up_ale;
data_word[].clrn = VCC;
ma[] = (0, upad[7..1]);
p186_write = !/up_cs5 & !/up_wr;
IF p186_write == 0 THEN
register[].clk = !up_ale;
--register[].ena = VCC;
register[].d = upad[];
lb_word[] = register[];
CASE ma[] IS
WHEN H"45" =>
data_word[21..16] = register[5..0];
%IF up_ale THEN
ma[] = H"44";
ELSE
ma[] = H"45";
END IF;%
WHEN H"44" =>
data_word[15..8] = register[7..0];
%IF up_ale THEN
ma[] = H"43";
ELSE
ma[] = H"44";
END IF;%
WHEN H"43" =>
data_word[7..0] = register[7..0];
data_out = VCC;
%IF up_ale THEN
ma[] = H"42";
ELSE
ma[]= H"43";
END IF;%
WHEN H"42" =>
data_out = GND;
IF register[3] THEN
band_config[2..0] = register[2..0];
pll_sel = VCC;
ELSE
pll_sel = GND;
END IF;
%IF up_ale THEN
ma[] = H"41";
ELSE
ma[] = H"42";
END IF;%
WHEN OTHERS =>
ma[] = H"45";
END CASE;
ELSE
p186_read = !/up_cs5 & !/up_rd;
lb_word[] = register[];
END IF;
END;
Article: 33915Hi all, Does anyone here have experience in using the Xilinx Foundation tools with Annapolis Micro Systems WILDCARD? I am looking at using Foundation to develop designs for the WILDCARD and am wondering if 1. This is possible. 2. How "difficult" it is to get the two to work together. Thanks, James.Article: 33916
I'm assuming then that you are NOT using synplicity and modelsim then. I think you have an uphill battle. The libraries have synplicity specific pragmas and attributes, the scripts are set up for synplicity and modelsim. You've got a lot of modifying to do to get to a successful compile, especially if you are using alot of the annapolis components and interfaces. It can be done, but it is a mountain of work to get there. I got around this for one client by doing a top level design that instantiated his design as a black box and put in the required annapolis stuff, pins etc. I compiled the top level in the suggested tools flow and verified it with a simple test circuit. This essentially gives him a pre-compiled socket for his design. Now the client is free to modify his stuff, compile it as a black box under whatever tool he wants. To put it in the design he just puts his edif file where it can be found by the xilinx tools and place and route the wrapper design. James Brennan wrote: > Hi all, > > Does anyone here have experience in using the Xilinx Foundation tools with > Annapolis Micro Systems WILDCARD? I am looking at using Foundation to > develop designs for the WILDCARD and am wondering if > 1. This is possible. > 2. How "difficult" it is to get the two to work together. > > Thanks, > > James. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33917
Hello Yoram, You can also look at the (Xilinx based) board described at: http://www.dalanco.com/avr32.htm Thanks, David Langmann (Marketing & Sales) Dalanco Spry Yoram Rovner wrote in message <62ef4351.0108061133.cab3562@posting.google.com>... >Hello: > >I need an advice on which fpga board buy. Somebody could tell me which >one has best software, documentation support, etc. > >Thanks > > >Yoram Rovner >yoram@puc.clArticle: 33918
Thanks Ray. I don't have access to Synplify nor Modelsim. I do have access to Active-HDL and I read on the Aldec web page that it is now possible to obtain Synplify with Active-HDL. To the best of your knowledge, would this be a better solution than using Foundation? James. Ray Andraka <ray@andraka.com> wrote in message news:3B714E5C.A8EEF4E1@andraka.com... > I'm assuming then that you are NOT using synplicity and modelsim then. I > think you have an uphill battle. The libraries have synplicity specific > pragmas and attributes, the scripts are set up for synplicity and modelsim. > You've got a lot of modifying to do to get to a successful compile, especially > if you are using alot of the annapolis components and interfaces. It can be > done, but it is a mountain of work to get there. > > I got around this for one client by doing a top level design that instantiated > his design as a black box and put in the required annapolis stuff, pins etc. > I compiled the top level in the suggested tools flow and verified it with a > simple test circuit. This essentially gives him a pre-compiled socket for his > design. Now the client is free to modify his stuff, compile it as a black box > under whatever tool he wants. To put it in the design he just puts his edif > file where it can be found by the xilinx tools and place and route the wrapper > design. > > > > James Brennan wrote: > > > Hi all, > > > > Does anyone here have experience in using the Xilinx Foundation tools with > > Annapolis Micro Systems WILDCARD? I am looking at using Foundation to > > develop designs for the WILDCARD and am wondering if > > 1. This is possible. > > 2. How "difficult" it is to get the two to work together. > > > > Thanks, > > > > James. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > >Article: 33919
Bingo! Thanks Colin. "Colin Marquardt" <colin.marquardt@usa.alcatel.com> wrote in message news:ysd6itfznuhq.fsf@sol-cmarquar.pet.usa.alcatel.com... > "Dave Feustel" <dfeustel1@home.com> writes: > > > Does anyone have a copy of the book listed below that they > > > > would be willing to sell? > > > VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on > > a Large RISC Processor Design > > By Golze, Ulrich (other contributor) > > Published by Springer-Verlag New York, Incorporated (February 1996) > > ISBN: 3540600329 Number of pages: 358 > > Binding: > > Weight: 1.57 lbs. Dimensions: 9.53 in. by 6.39 in. by 1.19 in. > > I found a few at > http://www.addall.com/New/BrowseCompare.cgi?isbn=3540600329 > > Looks like BOL UK might have one. > > I found the above site by typing the ISBN into Google. > > ColinArticle: 33920
In article <3B6D92B0.E5BD15C@yahoo.com>, spamgoeshere4@yahoo.com says... > I am looking for a laptop which will be my "everything" PC including > running FPGA design software. It seems that laptops are nearly up to the > task with the possible exception of the memory. I am looking at AMD > Athlon powered units and they don't seem to have much memory and it is > not very fast. Desktop units use 266 DDR memmory while these laptops use > SDRAM 100. The laptops also only support up to 512 MB while desktops go > up to 3 GB. I've been using an IBM ThinkPad A21p (PIII-850 - 512MB) for my "everything" PC since the beginning of the year. Trust me, a high-end laptop is the *only* way to fly. When I go into the lab I take everything with me (I'm always having to look up something in my design). You're right, the PIII laptops only support 512MB because the mobile BX chipset only supports this. I'm sure this is the reason for PC100 too. > Am I correct in thinking that the difference in both speed and quantity > will affect my P&R times severely? Does anyone have an estimate of the > performance hit for using PC100 memory vs. DDR266? I can't answer this directly, but before I had this ThinkPad I had an IBM NetFinity 5000 server (PIII-650 - 768MB PC133) set up *just* for P&R runs. The ThinkPad is faster even when I'm doing other work on it (though I normally run P&R overnight). > It does seem that AMD can't shake the low end image they have in the > laptop market. The Athlon is the screamer chip in laptops and yet the > PIIIs are in the high end units with the bells and whistles such as the > higher resolution LCDs and the larger memories. I'm a well known AMD fan, but wouldn't give up the bells and whistles on this A21p for anything. In particular, the 1600x1200 LCD display. I also have a graphics card in a docking station and run a secondary 20" display (combined 3200x1200 desktop). I can keep all of the ModelSim windows, along with my synthesis tools/VHDL editor open on the LCD and move the ModelSim waveform window to fill the entire secondary display. Of course, I don't haul the secondary display around with me. ;-) ---- KeithArticle: 33921
Hello Dave, I assume that you need to assign that input to a GCLK pin because XST is inferring a input global clock buffer for that signal, maybe due to a high fanout for that signal or it actually being a clock. If you want to LOC that input to a regular IOB, then that type of input buffer can not be used. Therefore, I believe you could instantiate an IBUF then a BUFG in your HDL code for this input. The IBUF will allow the input to be LOC'd to a regular I/O and BUFG will place it on the global routing lines. I hope this helps. Best regards, Kamal Patel Speedy Zero Two wrote: > Hi All, > > I have a design which the Webpack software gives me an error, which requires > me to assign a specific input to a GCLK pin. > I have reasons why but to be concise, I want to assign it to a normal I/O. > > How can I force the software to allow it to be routed to the I/O pin I have > specified in the UCF file. > > In the past I have used, > assign myroute = dummy ? mypin : 1'bz; > where myroute goes to the internal logic from mypin but there must be an > easier way. > > Cheers > DaveArticle: 33922
Hal Murray wrote: > > >The best design tool-chain is one that has tools that: > > > >1) Don't force you into a GUI > >2) Come with complete and useful documentation to explain the various > >interesting options and switches > >3) Don't force you to use a GUI to generate constraints > >4) Don't force you to use a GUI to see if you've met timing constraints > >5) TELL YOU IF YOU'VE MET TIMING CONSTRAINTS (all of 'em) -- Lattice, > >are you listening? > >6) DON'T FORCE YOU TO USE A CERTAIN ARBITRARY DIRECTORY STRUCTURE. We > >have reasons for setting up our directory trees the way we do. > > That's a pretty good list. But I think there is one more very > critical item... > > Good documentation for the files so you can write your > own tool/hack to do something you think is important that > the tools don't do yet. Or, put another way, good documentation for the files so you canb write your own tool/hack to do something from the command line you think is important that the tools will only do from the GUI! -aArticle: 33923
Dave Feustel wrote: > > Thanks Peter! > > I'm finally, with help from Tony at Burched and a few others, within sight of downloading > and testing my first FPGA. FPGA development is a *lot* more complicated > than any software development I've ever done! > > But learning how to do it's going to be worth the effort You can make it even more complicated by designing the board the FPGA solders onto! -andyArticle: 33924
To the "diffused processor" camp, be sure to look at the Triscend
Configurable System-on-Chip (CSoC) devices, which unlike the others
mentioned, are actually shipping today.
Triscend E5 CSoC (Embedded Applications)
========================================
Accelerated 8051 8-bit microcontroller, 2-channel DMA, 8K to 64K
on-chip RAM, 3K to 40K gates of programmable logic.
http://www.triscend.com/products/indexe5.html
Triscend A7 CSoC (Embedded Processing Applications)
===================================================
ARM7TDMI 32-bit RISC CPU, 4-channel DMA, Flash and SDRAM controller,
8K cache, 16K on-chip RAM, 5K to 40K gates of programmable logic.
http://www.triscend.com/products/indexa7.html
"rodger" <rodger@bit.bucket> wrote in message news:<aQac7.133$T3.191081984@news.frii.net>...
> Have you taken a look at Xilinx' new MicroBlaze processor?
>
> http://www.xilinx.com/ipcenter/processor_central/microblaze.htm
>
> The other possibilities are the diffused processors such as
> the PowerPC in Xilinx and ARM9 in Altera.
>
> http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Processor+Centr
> al
>
> "Jason Stratos Papadopoulos" <jasonp@y.glue.umd.edu> wrote in message
> news:9jnstk$4lo$1@hecate.umd.edu...
> > From: Jason Stratos Papadopoulos <jasonp@y.glue.umd.edu>
> > Subject: prospects for a tiny FPGA supercomputer?
> > Newsgroups: comp.arch.fpga
> > Organization:
> > Summary:
> > Keywords:
> > User-Agent: tin/1.4.2-20000205 ("Possession") (UNIX) (SunOS/5.7 (sun4u))
> >
> > Hello. Please pardon the following stack of ignorant questions from a
> > software weenie. I know a little about hardware and a little more about
> > computer architecture (picked up on the job).
> >
> > I was amazed when I found out about these guys, who apparently built
> > their own little (integer only) vector processor which they intended
> > to use for fixed point neural net training.
> >
> > http://www.icsi.berkeley.edu/real/spert/t0-intro.html
> >
> > This is a chip with a simple processor core, and 16 enormous vector
> > registers (32 x 32-bit words each). The vector registers fed 8 words
> > at a time to one of two clusters of 8 pipelined functional units each,
> > and the chip had eight 16-bit integer multipliers. The PhD students on
> > this project got HP to implement it in about 750,000 gates (1995
> > technology), and it beat the pants off the expensive workstations of the
> > day at the specialized tasks the chip was designed for.
> >
> > I was wondering if it would be possible to pack a 64-bit version of this
> > kind of vector processor into latter-day programmable logic; specifically
> > something with a group of 64-bit ALUs that could do adds, subtracts and
> > 64 x 64 bit pipelined integer multiplies as fast as possible. A beast like
> > this would be very useful for the very large integer convolutions I
> > continually find myself doing, and for which conventional general-purpose
> > processors are way too slow for my taste.
> >
> > If by some chance this is feasible, I've further deluded myself into
> > believing that with enough patience I can actually design such a thing in
> > my spare time and on a modest budget (say, a few thousand dollars), and
> > maybe put it onto a PCB with some fast SRAM memory. Presto, a pygmy super-
> > computer.
> >
> > Am I completely nuts here? Are there low-cost tools that can do a
> > synthesis and/or place and route for what even to me sounds like a pretty
> > ambitious design? What about tutorials on Verilog/VHDL? Finally, are there
> > IP cores for little processors like an ARM7 or older MIPS that would fit
> > into a big FPGA? What about processor cores that have a big blob of
> > programmable logic on-chip and tons of I/O?
> >
> > Thanks in advance for any help (or talking me out of this),
> > jasonp
> >
> > PS: Hi Keith!
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