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Basically anything you can dream up a digital circuit for. The FPGA is
just a sea of uncommitted logic that you can wire up for just about
anything your little heart desires. We are typically pushing FPGAs for
performance and functionality. Our recent stuff includes several
weather radar demodulator/processors, soft radio recievers, a spectrum
analyzer, HDTV resizing, reformatting and encryption, and other
applications.
Samuel Bogale wrote:
> Can someone suggest ideas what FPGA can be used for?
>
> -Sam
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36501
Depends on your circuit. VHDL is just the language to describe your
circuit.
Banana wrote:
> Ok, the question in another form :
>
> Normally How you send the coefficient to a filter in VHDL ???
>
> Thanks
>
> Banana
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36502
I don't know (nor do I really want to) your intended circuit topology. If this is
just a behavioral thing, then you could use an array with all 3 sets of coefficients,
and index which part of the table you use by adding an offset to the table address.
The table can be passed as an array of integers, either through a generic, through a
signal, or through a package. The type for the array has to be defined in a package
that is referenced by your entity so that the type definition is done before it needs
to be used in the entity block.
Banana wrote:
> I have a filter and want to use it with three different set of
> coefficients, I'm not sure
> about the vhdl implementation of this, I arrange the following :
>
> 1) I define a package SRRC_coeffs where I define the coeff type and
> the coeffs type, here it is :
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_signed.all;
>
> package SRRC_coeffs is
> subtype coeff is std_logic_vector(11 downto 0);
> type coeffs is array(1 to 42) of coeff;
> end SRRC_coeffs ;
>
> 2) I define an entity named coeffs_selector in this way :
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_signed.all;
> use work.SRRC_coeffs.all;
>
> entity coeffs_selector is
> port( coeffs_sel : in std_logic_vector( 1 downto 0);
> coeffs_SRRC : out coeffs
> );
> end coeffs_selector;
>
> architecture coeffs_selector_arch of coeffs_selector is
>
> Constant coeffs_SRRCx3 : coeffs := coeffs'(
> coeff'("111111100010") , -- 1
> coeff'("111111111100") , -- 2
> coeff'("000001000001") , -- 3
> -- .....................
> coeff'("000000000000")); -- 42
>
>
> Constant coeffs_SRRCx4 : coeffs := coeffs'(
> coeff'("111111100110") , -- 1
> coeff'("111111110001") , -- 2
> coeff'("000000011010") , -- 3
> -- .....................
> coeff'("000000000000")); -- 42
>
>
>
> Constant coeffs_SRRCx6 : coeffs := coeffs'(
> coeff'("000000000110") , -- 1
> coeff'("111111110011") , -- 2
> coeff'("111111100010") , -- 3
> -- .....................
> coeff'("000000000110")); -- 42
>
> begin
>
> with coeffs_sel select
> coeffs_SRRC <= coeffs_SRRCx3 when "00",
> coeffs_SRRCx4 when "01",
> coeffs_SRRCx6 when others ;
> end coeffs_selector_arch;
>
> 3) On the filter where arrive the coefficient bus I've something like
> this :
>
> library IEEE;
> use IEEE.std_logic_1164.all;
> use work.SRRC_coeffs.all;
>
> entity SRRC_x_N is
> port(
> SRRCxN_coeffs : in coeffs;
> clk_div_n : in STD_LOGIC;
> in_fir_MSB : in STD_LOGIC;
> reset : in STD_LOGIC;
> count_n : in STD_LOGIC_VECTOR (2 downto 0);
> polyphase_out : out STD_LOGIC_VECTOR (11 downto 0)
> );
> end SRRC_x_N;
>
> architecture SRRC_X_N of SRRC_x_N is
>
> signal COEFF_1 : coeff ;
> signal COEFF_2 : coeff ;
> signal COEFF_3 : coeff ;
> -- ...............
> signal COEFF_42 : coeff ;
>
> component FIR_1
> port (
> clk_div_n : in STD_LOGIC;
> coeff_a : in coeff;
> coeff_b : in coeff;
> coeff_c : in coeff;
> coeff_d : in coeff;
> coeff_e : in coeff;
> coeff_f : in coeff;
> coeff_g : in coeff;
> in_fir_MSB : in STD_LOGIC;
> reset : in STD_LOGIC;
> out_fir : out STD_LOGIC_VECTOR (11 downto 0)
> );
> end component ;
>
> begin
> coeff_1 <= SRRCxN_coeffs(1);
> coeff_2 <= SRRCxN_coeffs(2);
> coeff_3 <= SRRCxN_coeffs(3);
> -- ...............
> coeff_42 <= SRRCxN_coeffs(42);
>
> U1 : FIR_1
> port map(
> clk_div_n => clk_div_n,
> coeff_a => coeff_1,
> coeff_b => coeff_2,
> coeff_c => coeff_3,
> coeff_d => coeff_4,
> coeff_e => coeff_5,
> coeff_f => coeff_6,
> coeff_g => coeff_7,
> in_fir_MSB => in_fir_MSB,
> out_fir => to_in_0,
> reset => reset
> );
>
> -- ...............
>
> end SRRC_X_N;
>
> AND FINALLY HERE ARE MY QUESTION :
> A) Aldec don't permit me to do directly the assignment
> U1 : FIR_1
> port map(
> coeff_a => SRRCxN_coeffs(1);
> .......
> );
>
> I can't understand why and if there is another solution to avoid
> this double assignment
>
> B) there's a clever way to do this assignment of three different set
> of coefficients to the filter ??
>
> Thanks for your help
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36503pete dudley wrote: > > Our bread and butter decoupling cap is .01uF (10nF) 0805 surface mount, like > 1 per 4 VCC on fpga's, and we back them up with a few larger caps up to 10uF > tantalums. > > We use terminated differential signalling for the high speed stuff if > possible to cancel the ground bounce and use slew rate control on the rest. > > On the highest end of the switching spectrum the ground/power planes help > you and my guess is that 100pF or smaller chip caps do nothing for you. > > Once we built some multiprocessor boards that ran about 150MHz but the caps > were bad so we removed all of them. The boards ran fine without any > decoupling. I'd like to try that experiment again with high speed fpga's. > > I like Austin's idea of tuning the caps to the operating frequency. With *thin* layers (such as in 8 layer boards etc), all the caps can be left off except one electro per board. The VCC and GND planes must be adjacent to provide very low planar transmission line impedance (lumped capacitance is meaningless at fast edges). A bit of track to bypass caps and vias hardly matters relative to the inductance in many internal bond wires.Article: 36504
Is it possible to use the SLOW constraint on a SpartanXL output? The Constaints guide says that SLOW is not applicable to SpartanXL's, yet the SpartanXL datasheet talks about setting the slew rate to slow. I tried it and on a scope, there was no difference in the edges of my outputs. Anyone know if I can set a slow slew rate on my outputs? Thanks, DaveArticle: 36505
Thanks RA, that works good. I thought of using a loop, but thought a synthesis tool wouldn't like things like 'while'... Ray Andraka wrote: > > THis is one I wrote a few years ago. I keep it in my common library so > that it is always available. > > function Log2( input:integer ) return integer is > variable temp,log:integer; > begin > temp:=input; > log:=0; > while (temp /= 0) loop > temp:=temp/2; > log:=log+1; > end loop; > return log; > end function log2; > > Russell Shaw wrote: > > > Hi all, > > > > There's an exponent operator (**), but no log-base-2 (from what > > i could see). Such a function (with integer result) would be useful > > would it not?: > > > > constant MAXADDR: natural:=1000; > > . > > . > > . > > signal addrcntr:unsigned(LOG2(MAXADDR) downto 0); > > > > LOG2 should round upwards. > > > > Could a function be written to do it?Article: 36506
I think I found the answer, I have to use SLEW = SLOW as the contstaint. "Dave Brown" <dbrown@novatel.ca> wrote in message news:9shrga$4rf$1@pallas.novatel.ca... > Is it possible to use the SLOW constraint on a SpartanXL output? The > Constaints guide says that SLOW is not applicable to SpartanXL's, yet the > SpartanXL datasheet talks about setting the slew rate to slow. I tried it > and on a scope, there was no difference in the edges of my outputs. Anyone > know if I can set a slow slew rate on my outputs? > Thanks, > Dave > > >Article: 36507
This function is not intended to synthesize directly into hardware, rather it
is used to generate constants for synthesized hardware. Typically for sizing
a bus to a maximum value or setting the number of layers in a tree
structure. A hardware Log2 is a first '1' detect and encoder, or cna be done
with a normalizing shifter.
Russell Shaw wrote:
> Thanks RA, that works good. I thought of using a loop, but
> thought a synthesis tool wouldn't like things like 'while'...
>
> Ray Andraka wrote:
> >
> > THis is one I wrote a few years ago. I keep it in my common library so
> > that it is always available.
> >
> > function Log2( input:integer ) return integer is
> > variable temp,log:integer;
> > begin
> > temp:=input;
> > log:=0;
> > while (temp /= 0) loop
> > temp:=temp/2;
> > log:=log+1;
> > end loop;
> > return log;
> > end function log2;
> >
> > Russell Shaw wrote:
> >
> > > Hi all,
> > >
> > > There's an exponent operator (**), but no log-base-2 (from what
> > > i could see). Such a function (with integer result) would be useful
> > > would it not?:
> > >
> > > constant MAXADDR: natural:=1000;
> > > .
> > > .
> > > .
> > > signal addrcntr:unsigned(LOG2(MAXADDR) downto 0);
> > >
> > > LOG2 should round upwards.
> > >
> > > Could a function be written to do it?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36508We had one in .18u standard cell asic process at 24MHz (24M pixels input rate). I'm sure it would have gone faster, but that was all we needed for our motion JPEG app (30fps). FPGA version (HDL not optimized for FPGA) ran at 6MHz. Regards "Seb" <someone@microsoft.com> wrote in message news:<E5VG7.47306$88.5467995@zwoll1.home.nl>... > Hi group(s) > > regarding any JPEG standard (JPEG, JPEG2000, JPEG-LS,...) what bitrates can > be obtained with current implementation technologies (DSP, FPGA, ASIC)? > > Indications and estimations are also welcome. > > cheers > SebArticle: 36509
You might want to check out the QL5064 from QuickLogic www.quicklogic.com . They have integrated a Master/ Target 64bit 66 Mhz PCI core into an OTP FPGA. The device has a built in 4 channel (2 XMIT, 2 RCV) DMA Controller along 74K Gates of programmable user logic. There is no NRE charge for using the core and they have an RDK board available for evaluation. You could easily migrate the CPLD logic into the FPGA an also have the PCI functionality in a single device. Chuck "Alex Rast" <arast@inficom.com> wrote in message news:ANEE7.153$FU5.365042@news.uswest.net... > Lattice has a core on their site for 32-bit PCI, but I'm wondering if there is > available from Lattice or third parties a 64-bit core. It would be ideal if it > can run at 66MHz to boot. I'm looking to target an ispLSI8600VE. Such a core > would be helpful because it would let me save an additional chip on our > circuit board. Right now we're using a different (much smaller) CPLD on our > board for other, non-PCI functions. I'm getting ready to design the second > revision. I'm leaning towards the Lattice chip because I've been unsatisfied > with the s/w tools for the chip I have now, and because I really could use the > internal tristate busses on the 8000 series. The 8600VE is way, way overkill > in terms of macrocell density as a direct replacement for our current CPLD, > but if I could integrate the PCI core onto the chip as well then I think it's > justifiable. > > BTW, anybody out there have any experience with Lattice's tools? What are your > thoughts on them? > > Alex Rast > arast@qwest.net > arast@inficom.comArticle: 36510
Tim Stewart wrote: > > I have a file that was written for Philips SNAP compiler that I would > like to modify. The file was written for the 18V8Z35N, which > apparently is now obsolete. The ICT 18CV8 PEEL device is supposedly a > direct replacement but seems I now have to learn a new compiler (i.e., > ICT's WinPLACE). The quickest solution would be to obtain a copy of > SNAP since I do have some 18V8Z35N's left. Anyone know where I can > get a copy of SNAP? > > Thanks in advance, > > Tim I have Slice on 5 1/4 floppies, but not sure I can read them anymore :-) You could check AtmelCUPL V4.8, I think is still on their WEB, as that used to support 18V8Z ( For a while Atmel cross licenced with Philips ) The ICT ones have different fuse maps. -jgArticle: 36511
I recently had the link
http://www.howell1964.freeserve.co.uk/ZX81/ZX81_FPGA/ZX81_FPGA.htm
pointed out to me, as I love the ZX81 and happen to have a bag of the
XC3042 used to replace the ULA in this design, I am thinking of getting
some boards made and putting together some machines.
Is there much interest? Obviously the more the cheaper. I am in
Australia but postage of the PCB should not be too expensive.
I have not started on this yet, but once I get some more info it should
not take long at all and having some feedback from others interested
will help me to scale the cost of making boards down.
cya, Andrew...
Article: 36512Yes. It is possible and very useful. One can have a test bench that is completely driven by vectors, easily edited by a text editor. Many texts outline how to do this. Clyde Andrew Gray wrote: > Hi > > Is it possible to read a data file into a test bench and use it as one of > the data inputs to your design? > Is it possible to write from one of the outputs of your design into a file? > > Thanks > > AndrewArticle: 36513
Hi, How can I synthesize a project consisting of both vhdl and verilog files in Synplify? My top level file is a vhdl file and I want to instantiate a module written in verilog file in my top-level vhdl file. Thanks in advance. Servan -- Posted from [193.140.73.215] via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 36514
"Dave Brown" <dbrown@novatel.ca> schrieb im Newsbeitrag news:9shrga$4rf$1@pallas.novatel.ca... > Is it possible to use the SLOW constraint on a SpartanXL output? The > Constaints guide says that SLOW is not applicable to SpartanXL's, yet the AFAIK SLOW is the default setting for all outputs. > SpartanXL datasheet talks about setting the slew rate to slow. I tried it > and on a scope, there was no difference in the edges of my outputs. Anyone ;-)) Did you really do a high-speed measurement? Or just hooked up a probe to the output? The difference between SLOW and FAST is not 20ns, its maybe somewhere 2 ns. To see that, use a fast scope (>500MHz) and a fast probe. These 10:1 probes wont work here. -- MfG FalkArticle: 36515
Hi all, I compiled a vhdl design with leonardo/maxplus2 into an acex 1k30 device, and found that as well as the normal 3.3V outputs, there were also some pulses at 1.5V and 0.3V. The pins are unloaded. The signals come from a bit of code i've been trying to debug. Can tools let these kinds of conflicting designs happen without warnings?Article: 36516
Hi all, I compiled a vhdl design with leonardo/maxplus2 into an acex 1k30 device, and found that as well as the normal 3.3V outputs, there were also some pulses at 1.5V and 0.3V. The pins are unloaded. The signals come from a bit of code i've been trying to debug. Can tools let these kinds of conflicting designs happen without warnings? There's no tristate buses or gates in the design, and only one clock.Article: 36517
in article 3BEC9A9B.2D0EA6EB@touch88.com.au, McMeikan at mcmeikan@touch88.com.au wrote on 11/10/01 3:10 AM: > I recently had the link > http://www.howell1964.freeserve.co.uk/ZX81/ZX81_FPGA/ZX81_FPGA.htm > pointed out to me, as I love the ZX81 and happen to have a bag of the > XC3042 used to replace the ULA in this design, I am thinking of getting > some boards made and putting together some machines. > > Is there much interest? Obviously the more the cheaper. I am in > Australia but postage of the PCB should not be too expensive. > > I have not started on this yet, but once I get some more info it should > not take long at all and having some feedback from others interested > will help me to scale the cost of making boards down. I know a few Speccy users in Oz who may be interested. If I could make a suggestion, since you can build it any way you want, it might be worthwhile having a switchable ROM with ZX80, ZX81, and TreeForth as options, and the RAM can easily be extended to 64K. The German group ZX-Team probably has a lot of helpful info on this kind of thing, and may even be interested in buying a few boards but I can't remember their web or email address off had - try google. -(another) AndrewArticle: 36518
Andrew Owen wrote: > iI know a few Speccy users in Oz who may be interested. If I could make a > suggestion, since you can build it any way you want, it might be worthwhile > having a switchable ROM with ZX80, ZX81, and TreeForth as options, and the > RAM can easily be extended to 64K. The German group ZX-Team probably has a > lot of helpful info on this kind of thing, and may even be interested in > buying a few boards but I can't remember their web or email address off had > - try google. Putting ZX81 into google.com gave 12,000 hits ( in 0.1 sec ). Sorted by # of references. More than you ever want to know. Have fun ! Peter AlfkeArticle: 36519
ndeshmukh@yahoo.com (nitin) writes:
> Anybody have any ideas why Virtex II CLB has two carry chains passing
> through it linking two slices and each and propagating in columns from
> top to bottom...?
>
> Why didn't they link all fourslices in just one chain and joined CLBs
> in one column together and so on in different columns...
Well this is spaeculation (but well founded).
In the original Virtex there ae 2 slices and also 2 carry chains,
each going CLB to CLB taking only one slice per CLB.
Studying the info in XAPP151 is becomes obvious that the actial
transistors are layed out in an "butterfly" configuration, with the 2
slices left and right of the routing!
Sort of like this:
.----|----|||||----|----.
| .--|--. ||||| .--|--. |
| | C | ||||| | C | |
| `--|--' ||||| `--|--' |
| Slice 1 ||||| Slice 0 |
| | ||||| | | CLB
| | ||||| | |
-----|-----||------|-----
-----|-------|-----|-----
-----|------|||----|-----
-----|-----||------|----- routing - and |
-----|-------||----|-----
-----|----||-------|-----
| | ||||| | |
`----|----|||||----|----'
carry1^ ^carry0
So having carry going through both slices would require it to meander
through the chip, massively increasing distance and so slowing it down.
I suspect Virtex-2 to have 2 slices each side of routing, so I assume
this to also apply there.
> It would be nice if some one with some insight into this matter can
> shed some light on it...
Hope it helped.
--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer
- Intellectual Property is Intellectual Robbery
Article: 36520Hi, Can you show me how to do it?Or what buttons to push in the software? Thank you very much! sincerely ------------- Kuan Zhou ECSE department On Thu, 8 Nov 2001, Falk Brunner wrote: > > "Kuan Zhou" <zhouk@rpi.edu> schrieb im Newsbeitrag > news:Pine.SOL.3.96.1011108021708.6365A-100000@rcs-sun1.rcs.rpi.edu... > > Hi, > > I did a fir design but don't know what's the critical > > path in my design.Can Xilinx tool has someway to mesure and > > recognize it? > > Depends on your definition of "critical". The tools can "only" find the path > with the longest delay in a synchronous design. What they cant do, is to > look for bad design style (except detecting gated clocks or so). > > -- > MfG > Falk > > > > > >Article: 36521
Use "Timing Analyzer" after "Implement". The tool will generate a report showing the path delays. Jim "Kuan Zhou" <zhouk@rpi.edu> wrote in message news:Pine.A41.3.96.1011110151214.22494A-100000@cortez.sss.rpi.edu... > Hi, > Can you show me how to do it?Or what buttons to push in > the software? > > Thank you very much! > > sincerely > ------------- > Kuan Zhou > ECSE department > > > On Thu, 8 Nov 2001, Falk Brunner wrote: > > > > > "Kuan Zhou" <zhouk@rpi.edu> schrieb im Newsbeitrag > > news:Pine.SOL.3.96.1011108021708.6365A-100000@rcs-sun1.rcs.rpi.edu... > > > Hi, > > > I did a fir design but don't know what's the critical > > > path in my design.Can Xilinx tool has someway to mesure and > > > recognize it? > > > > Depends on your definition of "critical". The tools can "only" find the path > > with the longest delay in a synchronous design. What they cant do, is to > > look for bad design style (except detecting gated clocks or so). > > > > -- > > MfG > > Falk > > > > > > > > > > > > >Article: 36522
hi,
I am in need of some ideas about reconfigrable routers( IP )
using FPGA's.
Can some one point the door. Although i have got some papers from
google i could not digest it.
Ramnath
Article: 36523I have a Xilinx XS40-05XL fpga. i see that it has an onboard 8031 which is interesting because i needed an 8051 anyway. i need a 256 byte ram. i did a search on google groups and found a discussion where there was a disagreement on whether this 8031 has 128bytes RAM or 256.Article: 36524
This is a bug that I have noticed too, but have not had the time to report it to Xilinx yet. Could you please report it !!! Additional info: It seems to be triggered by turning on the "try to improve timing after routing is completed" switch. I believe the "-d n" is such an example, as is the new "-e n" switch. Leaving these out does not give as good a result, but the incorrect error message goes away. Philip On Mon, 5 Nov 2001 10:19:29 -0700, "Dave Brown" <dbrown@novatel.ca> wrote: >Hi, > When I run place and route using foundation ISE 4.1 (using FPGA Express >as synthesis tool), I get the report that the submitted design did not meet >timing requirements, those requirements with an asterix were not met. Then, >in the list of timing requirements, none have an asterix, and at the >completeion of place and route, it says all timing requirements met, 0 >errors. Same thing if I look at the static timing report, it says all >constaints met. What gives? Is there a timing error in there? Seems like >there isn't, anyone else noticed this? >Thanks, >Dave > > Philip Freidin Fliptronics
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