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Your can use the lookup tables in Xilinx Virtex/VitexII as shift registers. For each LUT you can generate up to a 16 clock delay. Given that your have approximately the same number of flip-flops available as LUTs it is far more efficient to use the LUT (SRL16 mode). The only limitation is that you usually only have one O/P from a SRL16 to use, i.e. adjacent bits not accessable. John Adair Enterpoint Ltd. Unit 4 Malvern Hills Science Park Geraldine Road Malvern Worcestershire United Kingdom www.enterpoint.co.uk The views expressed in this message are those of the writer and not necessarily those of Enterpoint Ltd.. The use of information in this message is without warranty and persons using the information are advised to make their own checks as to it's validity. No responsibility will be accepted for any incorrect, inaccurate or missleading information supplied. mehmeto <mehmetozcelebi@turk.net> wrote in message news:e6ae63f0.0111140035.3d843044@posting.google.com... > Hi, > I have a similar problem like srinas has. > The convolutional interleaver for ATSC has 52 lines and needs > (51x52)/2=1326 delay elements. If the input is 8 bit then 1326x8=10608 > delay elements are required. The required number of Flip flops for a 4 > symbol delay is 10608x4 = 42432. This is quite large. > The same complexity is also valid for DVB interleavers. > Is there any way to reduce the Flip Flop count? I know there are > megafunctions for altera and xilinx devices, but they are commercial. > > ThanksArticle: 36651
Jim Bittman wrote: > being able to run the CoreGen (because of the Pentium-4 bug), switching ^^^^^^^^^^^ What bug is this ?Article: 36652
Hi, I'm interested in exploring the image processing potential of using FPGAs within high-speed video cameras. Initially I would like to get an FPGA prototyping/development/evaluation kit working within the PC itself. Features I would like: -PCI-card-based, to allow easy I/O to/from PC memory. -on-card memory to store image data and results. At least 8 MB, preferably more. -Virtex II device (2 million gates, or more). -Some FPGA I/O pins accessible through a header/connector on the PCI-card. Does anyone know if such a card, or similar, exists? Are there any other important features I should look for? Thanks David Eadie, Computer Vision and Robotics Research Group, Dept. of Computer Science, Trinity College Dublin.Article: 36653
I do not think that 6Mhz is going to cause too many problems even for dodgy
wired prototypes.
Nice looking spartan board tho, definitely something to save up for.
As I have a quantity of 3042 as well as 3064's they will at least get things
started, finding a cheap but large gate array suitable for easy construction
(i.e. no BGA or really fine pitch) will probably always be some sort of
compromise.
People who want to build a ZX81 usually want to do so in the back shed with a
100W soldering iron ;)
cya, Andrew...
kryten_droid wrote:
> The '3042 is getting on a bit as Xilinx have advanced several generations.
> I'm looking at porting the design to this board:
>
> http://www.howell1964.freeserve.co.uk/logic/burched/fpga_devkit_b5.htm
>
> There is a lot more logic and I/O available in the chip,
> so room to use this board for future projects.
>
> I should point out that these chips involve a lot of very sensitive gates
> toggling like crazy, so they do need a good quality PCB design with decent
> power decoupling and dedicated power and ground planes. Four-layer boards
> are significantly dearer to produce than two layer boards of course. It's
> not really economically feasible to make a small production run for a
> low-value product.
>
> What might be worth doing is making a 2-layer board to mate with the B5
> board.
> That would have the relatively simple application specific circuitry.
> A Z80, a 32K RAM and a ROM (5V flash?).
Article: 36654There is a bug in 3.1 that doesn't let the CoreGen utility run on P4 machines. Rick Filipkiewicz wrote: > Jim Bittman wrote: > > > being able to run the CoreGen (because of the Pentium-4 bug), switching > > ^^^^^^^^^^^ > > What bug is this ? -- ******************************************************************** * Jim Bittman * Tel: 603-226-0404 * * BittWare, Inc. * Fax: 603-226-6667 * * 33 North Main Street * E-Mail: jmbj@bittware.com * * Concord, NH 03301 * WWW: http://www.bittware.com * ********************************************************************Article: 36655
In article <9stchu$kdl$1@sunce.iskon.hr> , "Damir Danijel Zagar" <dzagar@srce.hr> wrote: > I'm in need of a pointer for a ASRC implementation > using DSP or FPGA. Any source (C-code or VHDL) > will be more than welcome. Regards, you ain't gonna get any C code from me (it belongs to the company), but i did implement such a thing on the SHArC about 5 or 6 years ago. Bob Adams of Analog Devices is essentially the father of the ASRC chip (AD-1890 and relatives) and the only on-line publication i can find from him about this is at: http://www.analog.com/industry/audio/documents/92AES.pdf there are two independent concepts to get down. the first is the basics of "resampling" or "polyphase filtering" or "bandlimited interpolation" or "sample rate conversion" (whether it's asynchronous or not) or whatever is the jargon that's currently in vogue for it. a primer can be found at: http://groups.google.com/groups?selm=387e71db.0%40news.viconet.com the second concept to get down is the servo control mechanism to adjust the sampling ratio between input and output that is based purely on the asynchronous input and output word clocks. the Bob Adams paper to look that up is not online (as best as i can tell) but is published: Adams & Kwan, "Theory and VLSI Archetectures for Asynchronous Sample-Rate Converters", JAES, vol. 41, p. 539 (Jul 1993) . -- r b-j Wave Mechanics, Inc. 45 Kilburn St. Burlington VT 05401-4750 tel: 802/951-9700 ext. 207 http://www.wavemechanics.com/ fax: 802/951-9799 robert@wavemechanics.com --Article: 36656
On Wed, 14 Nov 2001 10:12:56 +0100, "Damir Danijel Zagar" <dzagar@srce.hr> wrote: >I'm in need of a pointer for a ASRC implementation >using DSP or FPGA. Any source (C-code or VHDL) >will be more than welcome. Regards, > >Damir You can use a phase generator and a fractional delay filter to do asynchronus sample rate conversion. A phase generator is simply a modulus counter which calculates the sampling point of the target clock on the data. Using this phase, you can calculate the newly sampled data by interpolation. For interpolation, a fractional delay filter can be used as implemented by a farrow filter. With a farrow filter, you can use any polynomial interpolator. hope this help, Muzaffer Kal http://www.dspia.com DSP algorithm implementations for FPGA systemsArticle: 36657
khtsoi@cse.cuhk.edu.hk wrote in message news:<9sqnh1$j6u$1@eng-ser1.erg.cuhk.edu.hk>... > Someone told me that tools from Synplicity is better than the Synopsys > Xilinx combination in FPGA place and route process. I am sick with the > bad routing design in Alliance3.1i. Also, it takes me more than 1 day > to par a design using only 45% slices of a XCV1000E (on a Sun E4500). > > I really hope someone can give me some advices about the performance > of the Synplicity tools. I will use it on either or both Sun E4500 with > SunOS and P4 1.4GHz PC with Win/Linux. Does anyone has experience on > implementing a design in similar size under these environment? Also, > most of my current design is developed under Synopsys Design Compiler > which cannot be synthsised directly on FPGA Express. Can the Synplicity > tools under the synopsys coding style? Last, is there any performance > differences between the commercial version and evaluation version? > Let me put it this way, Xilinx uses Synplicity for their IP development. Synplicity has always beaten Synopsys hands down in compile time and ease of use. Design speed is also better but not by such a huge margin. Personally I use a PC instead of Sun now. I have a design that uses 80% of the XCV1000E. Synplicity takes about 20 minutes; Xilinx PAR takes about 45-60 minutes. Synplicity wont do much for poor placement, that is a Xilinx problem, that is generally fixed with floorplanning (which I did for my entire design). If you are rich, you can by Amplify which is an add on to Synplicity which will help you floorplan and then resynthesize in an attempt to make up for the Xilinx tools randomly scattering your state machines across the die. MarkArticle: 36658
Russell Shaw wrote: > I figured out how to trace signal paths using the maxplus2 > floor-planner. > I traced from the clock input pin to the clock divider, and looked at > the fanout from the last flip-flop. I found there were a few counters > implemented as scattered logic, not being recognized as counter > templates. I found just one or two extra lines in a process can prevent > recognition by the compiler as a counter. With a slight modification to > match standard leonardo templates, they get recognized and implemented > as LPM library functions, showing compact grouping in LABs. You can also see this sort of thing by viewing the "technology" schematic. To get some idea of the templates leo is looking for, see: http://www.edif.org/lpmweb/more/vhdl.htm http://www.edif.org/lpmweb/documentation/docu_index.html I have found that leo does a good job with both brand A and brand X if you follow these templates. > The next > thing was to get that buried node from the clock-divider output onto > a global clock track. A simple resource assignment in the floor-planner > did that. The externally supplied clock just goes to an 'ordinary' > io pin. Excellent. Didn't now the 1k30 could do that from a port pin. -- Mike TreselerArticle: 36659
Hi
Each Xilinx fpga logic cell, there is a 16x1 ram which might be used as 16x1 ram
which might be a basic delay line
a 1326x8 bits delay line would require 83x8 logic cells (664) this is
applicable to Spartan, and virtex
for Xilinx virtex either Altera 10k and Apex , you might use ram blocs
- 4k blocks => 1k*8 or 2k*4 , I would use 2 Brams for a 1326x8 plus a
basic counter which makes a shift register ( a DLL is
required not to violate Tbccs ( see data sheet )
for each add : read first and write a new value a 2 ports
ram is mandatory for very high speed
- 18k blocs ( virtexII) => use a 4k*8 then as basic shift register read first
I hope it will help
jacky
--
User of http://www.foorum.com/. The best tools for usenet searching.
Article: 36660I've done Forney (RamseyIII) and RamseyII interleavers using Xilinx BRAM. Setting up all the pointers is tricky, but is definitely worthwhile because of the CLB savings. These interleavers are commerical. But that isn't always a bad thing if it saves you a lot of time in development and verification. -Kevin "mehmeto" <mehmetozcelebi@turk.net> wrote in message news:e6ae63f0.0111140035.3d843044@posting.google.com... > Hi, > I have a similar problem like srinas has. > The convolutional interleaver for ATSC has 52 lines and needs > (51x52)/2=1326 delay elements. If the input is 8 bit then 1326x8=10608 > delay elements are required. The required number of Flip flops for a 4 > symbol delay is 10608x4 = 42432. This is quite large. > The same complexity is also valid for DVB interleavers. > Is there any way to reduce the Flip Flop count? I know there are > megafunctions for altera and xilinx devices, but they are commercial. > > ThanksArticle: 36661
The datasheet for the AD1896 is a good place to look too. Bob designed this chip and the data sheet has a lot of the theory. http://www.analog.com/pdf/AD1896_0.pdf "robert bristow-johnson" <robert@wavemechanics.com> wrote in message news:9hxI7.7619$o16.377059@typhoon2.gnilink.net... > In article <9stchu$kdl$1@sunce.iskon.hr> , "Damir Danijel Zagar" > <dzagar@srce.hr> wrote: > > > I'm in need of a pointer for a ASRC implementation > > using DSP or FPGA. Any source (C-code or VHDL) > > will be more than welcome. Regards, > > you ain't gonna get any C code from me (it belongs to the company), but i > did implement such a thing on the SHArC about 5 or 6 years ago. > > Bob Adams of Analog Devices is essentially the father of the ASRC chip > (AD-1890 and relatives) and the only on-line publication i can find from him > about this is at: > > http://www.analog.com/industry/audio/documents/92AES.pdf > > there are two independent concepts to get down. the first is the basics of > "resampling" or "polyphase filtering" or "bandlimited interpolation" or > "sample rate conversion" (whether it's asynchronous or not) or whatever is > the jargon that's currently in vogue for it. a primer can be found at: > > http://groups.google.com/groups?selm=387e71db.0%40news.viconet.com > > the second concept to get down is the servo control mechanism to adjust the > sampling ratio between input and output that is based purely on the > asynchronous input and output word clocks. the Bob Adams paper to look that > up is not online (as best as i can tell) but is published: > > Adams & Kwan, "Theory and VLSI Archetectures for Asynchronous Sample-Rate > Converters", JAES, vol. 41, p. 539 (Jul 1993) . > > -- > > r b-j > > Wave Mechanics, Inc. > 45 Kilburn St. > Burlington VT 05401-4750 > > tel: 802/951-9700 ext. 207 http://www.wavemechanics.com/ > fax: 802/951-9799 robert@wavemechanics.com > > --Article: 36662
> Hey there, > It seems I have another challange to overcome in attempting 'timing' > simulations in ModelSIM. Kris, Why are you doing timing simulations in the first place? AustinArticle: 36664
Mike Treseler wrote: > > Russell Shaw wrote: > > > I figured out how to trace signal paths using the maxplus2 > > floor-planner. > > I traced from the clock input pin to the clock divider, and looked at > > the fanout from the last flip-flop. I found there were a few counters > > implemented as scattered logic, not being recognized as counter > > templates. I found just one or two extra lines in a process can prevent > > recognition by the compiler as a counter. With a slight modification to > > match standard leonardo templates, they get recognized and implemented > > as LPM library functions, showing compact grouping in LABs. > > You can also see this sort of thing by viewing the "technology" schematic. Unfortunately, the leo-freebie doesn't have that option:( > To get some idea of the templates leo is looking for, see: > > http://www.edif.org/lpmweb/more/vhdl.htm > http://www.edif.org/lpmweb/documentation/docu_index.html > > I have found that leo does a good job with both > brand A and brand X if you follow these templates. > > > The next > > thing was to get that buried node from the clock-divider output onto > > a global clock track. A simple resource assignment in the floor-planner > > did that. The externally supplied clock just goes to an 'ordinary' > > io pin. > > Excellent. > Didn't now the 1k30 could do that from a port pin. I found its not so foolproof tho. Changing the vhdl code can change the name of that compiler-assigned node. However, after doing some more code cleanup, there's lots of fanout from the one clock-divider output. I think the quartus fitter will automatically use a global clock net for an output that goes to lots of FF clock inputs. Another source of confusion which i fixed is that latched outputs from the case statement of a state machine are a bad thing. When the state changes, a momentary glitch (race) means any number of other states can be momentarily selected, causing latched signals to change value.Article: 36666
"Seb" <someone@microsoft.com> wrote in message news:E5VG7.47306$88.5467995@zwoll1.home.nl... > Hi group(s) > > regarding any JPEG standard (JPEG, JPEG2000, JPEG-LS,...) what bitrates can > be obtained with current implementation technologies (DSP, FPGA, ASIC)? > > Indications and estimations are also welcome. Our JPEG codec core ran at ~ 20 MHz in VirtexE. I don't remeber the part number, I think i was smaller than a 400. Since it processed one sample per clock, this translates into about 6.666 Mpixels/s for RGB (3 samples per pixel) or 13.333 Mpixels/s in YUV 4:2:0 (1.5 samples per pixel). The bottleneck was the guaranteed one cycle Huffman decoder. An encoder only would have been quite a bit faster. Using Virtex II even better results should be possible. It was straight VHDL/Verilog with no optimizations for FPGA (> 60 MHz in 0.25 u ASIC process). FPGA Express was used for FPGA synthesis. It has been proven in silicon various times and InSilicon Corporation acquired the code at the end of 2000. You now purchase from them: http://www.insilicon.com/ We'll be offering a variety of MPEG solutions soon, even for low end FPGAs. > > cheers > Seb Regards, Enzo ------------------------------------------------------------------ Vincenzo Liguori Ocean Logic Pty Ltd PO BOX 768 Manly NSW 1655 Australia Ph : +61-2-99054152 Fax : +61-2-99050921 WWW : http://www.ocean-logic.comArticle: 36667
Jim Bittman <jmbj@bittware.com> wrote in message news:<3BF01451.5DD62639@bittware.com>... > We have a real simple sch/vhdl design done under 3.1 that has > encountered > a number of problems. I can't imagine these being unique, but I also > don't see how > everyone could have them and not be screaming.... > ---- SNIP I was switching back and forth between 3.1i and 4.1i for a little while and didn’t see any problems. In fact for a little while I was placing and routing with one version and using fpga editor from another version. If you install them in different directories then you just need to change the environment variable to switch from one to another. 4.1i includes a copy of Design Manager under accessories. If you use this then you don’t have to change your design directory structure. My buddy and I are running our designs that were in process with Design Manager, and I am using Project Navigator with my new designs. All of our designs are Verilog, with a little coregen, and some hard macros. Looks like most of your compatibility issues are with schematics, which does not surprise me. I gave up on schematics a long time ago when a bug on a CPLD forced me to change vendors at the last minute, which meant a complete, redo on the schematic. My Xilinx FAE has no customers using schematic anymore, which is not to say that no one uses it, but that it is not the most common entry method. This means that it will get the least testing before release, the least testing and bug reporting after release, and the least amount of resources to correct the bugs. Of course, I realize this does nothing to help your current situation, and I have lots of sympathy for you since I have been there myself. I like to use FPGA editor to create hard macros. This flow is hardly supported at all and even the FAEs don’t use it much so it is full of bugs. Although using an HDL has made me immune from many of your problems, I was not immune from compatibility issues between VirtexE and VirtexII. I am having to modify a lot of code because the primitive libraries are different and things like LVDS instantiation have changed. Don’t you wish you had a Co-op working for you to work through all that crap?!?!Article: 36668
Hi...
Does anyone have any ideas what exactly the ALTDIG & DIG pins in a V-II do?
Thanx in advance ...
Ciao,
Nitin.
Article: 36669
s9323090@cc.ncu.edu.tw (Arguo) wrote in message news:<52758910.0111131827.4f26d43f@posting.google.com>...
> Hi,
> I am try to design sdram controller. I think the sdram module interface is
> similar sdram. Can I treat the sdram module as a larger sdram?
>
> Best Regards,
> Arguo
There are two types of SDRAM modules: one is just a bunch of SDRAM chips
(usually 64-bit wide with Byte Enable for each 8-bit byte; some have an
additional 8 bits for ECC); this type is called unbuffered DIMM.
The other type contain registers on all control and address signals, and
usually also a PLL to reduce loading on the clock inputs; this type is
called buffered or registered.
For standard 168-pin DIMMs there are both buffered and unbuffered modules;
the larger sizes (currently above 512 MB) are available only as buffered.
Another common standard type is 144-pin SODIMM; this is usually of smaller
capacity (currently up to 256 MB) and is always unbuffered.
You can get SDRAM simulation models from Micron (www.micron.com); build
a model of your module by selecting the correct width and array size; if
you want to use buffered modules, just add a register on all control and
address inputs.
Regards
Assaf Sarfati
Article: 36670OK, everyone is suugesting solutions for xilinx. What about Altera devices and how could I instantiate the embedded blocks in my vhdl file? The commercial components are good, but at least they are composed of basic building blocks. Does anybody know how? Thanks "John Adair" <newsanswer@removethisenterpoint.co.uk> wrote in message news:<3bf268fa$1_1@news2.vip.uk.com>... > Your can use the lookup tables in Xilinx Virtex/VitexII as shift registers. > For each LUT you can generate up to a 16 clock delay. Given that your have > approximately the same number of flip-flops available as LUTs it is far more > efficient to use the LUT (SRL16 mode). The only limitation is that you > usually only have one O/P from a SRL16 to use, i.e. adjacent bits not > accessable.Article: 36671
Mike Treseler <mike.treseler@flukenetworks.com> writes: > Russell Shaw wrote: > > > The next > > thing was to get that buried node from the clock-divider output onto > > a global clock track. A simple resource assignment in the floor-planner > > did that. The externally supplied clock just goes to an 'ordinary' > > io pin. > > Excellent. > Didn't now the 1k30 could do that from a port pin. > Just for anyone who's interested, any internal signal can be routed onto any of the global (low-skew) interconnects which can then be used for clocks, OEs etc. This is in 6000, 10K, 1K and 20K IIRC. An external pin can be put through an LCELL to create an internal signal which can then be put onto a global signal. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 36672
Check out www.datacube.com for their MaxRevolution product. David Eadie <david.eadie@cs.tcd.ie> a écrit dans le message : a0ce2abd.0111140648.1f92ae6b@posting.google.com... > Hi, > > I'm interested in exploring the image processing potential of using > FPGAs within high-speed video cameras. Initially I would like to get > an FPGA prototyping/development/evaluation kit working within the PC > itself. > > Features I would like: > > -PCI-card-based, to allow easy I/O to/from PC memory. > -on-card memory to store image data and results. At least 8 MB, > preferably more. > -Virtex II device (2 million gates, or more). > -Some FPGA I/O pins accessible through a header/connector on the > PCI-card. > > Does anyone know if such a card, or similar, exists? > Are there any other important features I should look for? > > Thanks > > David Eadie, > Computer Vision and Robotics Research Group, > Dept. of Computer Science, > Trinity College Dublin.Article: 36673
Hey all. I'm dealing with an interesting problem -- something I'm sure a lot of other people have come across... The issue is how to get a high speed (>=200kHz) 10-bit PWM signal. That is 200kHz is the frequency of the PWM waveform, and 10-bit resolution is what I am seeking for the duty cycle control. My implementation (and essentially all I've come across) use a counter that counts pulse-widths and after that some kind of "customization" sets the output. The customization varies -- some people like to use a comparator and latch the output, others, like the Xilinx App note, like to use the Terminal Count on the counter and set an S-R flip-flop. My implementations in the past have essentially been like Xilinx's terminal count idea. The problem however, is how to get >=200kHz with 10-bit control; for a 200kHz waveform one needs a 200kHz * 2^10 = 204.8MHz clock to clock the pulse-wdith counter! Even with PLLs and DLLs a 16-bit PWM would be murder. I was discussing this very issue with an engineer the other day who told me he was able to implement PWM control in an FPGA (a Spartan or something <= Virtex) along with several FIR filters AND not need a clock greater than 20MHz and also went on to mention he was able to get 1ns resolution of the duty cycle. He was also clear that it was proprietary information and could not give me the specifics. I have every reason to believe he is not lying, that he has actually accomplished high-speed high-resolution PWM in an FPGA. My interest in this problem has now increased exponentially (much like the clock needed for "standard" PWM implementations). So the million dollar question is how might he have done it? I've been thinking of all sorts of things, but I still can't find an elegant solution. The best I've been able to come with is this: If one could get a 1ns delay out of an element, these elements could be strung together and at each "tap" feed the output into a 256:1 MUX or a 1024:1 MUX. The clock would be fed into the input of the 1st delay element and the selector bits on the MUX would give the desired PW. That might be a good idea for a VLSI design, but not for an FPGA... Anyway, I'm not sponsoring a competition, just wanted to hear some ideas ;). Thanks, VR.Article: 36674
Hi...
Yeah i guess this should be the reason. Thanx...
Ciao,
Nitin.
Neil Franklin <neil@franklin.ch.remove> wrote in message news:<6u7ksvg2tf.fsf@chonsp.franklin.ch>...
> ndeshmukh@yahoo.com (nitin) writes:
>
> > well i suppose the floor planning of the slices within a CLB is
> > driven by the fact that they were going to have two carry chains
> > through it... so they put two this side & two that side... other wise
> > why not all four in a column...?
>
> Because the aspect ration of the CLBs would get problematic.
>
> XC3000 and XC4000 have 2x1 LUTs/CLB
> XC5200 has 4x1 LUTs/CLB
> Virtex has 2x2 LUTs/CLB
> Virtex-2 has 4x2 LUTs/CLB
>
> Having a "square" was obviously considered better in Virtex. And 4x2
> is the nearest possible with 8 LUTs/CLB.
>
> Do not forget that having "high" CLBs with 8x1 ratio would result in
> less dense horizontal wiring, or require wider (and so asymmetrical)
> wiring bundles in horizontal direction.
>
> Alteras FLEX chips actually do this so (8x1 or 10x1), because they
> are adapted CPLD designs (with the product term array replaced by
> PIPs and the ORs replaced by LUTs).
>
> OTOH Atmel has 1x1 CLBs.
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