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Markus Meng wrote: > > Hi, > > this is exactly how I did it on 66MHz PCI Bus card having a Spartan-IIE > 300 a 2MB serial data flash and a cheap CPLD. This is all well below 2US$ > for > configuration. It even beats what Xilinx is offering us the 3Q or 4Q this > year .-( > > That's the way it is. I am jst wondering why SST or ST or others do not jump > on this train by simply changing the command for the read array mode to > something > like all '0' and all '1'. Then the only thing you need is the inverter you > mentioned and > then you have a ISP configuration from for 1..2US$. Then the price is > adequate and > you can neglect it and talk about the FPGA prices ... I expect this is not a large market. Many of the FPGAs do not use dedicated serial PROMs for configuration since there is often an MCU or CPLD and a standard Flash part on board. I don't think I have ever used a serial configuration device in the ten years or more that I have been designing FPGAs. If the really large quantities are not there, then there is no room for profit at $2 a part. > Maybe you remember Gorbatschows ...if you come to late then ... > > In my opinion the marketing responsible people at Xilinx and at Altera did > wait to long > to provide us with a cost effective solution for ISP configuration devices. > Especially > today having partial reconfiguration, soft cores, you can realize a in field > updatable electronic device with an FPGA SRAM based from the two big ones, > and > an external serial data flash. A mini cpu system insisde the fpga can handle > the user > request for firmware updates ...and reprograms the external configuration > device ... In fact, for many of the FPGAs, you can get an $8 32 bit MCU with enough Flash to hold one configuration. Maybe not for the high end parts, but if you already need an MCU, you get the configuration storage for nearly nothing. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56251
KG7HF wrote: > > Generally, it's OK to put various devices in a single chain. You simply > have to use a configuration tool to describe the JTAG chain to the debugger > so that it knows where the device you are trying to debug lies in the chain. > Part of the description is the number of devices, and the size in bits of > the instruction register. The debugger will ignore all the other devices > by using the bypass instruction and placing them in bypass mode. This > allows the debugger to "focus" on the device in the chain you are trying to > debug. What devices have you used in a scan chain together? What tools did you use to talk to these devices? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56252
I found something on my question: 1- ground wire needed for LVDS. Because all noise on differential pair can not be removed by LVDS receiver. IL711 ISOLATE noises from destionation board and not remove them from LVDS RECEIVERS. 2- Cable transmission on 30 meter require high ESD protection on drivers and receivers. Embedded Drivers/Receivers in spartan IIE or Virtex family of xilinx has low ESD protection. TI has some LVDS parts with 15kv ESD protection. It is possible to use embedded LVDS drivers/receivers of fpgas plus external ESD protector, but i do not prefer this! Regards. M. NaderiArticle: 56253
Hi all, Has anybody does experience on IDT TDM switches? I have a probelm on it's clock signal. It is too much sensitive to unknown things such a few jitter, slow rise/fall time and so! Is there any special recommendation on this or I do something completely wrong?! Regards M. NaderiArticle: 56254
Hi all, I want to do some basic sonet/sdh mapping, framing, pointer processing on xilinx spartan IIE. I see PMC-Sierra chipset on SDH, they are do many different things that I do not need for a basic STM-1 link. ( I want do multiplex 16*16Mhz signal on STM-1 frame). PMC-Sierra temux and spectra chipset are very complex and expensive ( $600 for both ). Does anybody has practical experince on this. I look for a more clear perspective on FPGA implementation. Best Regrads. M. NaderiArticle: 56255
There is a also a leakage current which is the static portion of the power
dissipation. There is a tradeoff for leakage current vs speed, and in the case
of the FPGA vendoers, speed is king.
Glen Herrmannsfeldt wrote:
> The tradition of CMOS is that it only consumes power changing state. During
> a change both transistors are partially on, resulting in current flow, and
> also charging/discharging of the load capacitance of the metalization
> layers. This may be less true as density increases, but as far as I know
> it is still true. Some devices spec. the power consumption as proportional
> to clock frequency.
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 56256Hi all, Xilinx ISE is giving me fits. I could swear that it hates me! This is version 4.2i, by the way. Version 5 does not support the part I'm using. Here's what's happening: The design is very close to -not- meeting the speed requirement, which is 50 MHz. If, when ISE runs, it does 'improving timing' passes, the speed comes out at 50.314 MHz. If it does not run these passes, I get 47.246 The problem is, I can't figure out how to get it to run these passes! Some times it does, some times it doesn't. The help file tells me to check an option box, but that box doesn't exist! Please, how do I turn this option on? Right now, ISE is stuck in the mode where it does not run these cleanup passes. :( And, if someone has a tutorial-like document for guiding place and route, I would like to see it. Basically, I want to 'suggest' to P&R that certain (Verilog) modules belong in certain haves of the chip. Much Appreciated, Gary gwhelbig-at-yahoo-dot-comArticle: 56257
Hey I'm looking for some information about how to program XC9572 ? I know how to build my own cable, but I don't know how to connect it to Xilinx. I mean I don't know how to connect power supply ? Does anybody know - where I can find some infotmation about it ? I know that there is a lot of information on xilinx web page... but where ??? thanks for any help GorgoArticle: 56258
Use v3.3 sp8 instead. The router in 4.x is lazy. FWIW, I've had some
good results so far with 5.2 sp3. Seems Xilinx has fixed many of the
problems I saw with the 4.2 router (Thank you).
email_address@message.end wrote:
> Hi all,
>
> Xilinx ISE is giving me fits. I could swear that it hates me! This
> is version 4.2i, by the way. Version 5 does not support the part I'm
> using.
>
> Here's what's happening:
>
> The design is very close to -not- meeting the speed requirement, which
> is 50 MHz.
>
> If, when ISE runs, it does 'improving timing' passes, the speed comes
> out at 50.314 MHz. If it does not run these passes, I get 47.246
>
> The problem is, I can't figure out how to get it to run these passes!
> Some times it does, some times it doesn't. The help file tells me to
> check an option box, but that box doesn't exist!
>
> Please, how do I turn this option on? Right now, ISE is stuck in the
> mode where it does not run these cleanup passes. :(
>
> And, if someone has a tutorial-like document for guiding place and
> route, I would like to see it. Basically, I want to 'suggest' to P&R
> that certain (Verilog) modules belong in certain haves of the chip.
>
> Much Appreciated,
> Gary
> gwhelbig-at-yahoo-dot-com
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 56259Ray, What is v3.3sp8, and how do I get it? I can't use ISE-5.2 with a 5V Spartan, can I? Thanks, Gary. On Sun, 01 Jun 2003 21:59:04 GMT, Ray Andraka <ray@andraka.com> wrote: >Use v3.3 sp8 instead. The router in 4.x is lazy. FWIW, I've had some >good results so far with 5.2 sp3. Seems Xilinx has fixed many of the >problems I saw with the 4.2 router (Thank you). > >email_address@message.end wrote: > >> Hi all, >> >> Xilinx ISE is giving me fits. I could swear that it hates me! This >> is version 4.2i, by the way. Version 5 does not support the part I'm >> using. >> >> Here's what's happening: >> >> The design is very close to -not- meeting the speed requirement, which >> is 50 MHz. >> >> If, when ISE runs, it does 'improving timing' passes, the speed comes >> out at 50.314 MHz. If it does not run these passes, I get 47.246 >> >> The problem is, I can't figure out how to get it to run these passes! >> Some times it does, some times it doesn't. The help file tells me to >> check an option box, but that box doesn't exist! >> >> Please, how do I turn this option on? Right now, ISE is stuck in the >> mode where it does not run these cleanup passes. :( >> >> And, if someone has a tutorial-like document for guiding place and >> route, I would like to see it. Basically, I want to 'suggest' to P&R >> that certain (Verilog) modules belong in certain haves of the chip. >> >> Much Appreciated, >> Gary >> gwhelbig-at-yahoo-dot-comArticle: 56260
16 * 16 MHz works out to 256 Mbps -- STM-1 is 155 Mbps. So, you will need to map into STM-4 at 622 Mbps, or do some sort of statistical muxing. Check out Core Foundry. www.corefoundry.com They make some very small SONET processing cores and do custom work. "Masoud Naderi" <naderimisc@yahoo.com> wrote in message news:2ba3bbea.0306011137.4e9857fc@posting.google.com... > Hi all, > I want to do some basic sonet/sdh mapping, framing, pointer processing > on xilinx spartan IIE. I see PMC-Sierra chipset on SDH, they are do > many different things that I do not need for a basic STM-1 link. ( I > want do multiplex 16*16Mhz signal on STM-1 frame). PMC-Sierra temux > and spectra chipset are very complex and expensive ( $600 for both ). > Does anybody has practical experince on this. I look for a more clear > perspective on FPGA implementation. > Best Regrads. > M. NaderiArticle: 56261
"Gorgo" <chudzielec21@wp.pl> wrote in message news:bbdq1l$o10$1@korweta.task.gda.pl... > Hey > > I'm looking for some information about how to program XC9572 ? I know how to > build my own cable, but I don't know how to connect it to Xilinx. I mean I > don't know how to connect power supply ? > Does anybody know - where I can find some infotmation about it ? I know that > there is a lot of information on xilinx web page... but where ??? I've got some info on this on my web site. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 56262
Followup to: <3ED837FB.E126507E@yahoo.com>
By author: rickman <spamgoeshere4@yahoo.com>
In newsgroup: comp.arch.fpga
>
> I don't mean to bug you, but you still did not answer the question of
> what distinguishes software from *other*ware. You said about FPGA/CPLD
> configuration data, "It has all the attributes of software". What
> features are you considering when making this claim? What defines
> software vs. *other*ware? What makes an antifuse program different?
> What makes semicustom asics different?
>
Okay, let me explain how I look at the world:
There are generic devices and there are specialized devices. A
specialized device is one which performs one particular task; a
generic device can be adopted to perform one of many tasks, but all by
itself performs *no* task.
The device, either way, is hardware.
What modifies the generic device into performing a task is software:
Generic device
V
+----------+ +----------+
| Hardware | <---+ Software |
+----------+ +----------+
If the hardware/software combination is sold or otherwise presented to
a user as if the whole thing was a specialized device, then by
convention we call the software portion "firmware":
Specialized device equivalent
V Generic device
+-V-----------------------------+
| +----------+ +----------+ |
| | Hardware | <---+ Firmware | |
| +----------+ +----------+ |
+-------------------------------+
Now, in SRAM-style FPGA or in a microprocessor, the programming is
ephermeral; the software component has to be introduced every time.
There is here a clear separation between the software and hardware
components.
Similarly, in a flash CPLD the software component can be modified at
will, even though it is physically stored inside the CPLD. The
separation is maintained.
With an antifuse or other OTP device, the separation clearly exists
*before* the programming. However, once programmed, it is a
specialized device -- it can no longer be separated into software and
hardware components, and it can never be reverted to a generic
device. Therefore, they are in my mind a sort of borderline
condition, although I tend to still consider the hardware/software
(hardware/firmware) separation useful.
A semicustom ASIC is turned into a specialized device already during
the manufacturing process, so I find it hard to consider it as a
generic device, even though some manufacturing steps are shared with
other devices.
It's not an obvious line to draw at the low end, though.
-hpa
--
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64
Article: 56263On Wed, 28 May 2003 20:30:32 -0400, Jerry Avins <jya@ieee.org> wrote: >Eric Jacobsen wrote: >> >> It's weird, though, even when the drill bit is square the hole comes >> out round! > >I use three-sided bits to drill square holes. I make mine from worn out >three-square* files, but you can buy them. > >http://www.integerspin.co.uk/polygon.htm > > ... > >Jerry >______________________ >* A stupid name I didn't make up. People keep pointing out the unintentional truths behind my jokes so that they're not funny any more. :( Not that they were good jokes anyway, but... The chucks for these look expensive. What do you use? This could be pretty handy, actually... Eric Jacobsen Minister of Algorithms, Intel Corp. My opinions may not be Intel's opinions. http://www.ericjacobsen.orgArticle: 56264
In article 3edad37f.247096254@news.earthlink.net, Eric Jacobsen at eric.jacobsen@ieee.org wrote on 06/02/2003 00:35: > People keep pointing out the unintentional truths behind my jokes so > that they're not funny any more. :( that's what you get, Reverend. we be a serious bunch of dogs here on comp.dsp . better believe it. :-| r b-jArticle: 56265
"H. Peter Anvin" wrote: > > Followup to: <3ED837FB.E126507E@yahoo.com> > By author: rickman <spamgoeshere4@yahoo.com> > In newsgroup: comp.arch.fpga > > > > I don't mean to bug you, but you still did not answer the question of > > what distinguishes software from *other*ware. You said about FPGA/CPLD > > configuration data, "It has all the attributes of software". What > > features are you considering when making this claim? What defines > > software vs. *other*ware? What makes an antifuse program different? > > What makes semicustom asics different? > > > > Okay, let me explain how I look at the world: > > There are generic devices and there are specialized devices. A > specialized device is one which performs one particular task; a > generic device can be adopted to perform one of many tasks, but all by > itself performs *no* task. > > The device, either way, is hardware. > > What modifies the generic device into performing a task is software: > > Generic device > V > +----------+ +----------+ > | Hardware | <---+ Software | > +----------+ +----------+ > > If the hardware/software combination is sold or otherwise presented to > a user as if the whole thing was a specialized device, then by > convention we call the software portion "firmware": > > Specialized device equivalent > V Generic device > +-V-----------------------------+ > | +----------+ +----------+ | > | | Hardware | <---+ Firmware | | > | +----------+ +----------+ | > +-------------------------------+ > > Now, in SRAM-style FPGA or in a microprocessor, the programming is > ephermeral; the software component has to be introduced every time. > There is here a clear separation between the software and hardware > components. > > Similarly, in a flash CPLD the software component can be modified at > will, even though it is physically stored inside the CPLD. The > separation is maintained. > > With an antifuse or other OTP device, the separation clearly exists > *before* the programming. However, once programmed, it is a > specialized device -- it can no longer be separated into software and > hardware components, and it can never be reverted to a generic > device. Therefore, they are in my mind a sort of borderline > condition, although I tend to still consider the hardware/software > (hardware/firmware) separation useful. > > A semicustom ASIC is turned into a specialized device already during > the manufacturing process, so I find it hard to consider it as a > generic device, even though some manufacturing steps are shared with > other devices. > > It's not an obvious line to draw at the low end, though. So in summary, you consider firmware/software to be *any* alteration of any form that can be performed on hardware as long as it is not permanent, right? Where do you draw the line between software/firmware and simple programming of registers? Many application specific, standard product (ASSP) chips do pretty much nothing until they are setup by configuring the various registers in the chips. This is not a lot different from the typical sort of software/firmware that is programmed into a CPLD or even a flash MCU. I have seen ASSP chips that have a manual on usage that is easily as large as an MCU. How do you distinguish ASSP chips from FPGAs in regards to the programming? Is the configuration of ASSP chips also called software/firmware? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56266
Your application might be good fit for FPGAs, if you are not going to use all the features that are provided by the standard chipset. Might even be cheaper, but depends (see below) In my opinion, developing the framing and path processing is not so easy, unless you have telecom experts in-house who also understand FPGA implementation. It is best to buy an IP and get it customized for your requirement. I have seen that an STM-1 and STM-4 path processor and framer can be implemented in 16K Logic cells (equivalent to an XC3S1000) which can be further optimized based on what you need and what you don't. The things I've seen being implemented in FPGA are framing, path processing, TU aligner, cross-connect functions and finally the mappers (PDH, Ethernet etc.). From business standpoint, it all depends on the volume you are going to generate, because unit price of FPGAs might be cheaper but developing/buying/customizing the IPs can be expensive. If you are going to build multiple solutions STM-1, STM-4 or greater, you can build volume since the FPGA device will be common for all solutions, whereas standard chipset will be different for each solution. The company I work for has a lot of IP in this area, and you can have a look at them on http://www.cg-coreel.com/pages/products/iplist.htm If you are interested in any of them, I can ask one of our business development guys to talk to you, send me a message offine. HTH, Neeraj "Masoud Naderi" <naderimisc@yahoo.com> wrote in message news:2ba3bbea.0306011137.4e9857fc@posting.google.com... > Hi all, > I want to do some basic sonet/sdh mapping, framing, pointer processing > on xilinx spartan IIE. I see PMC-Sierra chipset on SDH, they are do > many different things that I do not need for a basic STM-1 link. ( I > want do multiplex 16*16Mhz signal on STM-1 frame). PMC-Sierra temux > and spectra chipset are very complex and expensive ( $600 for both ). > Does anybody has practical experince on this. I look for a more clear > perspective on FPGA implementation. > Best Regrads. > M. NaderiArticle: 56267
"Ray Andraka" <ray@andraka.com> wrote in message news:3EDA5E88.A1A90548@andraka.com... > There is a also a leakage current which is the static portion of the power > dissipation. There is a tradeoff for leakage current vs speed, and in the case > of the FPGA vendoers, speed is king. In the olden days, this leakage was close enough to zero that people ignored it. As devices scale, the oxide gets thinner and tunnelling currents increase. Even if the current per transistor stayed constant, the total would increase with transistor count. At high clock rates you can still probably ignore it. If you want a device that can power down to minimal current, then you can't. Xilinx does keep the leakage low on the configuration circuitry, but speed doesn't matter (much) there. -- glenArticle: 56268
I would want to know if a situated one exists or of articles where they are described to us the characteristics and main the differences between the FPGA trade themArticle: 56269
Giovanni wrote: > I would want to know if a situated one exists or of articles where they are > described to us the characteristics and main the differences between the > FPGA trade them Did you have a look at the various papers provided by the manufacturers ? There are applcation notes, technical notes, family overviews and so on. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 56270
Hi there, I'm working with the Nios Excalibur Kit and I have a problem with the GERMS which is included in the ROM of the Nios. I have a software program stored in the FLASH memory of the Nios Development Kit and it works correctly: when I reset the board, the GERMS looks for the software application in the FLASH and it copies to the SRAM memory to be able to execute it. But when I want to access to the Nios microprocessor directly from my NDK Shell, I push the SW4 button while I reset the board as it appears in the manual, but it doesn't work. I don't know why, but it only works with the tutorial applications such as "standard 32", etc... Does anybody know the reason of this strange situation? Thanks.Article: 56271
I'm in the same opinion Neeraj does. SDH implementations in FPGAs require good FPGA engineering, especially at higher rates. I had been involved for an STM-16 mapper device to be implemented in XCV2000E 2 years ago and the design required extremous routing resources. The point is that OSI-layer 1 protocols like SDH require huge monitoring functions. The protocol implementation is not a big issue. But payload mappings are complex, alarm monitoring and other trace buffers require enormous FPGA area (RAM mostly) + routing. You must think about which functions are necessary. Unnecessary functions must be dropped out of design. A high-tech additional FPGA engineer is a must to map the design into an FPGA technology. It is not easy to meet timing constraints SDH protocol requires. Utku Neeraj Varma wrote: > > Your application might be good fit for FPGAs, if you are not going to use > all the features that are provided by the standard chipset. Might even be > cheaper, but depends (see below) > > In my opinion, developing the framing and path processing is not so easy, > unless you have telecom experts in-house who also understand FPGA > implementation. It is best to buy an IP and get it customized for your > requirement. I have seen that an STM-1 and STM-4 path processor and framer > can be implemented in 16K Logic cells (equivalent to an XC3S1000) which can > be further optimized based on what you need and what you don't. The things > I've seen being implemented in FPGA are framing, path processing, TU > aligner, cross-connect functions and finally the mappers (PDH, Ethernet > etc.). > > From business standpoint, it all depends on the volume you are going to > generate, because unit price of FPGAs might be cheaper but > developing/buying/customizing the IPs can be expensive. If you are going to > build multiple solutions STM-1, STM-4 or greater, you can build volume since > the FPGA device will be common for all solutions, whereas standard chipset > will be different for each solution. > > The company I work for has a lot of IP in this area, and you can have a look > at them on http://www.cg-coreel.com/pages/products/iplist.htm If you are > interested in any of them, I can ask one of our business development guys to > talk to you, send me a message offine. > > HTH, > NeerajArticle: 56272
XILINX website posts that MicroBlaze runs at: 150MHz in Virtex2-PRO (-7) using 950 logic cells, 125MHz in Virtex2 (-5) using 950 logic cells, 85MHz in Spartan3 (-4) using 1050 logic cells, 75MHz in Spartan2E (-7) using 1050 logic cells. Well, Virtex2-PRO uses 130nm technology, Virtex2 and Spartan2E use 150nm, and Spartan3 uses 90nm. As far as I know, Virtex2 doesn't use strained silicon, silicon on insulator or low K dieletrics. And finally, Spartan3 is based on Virtex2 architecture. So: Why is Spartan3 slowly than Virtex2? (Very slowly!) Why does Microblaze takes 1050 locic cells in a Spartan3? (Same as in Spartan2!) Luiz Carlos KHOMP SolutionsArticle: 56273
Hi, What is the need for Parallel_case directive. I know that, it is to infer a MUX for case statement rather if/else. But, isn't implied that case statement itself a MUX? If so, why this synthesis directive again? Am i missing anything? Regards, MuthuArticle: 56274
Hello, I'm looking for an evaluation board of the Virtex 2 (actually for the Spartan 3 but as there are none available i will have to verify on the Virtex 2) I want to verify a ddr-sdram and 300 Mb's lvds link design. Two avaluation boards is also ok (one for ddr and one for lvds). Who has some idea's ? Yours Bram -- ================================================== Bram van de Kerkhof OCE-Technologies BV Building 3N38 St. Urbanusweg 43, Venlo, The Netherlands P.O. Box 101, 5900 MA Venlo ================================================== Direct dial : +31-77-359 2148 Fax : +31-77-359 5473 ================================================== e-mail : mailto:bvdk@oce.nl ================================================== www : http://www.oce.nl/ ==================================================
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