Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
I recently started using Nios 2.0 kit with Quartus II 2.1, and all seems to work fine: I use SOPC Builder to build my own CPU core, generate it, and place it in my Quartus II design. The problem comes when I want to do some simulations, I can't make it work with Quartus simulator. I tried a very simple core and placed it on a Quartus II design, placed input/output pins for clk, reset, etc. and programmed the core with a little program that writes values to a PIO port. When I simulate it, nothing happens, it's like there was no program, nothing happens at the PIO output. Since all documentation seems to point me to use Modelsim, I wonder if Quartus II simulator isn't capable of simulating Nios designs. The quick solution would be using Modelsim, but I find it quite difficult to use (at least much more than Quartus simulator) and I don't really need all of its advanced features. I haven't found any reference about using Quartus II simulator with Nios designs, so my question is: is it possible? Thanks in advance -- Jesus Jimenez jesjimenez@NOSPAMtelefonica.netArticle: 56226
"Austin Lesea" <Austin.Lesea@xilinx.com> ha scritto nel messaggio news:3ED7A5D5.45BFB4A8@xilinx.com... > It seems that many have used them for years affordably, > and I am happy > to hear you say that our proms are now 'affordable' in > your > applications. I'm talking of small designs, where often a 10-20$ FPGA is used and it is out of question to spend more for the PROM than for the FPGA itself, with the need to desolder and change the part at each firmware upgrade. Moreover, some time ago I tried to get some samples of PROMs from my distributor, and he told me (between fun and serious) that he didn't carry many of them, and I'd better have asked to my jewelry shop. Seems like it wasn't such a best-selling panacea like you say. :) The new flash PROMs are as big as the old PROMs (or bigger), but they are a lot less expensive and rewritable. If Xilinx has done them I think there is a reason, whether you agree or not. ;) -- LorenzoArticle: 56227
> The other problem, is that a little flash ram is not so little: 2.5 > Mbytes. Why don't FPGA chips support compressed bitstreams? I recently did a such a thing in software (on a self-reconfiguring SoC). The original bitstreams were in the range of 500 kbytes, and compressed down to only 16-25 kbytes. I left out all framing information and then used LZ77 and Huffman encoding. About 200 bytes of assembler code are necessary to reconstruct the original bitstream. Now that FPGAs even DES-encrypt their bitstreams, one should really think they have enough resources to support compression, too! MarcArticle: 56228
Hi Marc, Altera's Cyclone FPGAs support bitstream decompression within the FPGA itself. This allows you to use very cheap, dumb configuration devices (our EPCSxxx devices). For our other fpgas, you can use the advanced configuration devices (EPC4, EPC8, and EPC16). These devices support compressed bitstreams which are decompressed on-the-fly, so from the FPGA's perspective it looks like a regular uncompressed bitstream. As far as compression ratios go, your mileage will vary depending on how full your device is and how much routing is used. For full Cyclone designs, we see 1.7 - 2.1x compression, with about 1.9x being the average. The primary considerations for our compression algorithm are (a) high-speed decompression and (b) simplicity & size of hardware. Regards, - Paul Leventis Altera Corp. "jetmarc" <jetmarc@hotmail.com> wrote in message news:af3f5bb5.0305310507.396cd810@posting.google.com... > > The other problem, is that a little flash ram is not so little: 2.5 > > Mbytes. > > Why don't FPGA chips support compressed bitstreams? > > I recently did a such a thing in software (on a self-reconfiguring SoC). > The original bitstreams were in the range of 500 kbytes, and compressed > down to only 16-25 kbytes. I left out all framing information and then > used LZ77 and Huffman encoding. About 200 bytes of assembler code are > necessary to reconstruct the original bitstream. > > Now that FPGAs even DES-encrypt their bitstreams, one should really > think they have enough resources to support compression, too! > > MarcArticle: 56229
I agree, especially for small companies it would be a great thing to have these devices. Something like proASIC, however in system programming is in my opinion a little to complicated ... Concerning prices that is really a little an old story. I have once the possibility to participate in a deal a very big customer did buy SRAM based FPGA's. Really high volumes 100K+. Suddently you recognice that the poor man's price for small volume is more or less a 'marketing' price. The ranges for prices depending on the order volume can easily be several 100% to the unit price ... Actually what is interesting for me to see that for example Xilinx and Altera did wait for years until they introduced 'normal' prices for the external configuration PROMS. Again this is still a 'politial' price. If not why is it so, that I can get 2MBit serial data flash from SST for ~1US$ and at the same time a reprogrammable PROM for Xilinx or for an Altera device 2MB cost's about 10 times more ?? This is because this a is a 'political' or a 'marketing' price nothing else. To bad for all of us, that for example the reading array mode command is not all '1' or all '0' for those devices from SST or from ST or from others. If it would be like that, you could directly connect those tiny devices to a Xilinx part configuring itself in master serial mode ... Actually two of my designs to this, however it requires some glue around it ... have a nice day markus "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> schrieb im Newsbeitrag news:jSvBa.35664$3t6.560949@news.xtra.co.nz... > > "Peter Alfke" <peter@xilinx.com> wrote in message > news:3ED67E37.5C9FC432@xilinx.com... > > > Undoubtably there might be a market for what you describe, but it would > > be for single-chip applications, where cost is secondary, and > > performance does not count. We think that this too small a market for us > > to engage in. > > It might be an bigger marker than one thinks, a given vendor could sell > their own application specific chips with very little in the way of startup > costs. Then xilinx lowers the bar on being a fabless chip vendor. > > Imagine 100k - 500k gates in in a package with flash, the possibilities are > endless for replacing other vendors chips. One and 2 man bands can start > selling pre configured FPGA easily and quickly. It could spawn a nice little > industry, that I don't believe is feasible with external configuration. > > The stacking Idea sounds pretty nice, like the p-pro was but one expects > easier to manufacture and smaller in size. Or perhaps a new flash technology > will come about that can be build on the latest processes. > > We can all dream. > > Ralph > > >Article: 56230
On Sat, 31 May 2003 09:47:10 -0700, Markus Meng wrote: > I agree, especially for small companies it would be a great thing to > have these devices. Something like proASIC, however in system > programming is in my opinion a little to complicated ... > > Concerning prices that is really a little an old story. I have once the > possibility > to participate in a deal a very big customer did buy SRAM based FPGA's. > Really high volumes 100K+. Suddently you recognice that the poor man's > price for small > volume is more or less a 'marketing' price. The ranges for prices > depending on the > order volume can easily be several 100% to the unit price ... > > Actually what is interesting for me to see that for example Xilinx and > Altera did wait > for years until they introduced 'normal' prices for the external > configuration PROMS. > Again this is still a 'politial' price. If not why is it so, that I can > get 2MBit serial data > flash from SST for ~1US$ and at the same time a reprogrammable PROM for > Xilinx > or for an Altera device 2MB cost's about 10 times more ?? > > This is because this a is a 'political' or a 'marketing' price nothing > else. To bad for > all of us, that for example the reading array mode command is not all > '1' or all '0' for > those devices from SST or from ST or from others. If it would be like > that, you > could directly connect those tiny devices to a Xilinx part configuring > itself > in master serial mode ... The SST 45LF010 (1Mb) has an all ones read command so it will connect with only one inverter as glue, alas it is the last of it kind, the later (and larger) 25 series parts have an 03 (ISTR) read command so they need a $.80 PIC or tiny CPLD helper, still cheaper than anything from X or A... > > Actually two of my designs to this, however it requires some glue around > it ... > > have a nice day > markus > > "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> > schrieb im Newsbeitrag news:jSvBa.35664$3t6.560949@news.xtra.co.nz... >> >> "Peter Alfke" <peter@xilinx.com> wrote in message >> news:3ED67E37.5C9FC432@xilinx.com... >> >> > Undoubtably there might be a market for what you describe, but it >> > would be for single-chip applications, where cost is secondary, and >> > performance does not count. We think that this too small a market for >> > us to engage in. >> >> It might be an bigger marker than one thinks, a given vendor could sell >> their own application specific chips with very little in the way of > startup >> costs. Then xilinx lowers the bar on being a fabless chip vendor. >> >> Imagine 100k - 500k gates in in a package with flash, the possibilities > are >> endless for replacing other vendors chips. One and 2 man bands can >> start selling pre configured FPGA easily and quickly. It could spawn a >> nice > little >> industry, that I don't believe is feasible with external configuration. >> >> The stacking Idea sounds pretty nice, like the p-pro was but one >> expects easier to manufacture and smaller in size. Or perhaps a new >> flash > technology >> will come about that can be build on the latest processes. >> >> We can all dream. >> >> Ralph >> >> >> >>Article: 56231
Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3ED677B8.4863@designtools.co.nz>... > Vaughn Betz wrote: > > > > Hi Leon, > > > > As Paul points out, some random bounce is pretty much unavoidable. To > > minimize the bounce / get the best result, you can "seed sweep" which > > basically runs the compiler multiple times with slightly different > > starting point. By picking the best run, you can gain a little bit of > > speed, by picking the luckiest compile. This also tends to cut the > > random bounce from release to release, of course at the expense of > > compile time. > > > > To do this, go to Tools->Tcl Scripts->Sweeper. The script is pretty > > self-explanatory -- tell it what you want, and how many compiles > > you're willing to do. > > > > You can also do this manually by using the "Initial Placement > > Configuration" (sometimes called "Seed") setting in the > > Assignments->Settings->Fitter Settings dialog. > > > > As Paul pointed out, another option is to back-annotate the placement > > and/or routing to "lock in" the results of a good compile. All Altera > > devices support back-annotation of placement. Only Stratix, > > Stratix-GX and Cyclone support back-annotation of routing. > > > > When back-annotating placement to lock in performance, the best option > > is typically to back-annotate and demote assignments to LABs (i.e. > > don't lock down to the LE level). This reduces, but does not > > completely eliminate bounce unless you also lock down the routing too, > > and unfortunately locking down the routing isn't supported for the > > 10K. > > Interesting - these tools are (slowly) becomming more like PCB design > tools. > > Can you manually do a partial/local un-route, to support > 'incremental compiles' ? ( which should be a LOT faster ? ) > > If a revison is fed into a route-back-annotated design, > ( ie skip the manual un-route) how do the tools handle the conflicts ? > > -jg You can do this somewhat in 2.2, by manually editing constraint files, or just changing the placement in the GUI. The next version of Quartus (3.0) integrates routing constraints with LogicLock (which already had placement constraints), so you can divide your project up into modules, and save the placement and/or routing of each independently. So it's more powerful in 3.0. The constraint files for both placement & routing are ASCII, so you can edit them. Quartus also has a Tcl interface that lets you remove / change placement constraints as an alternative to directly editing the constraint files, but I don't think there's a Tcl interface for removing or adding routing constraints (now I'm curious so I'll go find out). If you change the placement (location constraint) on a few cells, the routing constraints to route to and from those cells will now probably not make sense. Quartus detects this, and throws the affected routing constraints away, with messages saying what it did, rather than failing routing. VaughnArticle: 56232
Peter Wallace <pcw@karpy.com> writes: > The SST 45LF010 (1Mb) has an all ones read command so it will connect with > only one inverter as glue, alas it is the last of it kind, the later (and > larger) 25 series parts have an 03 (ISTR) read command so they need a > $.80 PIC or tiny CPLD helper, still cheaper than anything from X or A... Even with the new XCF0xS from Xilinx? Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 56233
jetmarc wrote: > > > The other problem, is that a little flash ram is not so little: 2.5 > > Mbytes. > > Why don't FPGA chips support compressed bitstreams? > > I recently did a such a thing in software (on a self-reconfiguring SoC). > The original bitstreams were in the range of 500 kbytes, and compressed > down to only 16-25 kbytes. I left out all framing information and then > used LZ77 and Huffman encoding. About 200 bytes of assembler code are > necessary to reconstruct the original bitstream. > > Now that FPGAs even DES-encrypt their bitstreams, one should really > think they have enough resources to support compression, too! > > Marc These are some pretty impressive numbers. Can you share your code? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56234
Vaughn Betz wrote: > > Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3ED677B8.4863@designtools.co.nz>... > > Vaughn Betz wrote: > > > > > > Hi Leon, > > > > > > As Paul points out, some random bounce is pretty much unavoidable. To > > > minimize the bounce / get the best result, you can "seed sweep" which > > > basically runs the compiler multiple times with slightly different > > > starting point. By picking the best run, you can gain a little bit of > > > speed, by picking the luckiest compile. This also tends to cut the > > > random bounce from release to release, of course at the expense of > > > compile time. > > > > > > To do this, go to Tools->Tcl Scripts->Sweeper. The script is pretty > > > self-explanatory -- tell it what you want, and how many compiles > > > you're willing to do. > > > > > > You can also do this manually by using the "Initial Placement > > > Configuration" (sometimes called "Seed") setting in the > > > Assignments->Settings->Fitter Settings dialog. > > > > > > As Paul pointed out, another option is to back-annotate the placement > > > and/or routing to "lock in" the results of a good compile. All Altera > > > devices support back-annotation of placement. Only Stratix, > > > Stratix-GX and Cyclone support back-annotation of routing. > > > > > > When back-annotating placement to lock in performance, the best option > > > is typically to back-annotate and demote assignments to LABs (i.e. > > > don't lock down to the LE level). This reduces, but does not > > > completely eliminate bounce unless you also lock down the routing too, > > > and unfortunately locking down the routing isn't supported for the > > > 10K. > > > > Interesting - these tools are (slowly) becomming more like PCB design > > tools. > > > > Can you manually do a partial/local un-route, to support > > 'incremental compiles' ? ( which should be a LOT faster ? ) > > > > If a revison is fed into a route-back-annotated design, > > ( ie skip the manual un-route) how do the tools handle the conflicts ? > > > > -jg > > You can do this somewhat in 2.2, by manually editing constraint files, > or just changing the placement in the GUI. The next version of > Quartus (3.0) integrates routing constraints with LogicLock (which > already had placement constraints), so you can divide your project up > into modules, and save the placement and/or routing of each > independently. So it's more powerful in 3.0. > > The constraint files for both placement & routing are ASCII, so you > can edit them. Quartus also has a Tcl interface that lets you remove > / change placement constraints as an alternative to directly editing > the constraint files, but I don't think there's a Tcl interface for > removing or adding routing constraints (now I'm curious so I'll go > find out). > > If you change the placement (location constraint) on a few cells, the > routing constraints to route to and from those cells will now probably > not make sense. Quartus detects this, and throws the affected routing > constraints away, with messages saying what it did, rather than > failing routing. Just my $0.02 worth. I did a project using MaxPlus2 a couple years ago. We were pushing density on a 10K100A part and also needed speed on a portion of it. We found that the placement the tools were using could not be understood by us. When we tried using constraints, we found that as often as not, we were working against the tool rather than helping it. So constraints are not an easy tool to use effectively. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56235
jetmarc wrote: > I recently did a such a thing in software (on a self-reconfiguring SoC). > The original bitstreams were in the range of 500 kbytes, and compressed > down to only 16-25 kbytes. I left out all framing information and then > used LZ77 and Huffman encoding. About 200 bytes of assembler code are > necessary to reconstruct the original bitstream. > > Now that FPGAs even DES-encrypt their bitstreams, one should really > think they have enough resources to support compression, too! I don't care to much about the compression, (you're going to be mad, if you change your design, and it doesn't fit in the nice smaller part anymore) But, anybody out here has an idea, why there is no bitstream encryption on the spartan 3 ? With all this gates & memory, you could do impressive designs, but to keep them for safe you still have to go to the virtex chips ... cheersArticle: 56236
antti@case2000.com (Antti Lukats) writes: > latest Xilinx iMpact doesnt seem to support the old style Parallel III > cable any more, and it seems there is no way to get the bitstream > into Spartan - the iMpact generated STAPL file does not work with JAM > player 2.3 gives bound error. The source of this problem might be that impact generates some extra instructions to reduce the size of the SVF file when there are multiple devices in a scan chain. SVF files generated by jtagprog does not include these instructions. Users which a single device in their jtag chains might not experience any differences between the two. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 56237
I like Jeopardy! -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email) "Petter Gustad" <newsmailcomp5@gustad.com> wrote in message news:87u1ba3n0p.fsf@zener.home.gustad.com... > antti@case2000.com (Antti Lukats) writes: > Petter > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail?Article: 56238
On Sat, 31 May 2003 12:33:13 -0700, Magnus Homann wrote: > Peter Wallace <pcw@karpy.com> writes: > >> The SST 45LF010 (1Mb) has an all ones read command so it will connect >> with only one inverter as glue, alas it is the last of it kind, the >> later (and larger) 25 series parts have an 03 (ISTR) read command so >> they need a $.80 PIC or tiny CPLD helper, still cheaper than anything >> from X or A... > > Even with the new XCF0xS from Xilinx? > > Homann Unless the XCF02 (for example) is less that ~$1.80 in low quantities, yes PCWArticle: 56239
> Just my $0.02 worth. I did a project using MaxPlus2 a couple years > ago. We were pushing density on a 10K100A part and also needed speed on > a portion of it. We found that the placement the tools were using could > not be understood by us. When we tried using constraints, we found that > as often as not, we were working against the tool rather than helping > it. So constraints are not an easy tool to use effectively. It is hard to improve the push-button placement results through constraints, and I'm pretty sure it's impossible to beat the router's results. For 10K and 20K, applying region constraints can help, as a human can sometimes figure out how to partition their design to fit the hard routing hiearchy boundaries in these parts better than the placer. In the case of Stratix and Cyclone, it is much harder since there are no longer any hard boundaries. For very regular/datapath designs (hi Ray) with short critical paths, relative placement constraints can still be beneficial. Many times that users experience optimization success through the application of placement constraints, this is purely due to random noise -- if the placer seed is swept across the before- and after-designs, any advantage often disappears. This is a good thing... it means that push-button compile is doing a good job. Note: The application of placement and routing back-annotation in order to preserve the performance of a previously successful fit is still _very_ valuable in many designs. It allows one to move a design from one version of Quartus to another, or to make small changes to a design without affecting the rest of it. Regards, Paul Leventis Altera Corp.Article: 56240
I'd say it's a definition of terms. You could say: "Generally, only trucks have a flat bed -- Why can't cars?" Then some fool came up with the idea for the El Camino and we all know where that went... Maybe if you drove around with an FSM in your datapath, people would make fun of you, too. So, in my world, an FSM is by definition a control structure. Datapaths are controlled by FSMs, but most people draw a line there somewhere. Oddly enough, ALUs are likewise found in the datapath isle, but people feel perfectly comfortable with ALUs in a controller. Then again, maybe the address generation unit is really part of the datapath. Confused as ever, Jake muthu_nano@yahoo.co.in (Muthu) wrote in message news:<28c66cd3.0305302353.40ac5ebc@posting.google.com>... > Hi, > > Generally control path alone have FSM. > > Whats wrong in having FSM for data path too? > > Regards, > MuthuArticle: 56241
Hi, I am reading Prof. Jan Rabaey's book: "Low-energy FPGAs - Architecture and design". However, I found it difficult to get one data mentioned in his book p35. The table is as follows: Power supply: 3.3 V One CLB driving 9 single segments(Energy per transition cycle): 320 pJ One CLB with no load (Energy per transition cycle): 39pJ Capacitance per segment: 2.9 pF Rabaey said following this table: The energy of a single segment line is 39 pJ. Assuming a full voltage swing on the line, this translates to a capacitance of 2.9 pF. My questions are: 1. How is 39 pJ got for each single segment?According to my understanding, it should be (320-39)/9=31.2 pJ 2. How to get 2.9 pF number? Thank you very much! sincerely ------------- Kuan Zhou ECSE departmentArticle: 56242
"Valli" <sri_valli_design@hotmail.com> wrote in message news:d9acfecb.0305310224.4c238718@posting.google.com... > hi, > > In my design I have few internal enable signals, some of them are > always one and some follows the a gated clock. > > What I would like to know is: In a design if a pin is permanently at > VDD consumes more power or a gated clocked like signal(changes to 1 to > 0, and 0 to 1) consume more power? assuming other i/p are same in the > design. The tradition of CMOS is that it only consumes power changing state. During a change both transistors are partially on, resulting in current flow, and also charging/discharging of the load capacitance of the metalization layers. This may be less true as density increases, but as far as I know it is still true. Some devices spec. the power consumption as proportional to clock frequency. -- glenArticle: 56243
emanuel stiebler <emu@ecubics.com> writes: > But, anybody out here has an idea, why there is no bitstream > encryption on the spartan 3 ? With all this gates & memory, you could > do impressive designs, but to keep them for safe you still have to go > to the virtex chips ... It's called product differentiation. More features, more dollars.Article: 56244
Hello I designed one project for Xilinx. I done it and assigned my pin configuration to xilinx cover. And now I would like to use this cover in ProtelDxp. Does anybody know if this is possible to import this cover from WebPack into Protel ? thanks for help GorgoArticle: 56245
Hi, this is exactly how I did it on 66MHz PCI Bus card having a Spartan-IIE 300 a 2MB serial data flash and a cheap CPLD. This is all well below 2US$ for configuration. It even beats what Xilinx is offering us the 3Q or 4Q this year .-( That's the way it is. I am jst wondering why SST or ST or others do not jump on this train by simply changing the command for the read array mode to something like all '0' and all '1'. Then the only thing you need is the inverter you mentioned and then you have a ISP configuration from for 1..2US$. Then the price is adequate and you can neglect it and talk about the FPGA prices ... Maybe you remember Gorbatschows ...if you come to late then ... In my opinion the marketing responsible people at Xilinx and at Altera did wait to long to provide us with a cost effective solution for ISP configuration devices. Especially today having partial reconfiguration, soft cores, you can realize a in field updatable electronic device with an FPGA SRAM based from the two big ones, and an external serial data flash. A mini cpu system insisde the fpga can handle the user request for firmware updates ...and reprograms the external configuration device ... markus "Peter Wallace" <pcw@karpy.com> schrieb im Newsbeitrag news:pan.2003.06.01.00.39.04.915776.21805@karpy.com... > On Sat, 31 May 2003 12:33:13 -0700, Magnus Homann wrote: > > > Peter Wallace <pcw@karpy.com> writes: > > > >> The SST 45LF010 (1Mb) has an all ones read command so it will connect > >> with only one inverter as glue, alas it is the last of it kind, the > >> later (and larger) 25 series parts have an 03 (ISTR) read command so > >> they need a $.80 PIC or tiny CPLD helper, still cheaper than anything > >> from X or A... > > > > Even with the new XCF0xS from Xilinx? > > > > Homann > > > Unless the XCF02 (for example) is less that ~$1.80 in low quantities, yes > > PCWArticle: 56246
Eric Smith wrote: > emanuel stiebler <emu@ecubics.com> writes: > >>But, anybody out here has an idea, why there is no bitstream >>encryption on the spartan 3 ? With all this gates & memory, you could >>do impressive designs, but to keep them for safe you still have to go >>to the virtex chips ... > It's called product differentiation. More features, more dollars. But if you used the 5 million gates for your design, would you publish it ? ;-)Article: 56247
In article <Pine.SOL.3.96.1030601003330.23460A-100000@vcmr-86.server.rpi.edu>, Kuan Zhou <zhouk@rpi.edu> wrote: > Hi, > I am reading Prof. Jan Rabaey's book: "Low-energy FPGAs - > Architecture and design". However, I found it difficult to > get one data mentioned in his book p35. > The table is as follows: > > Power supply: 3.3 V > One CLB driving 9 single segments(Energy per transition cycle): 320 pJ > One CLB with no load (Energy per transition cycle): 39pJ > Capacitance per segment: 2.9 pF > > Rabaey said following this table: The energy of a single segment line is > 39 pJ. Assuming a full voltage swing on the line, this translates to a > capacitance of 2.9 pF. > > My questions are: > 1. How is 39 pJ got for each single segment?According to my understanding, > it should be (320-39)/9=31.2 pJ Looks right > > 2. How to get 2.9 pF number? Energy in a capacitor: E = 1/2 V^2 C If a transition cycle is rise and fall (rather than just one edge) E = (1/2 + 1/2) V^2 C = V^2 C C = E/V^2 = 2.9 pF if you use 31.2 pJ, 3.6 pF if you use 39 pJ So it looks like the 39 pJ is a typo, but the 2.9 pF is correct. -- David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com)Article: 56248
Generally, it's OK to put various devices in a single chain. You simply have to use a configuration tool to describe the JTAG chain to the debugger so that it knows where the device you are trying to debug lies in the chain. Part of the description is the number of devices, and the size in bits of the instruction register. The debugger will ignore all the other devices by using the bypass instruction and placing them in bypass mode. This allows the debugger to "focus" on the device in the chain you are trying to debug. "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3ED6C3AD.410293B3@yahoo.com... > Fred Viles wrote: > > > > rickman <spamgoeshere4@yahoo.com> wrote in > > news:3ED5FB2E.D1EF6320@yahoo.com: > > > > > Fred Viles wrote: > > >> > > >> rickman <spamgoeshere4@yahoo.com> wrote in > > >> news:3ED3A6C7.229A5223@yahoo.com: > > >> > > >> >... > > >> > The second will have an ARM MCU and a large CPLD. > > >> >... > > >> > > >> There are JTAG probes available for ARM, at least, that have no > > >> problem with there being mulitple TAPs on the JTAG chain. > > >> (MultiICE from ARM and MAJIC from EPI, just to name two). > > >> Unless your CPLD programmer can't handle it, you shouldn't need > > >> to provide for isolating the TAPs in this section. > > >>... > > > To the best of my knowledge, the number of devices in the chain > > > has little to do with the hardware. I belive it is entirely up > > > to the software. > > > > Well sure. For some definition of "software" which varies > > depending on the probe you choose. E.g. for MultiICE it's an RDI > > compliant DLL on the PC, and for MAJIC it's firmware in the probe > > itself. For a cheap parallel port bit-banger like a Wiggler, it's > > host software either in a shared library or directly in the > > debugger. > > > > But I guess I don't understand how that observation is relevant to > > the question of whether your target board needs to isolate the > > various TAPs or not. I would think the only question is whether > > the probe+software you will use for each device supports the device > > not being the only TAP on the chain. > > > > I don't know about your CPLD, so I was just pointing out that for > > the ARM, at least, the answer can be yes. > > I still don't think I am with you. You are talking about firmware on > the probe having something to do with "understanding" the nature of the > chain. To the best of my knowledge (I have not dug into how the > advanced probes work) this is still a function of the debugger software > on the PC. If the debugger only supports one type of probe, then so be > it. But I don't think the probe itself determines whether or not the > software can work with multiple devices in a chain. > > I am asking about experiences others have had in this regard. I am not > clear if you are talking from experience or from a general knowledge of > how these devices work. > > I am also asking for ideas on how probe/software limitations have been > handled by others. Surely I am not the first to encounter limitations > of connector space on such a board. > > > > > I am not up to speed on the many suppliers of > > > debugging hardware and software for the ARM yet. I have heard a > > > lot of recommendations, but not many provide info on *why* one > > > combination is good or bad. > > > > That's a big subject to cover. There are a *lot* of products on > > offer from a lot of companies, not to mention the freeware/hobbiest > > options. They all have strengths and weaknesses, and what makes > > one a better solution than another is largely dependent on your > > particular needs. > > > > Do you need download performance? Multi-TAP support? Multi- > > Processor support? RTCLK support? ETM support? Networkability? > > Support for a particular debugger? Low cost? etc. > > I would much prefer a low cost solution. I described my chains in my > earlier post. I have one chain with a single CPLD, no problem. A > second chain has an ARM and a Lattice 5512MB CPLD. This CPLD is also > programmable from the ARM MCU, so the CPLD JTAG connection is needed > only in manufacturing test. The third chain has a TI DSP and a Xilinx > FPGA. Again, the FPGA has no need to be configured by JTAG, so it will > only be accessed during manufacturing test. I expect to provide a DSP > debug connector for my customers to write their code. The ARM debug > conector will only be needed by us unless our customers want to make > mods to the code. So that connector would not be needed in production. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56249
Eric Smith wrote: > > emanuel stiebler <emu@ecubics.com> writes: > > But, anybody out here has an idea, why there is no bitstream > > encryption on the spartan 3 ? With all this gates & memory, you could > > do impressive designs, but to keep them for safe you still have to go > > to the virtex chips ... > > It's called product differentiation. More features, more dollars. Another way to put it is, they charge you for what you get, not what it costs to make. In order to be able to charge more for the Virtex family, they can't put all the features in the low cost Spartan line, even if the features cost very little. But then that also leaves the door open for the competition to one up them if they are interested in giving up that feature as a high end item. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z