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Messages from 56350

Article: 56350
Subject: Re: JTAG madness
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 03 Jun 2003 16:02:12 -0400
Links: << >>  << T >>  << A >>
Dziadek wrote:
> 
> In the past I have done a board with the TI DSP and a CPLD in chain. There
> were some problems at the beginning to configure the debugger but later it
> worked OK. I have also a board with two SHARCs and few CPLDs and FPGAs in
> series and everything works OK.
> 
> But for now I prefer separate connectors: one for the processor and one for
> the CPLD/FPGA. With two connectors you can have connected both the processor
> emulator and the FPGA/CLPD programmer at the same time. This speeds up the
> debugging because you have both the hardware tool and software tools ready
> and can quickly update the H/W and S/W.

Thanks for your comments.  I won't need to use the scan chain for
debugging or programming the CPLD/FPGAs.  The processor will do that.  I
need them in the same chain for production boundary scan testing.  But
knowing that the TI CC will work ok with the PLDs in the chain is
important.  

Did it matter if the DSP was first or last in the chain?  I seem to
recall being advised to make the DSP last.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 56351
(removed)


Article: 56352
Subject: Re: Xilinx Spartan download with Parallel III cable
From: ben@ben.com (Ben Jackson)
Date: Tue, 03 Jun 2003 20:33:44 GMT
Links: << >>  << T >>  << A >>
In article <Ic0Da.54583$M01.37483@sccrnsc02>,
David Kinsell <kinsell@poboxyz.com> wrote:
>
>Even when powering it with 5 volts, I've sometimes had to tack small
>caps across the TCK line in order to make it work reliably.

The schematic I built from had 100 ohm/ 100pF low-pass filters on all
of the output lines:

http://toolbox.xilinx.com/docsan/3_1i/data/common/hug/figures/fig013.htm

> That trick
>didn't work in the current situation, the software showed a dozen devices
>in the chain when there was only two.

That sounds like a power problem.  ImPACT enumerates infinitely many
devices if the target circuit isn't powered.  It even has a warning popup
at 100 or 1000 so you can abort.

Maybe your device isn't using 1N5817s?  Put a meter on pin 15 of the
parallel cable, which should be 2 diode drops from the target VCC.

-- 
Ben Jackson
<ben@ben.com>
http://www.ben.com/

Article: 56353
Subject: Re: SONET/SDH chipset on FPGA
From: "Nial Stewart" <nial@spamno.nialstewart.co.uk>
Date: Tue, 3 Jun 2003 22:07:09 +0100
Links: << >>  << T >>  << A >>
> Hi all,
> I want to do some basic sonet/sdh mapping, framing, pointer processing
> on xilinx spartan IIE. I see PMC-Sierra chipset on SDH, they are do
> many different things that I do not need for a basic STM-1 link. ( I
> want do multiplex 16*16Mhz signal on STM-1 frame). PMC-Sierra temux
> and spectra chipset are very complex and expensive ( $600 for both ).
> Does anybody has practical experince on this. I look for a more clear
> perspective on FPGA implementation.
> Best Regrads.
> M. Naderi

Despite what's said below, this isn't that difficult if you've a
bit of experience with FPGA design and you think ahead when doing
the initial system and module designs.

I've done PDH mappings -> STM1 and my only problems were interfacing
with what was providing the PDH source. Even the pointer processing
pretty much P+R'd first time and this included the ability to do
valid and invalid movement bursts. (See my web site below for more
details).

If you're desperate to get this built quickly an IP core might be
the way to go, otherwise I'd do it yourself, or I'm shortly available
if you want someone else to do it for you :-)


Nial.

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk




Article: 56354
Subject: Re: FPGA's an Flash
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 03 Jun 2003 14:09:31 -0700
Links: << >>  << T >>  << A >>

rickman wrote:
> 
>
> I think Peter is very good at being professional.  But claiming that the
> competition's technology *must* be inferior because the company is not
> doing well is just plain silly. 
 
Peter replies: Here is what I posted, verbatim:

"Then we have to ask ourselves:
Why are all these companies so small and/or doing so poorly?
The market is the final arbiter. Success in this industry is defined by
a profitably  growing sales volume..."

>   When they started trashing the
> competition, and in this case in spite of the facts, I let it push a
> button.

 Peter replies: 
I was not trashing the competition. In a way, I was saying: If their
stuff is so good, why is that company not successful?  
Lattice, once one of the Big Three in sales volume is now far behind
(inspite of having absorbed AMD's and Lucent's programmable logic lines.)

I maintain: A profitably growing sales volume, and a rising share of
market, are both a favorable vote from the user community, voting with
their money. That's the advantage of capitalism: Feedback is pretty
swift, either encouraging or devastating. 
And we, as well as all our competitors, are watching that feedback,
daily. 
Now let me get back to the technical issues...
Peter Alfke

Article: 56355
(removed)


Article: 56356
Subject: Re: FPGA's an Flash
From: jetmarc@hotmail.com (jetmarc)
Date: 3 Jun 2003 14:33:29 -0700
Links: << >>  << T >>  << A >>
>  20:1 sounds very high compression, esp of 'design' not 'empty' FPGA.

I have pointed this out by email already, but I see new followups
daily.
So here's more information:  The bitstream I compressed as described,
was for an Atmel chip, not Xilinx.  I don't know how much redundancy
Xilinx bitstreams carry, but Atmel's definately have a lot.  There's
the encoding itself, there's a lot of framing information (useful for
partial reconfiguration), there's extra information for power-saving
(avoids bus clashes by loading some bits twice), and last not least
there are the bits themselves.

My compressor removes everything, except the very bits that the FPGA
uses (the decompressor algorithmically re-creates all the excess
stuff on the fly).  Then, the bits are compressed with a scheme
similar
to LZH.

That is, my compressed bitstream is shorter than a .RAR of the
original
bitstream file.  On the other hand, it is bigger than a .RAR of the
"bit image" (without framing info) because my decompressor has less
resources than a win32 program and thus achieves slightly worse
ratios.

You will get an approximate idea (+-25%) of what is possible with
Xilinx bitstreams, when you .RAR the bitstream file.  I don't have
any at hand, so check yourself.

The code itself is quite simple, once you fix the LZ parameters and
Huffman tree storage format.  I found that this particular encoding
method allows for a very tiny code footprint of the decompressor:

http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&oe=utf-8&selm=3d779a37%40news.tce.com

For the LZ encoding, I found that 8-bit symbols fit best to my 8-bit
MCU.

>  We did some trials with Run Length Encoding

I did some experiments with RLE, too, both on byte and on bit basis
(similar to FAX encoding).  It didn't work out well, and compression
ratio becomes worse when the design is more complex (when you need
compression most!).

Marc

Article: 56357
Subject: Re: FPGA's an Flash
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 03 Jun 2003 14:48:24 -0700
Links: << >>  << T >>  << A >>

jetmarc wrote:
> 
> > I did some experiments with RLE, too, both on byte and on bit basis
> (similar to FAX encoding).  It didn't work out well, and compression
> ratio becomes worse when the design is more complex (when you need
> compression most!).

Just to clarify: The (uncompressed) Xilinx bitstream is of constant
length for any given device, completely independent of the implemented
design complexity.
You can read the precise  length for any chip in its the data sheet.
Peter Alfke, Xilinx Applications

Article: 56358
Subject: Celoxica RC200
From: erdincozturk@su.sabanciuniv.edu (Erdinc Ozturk)
Date: 3 Jun 2003 15:31:17 -0700
Links: << >>  << T >>  << A >>
Hi,

Can anyone help me about programming a RC200 board?

I wrote a simple vhdl code (an and gate), assigned ports with
floorplanning tool of xilinx foundation 3.1 (I assigned buttons on the
board as inputs and one of the blue leds as output. That means J5 and
K5 as inputs and K6 is output.) I created the bit file with P&R tools
of foundation 3.1, I tried to configure the board with the bit file I
created using the FTU2 program but it did not work. The board passes
the test of the program, it starts to configure the board but it does
not finish programming the board, I waited about 40 minutes but
nothing changed.

Article: 56359
Subject: Re: size of SRAM, antifuses and EPROM elements
From: pagercam@yahoo.com (Mark Sandford)
Date: 3 Jun 2003 16:20:54 -0700
Links: << >>  << T >>  << A >>
wolfgang@byke.com (Wolfgang Schmiesing) wrote in message news:<eb5a527f.0306030745.63fe8db5@posting.google.com>...
> Hello,
> 
> Can anyone tell me dimensions of FPGA programming elements like
> SRAMs, antifuses or EPROMs? How big are the differences in size between them?

The cell sizes for the memory elements are only one portion of the
puzzle what support structures are required, and how they are aranged
play a big roll in the ability to how dense they maybe place together,
varry the FPGA architecture might allow the storage cells to be more
widely space so the actual size less of an issue.   Nothing is ever a
simple as a one number answer and changing one parameter often has
cascading effects on other parts of a design and not all technologies
and processes are compatible.

Article: 56360
Subject: Re: spartan2e vs cyclone
From: Karsten Becker <KB@Karsten-Becker.de>
Date: Wed, 04 Jun 2003 01:56:01 +0200
Links: << >>  << T >>  << A >>
Steve Knapp wrote:
> If designing for applications going to production early next year and if
> you are considering changing FPGA families, you should also consider the
> recently announced Spartan-3 family.  Spartan-3 is manufactured on
> advanced 90 nm (0.09u) technology, offering about a 50% area advantage
> over 0.13u.  Software support is already available in ISE 5.2i, but I
> recommend downloading the latest service pack for recent feature
> upgrades.
> 
>    http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
> 
If you just would have added support for the full spartan-3 line in your 
ISE Webpack it might have been a reason to wait for me. But as the 
Cyclone-family is fully supported by alteras quartus-2-web edition I 
don't see any point paying a xxx dollars license/per year + xxx dollars 
for a board....
BTW. I'm a student and I want to have a very low entry price. The more 
features are avaible for free, the better for me.
So I start loving Quartus-II and will use it in future.

Karsten


Article: 56361
Subject: Re: Online courses for FPGA
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Wed, 04 Jun 2003 00:37:53 GMT
Links: << >>  << T >>  << A >>
You could start here:

http://university.xilinx.com/

http://www.aldec.com/default.aspx

http://www.xess.com/index.html

http://search.yahoo.com/search?x=op&va=verilog+tutorial&va_vt=any&vst=0&vd=all&fl=0&ei=ISO-8859-1&vm=p&n=20

http://search.yahoo.com/search?p=vhdl+tutorial&ei=UTF-8&vm=p&n=20&fl=0&x=wrt

http://www.google.com/search?hl=en&ie=UTF-8&oe=UTF-8&q=xilinx+tutorial

...you get the idea.


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"




"Atif" <atif@kics.edu.pk> wrote in message
news:6a0a3f23.0306030258.42d93cfe@posting.google.com...
> Is there any free online course available for FPGA using xilinx?
> In case of not free, how much it costs?
> Regards
> Atif



Article: 56362
(removed)


Article: 56363
Subject: Re: Spartan-3 questions?
From: Karsten Becker <KB@Karsten-Becker.de>
Date: Wed, 04 Jun 2003 03:23:45 +0200
Links: << >>  << T >>  << A >>
rickman wrote:
> Eric wrote:
>>.....especially since some of our applications focus on DSP. Does...

> Again, I don't want to knock Xilinx (I like 'em... I like 'em a lot!),
> but the Altera Cyclone is looking pretty good and priced right.  The
> Cyclone parts have as much or more RAM bits than the XC2S parts. 
> Compared to the XC3S they are in smaller blocks.  If you don't need a
> full 18kbits in each block, the Cyclone may be just what you need with
> 4kbit blocks.  
> 

If they just would have placed some DSP blocks on it.....

Karsten


Article: 56364
(removed)


Article: 56365
(removed)


Article: 56366
(removed)


Article: 56367
(removed)


Article: 56368
Subject: Re: For Loop Synthesis
From: "Stan Lackey" <stanlackey@hotmail.com>
Date: Tue, 3 Jun 2003 23:21:00 -0400
Links: << >>  << T >>  << A >>
You don't need loops.  Reading is:

always @(posedge clk) dout <= mem[raddr];

and writing is

always @(posedge clk) if (we) mem[wadr] <= din;

Also, you shouldn't be using resets, you certainly shouldn't be using
asynchronous resets, and in the very rare case that resetting is necessary,
why on earth would you make the reset low true ??  Why would anybody ever
make anything low true?  Since the 80's, I mean.

Anyway, this will synthesize into a register file made of flops and muxes.
Synthesis tools are very much hyped in terms of their true capabilities.  If
you want a vendor's memory instanced, you have to hand instance it yourself.

-Stan

"Muthu" <muthu_nano@yahoo.co.in> wrote in message
news:28c66cd3.0306030744.5830229d@posting.google.com...
> Hi,
>
> I want to build a memory using register array. I tried as below.
>
> //----------------------------
>
> reg[31:0] mem[DEPTH-1:0];
>
> // Read LOGIC
>
> always @(posedge clk or negedge rst_n)
> begin
>   if(!rst_n)
>   begin
>     dout <= 0;
>   end
>   else
>   begin
>     for(i=0; i<DEPTH ; i=i+1)
>     begin
>       if(raddr == i)
>       begin
>         dout <= mem[i];
>       end
>     end
>   end
> end
>
> // Write LOGIC
>
> always @(posedge clk or negedge rst_n)
> begin
>   if(!rst_n)
>   begin
>     for(j=0; j<DEPTH; j=j+1)
>     begin
>       mem[j] <= 0;
>     end
>   end
>   else
>   begin
>     if(we)
>     begin
>       for(k=0; k<DEPTH; k=k+1)
>       begin
>         if(waddr == i)
> begin
>           mem[i] <= din;
> end
>       end
>     end
>   end
> end
>
> ---------------------------
>
> In the above Piece of code is not inferring all the register elements
> for memroy. It is replacing registers by LOGIC, since it is
> unchanging.
>
> How do i code a memory using register array, which could be
> parameterized. So, for-loop option could be better. But it is not
> giving the desired result.
>
>
> Regards,
> Muthu



Article: 56369
(removed)


Article: 56370
(removed)


Article: 56371
Subject: Re: An FPGA is flying to Mars
From: rk <stellare@NOSPAMPLEASE.erols.com>
Date: 4 Jun 2003 03:37:44 GMT
Links: << >>  << T >>  << A >>
Mike Butts wrote:

> The May 2003 issue of IEEE Spectrum has a nifty and
> detailed article on the exciting British Beagle 2
> lander hitching a ride on ESA's Mars Express orbiter,
> set to launch soon and arrive in December.  
> 
> Its robotic arm carries a bunch of instruments and
> other devices.  "Discrete electronic interfaces
> between each instrument and the lander would have
> been complex to build and heavy as well.  So the 
> PAW uses a single interface with a field-programmable
> gate array that can reconfigure itself to match each
> instrument's needs."
> 
> Excellent!  One of you must be able to tell us more.
> Who's the clever designer?  Who's the lucky vendor?  
> What device?  Rad-hard?  Fault-tolerant?  Designed 
> in what language?  Verified how?  Bitstreams stored 
> where and loaded by what?  Can they upload new 
> bitstreams from Earth?  (Now that's an UPload!)
> What if DONE doesn't go high?
> 
> Will this be the first FPGA in Mars space?

I don't recall if there were any on Mars Pathfinder but there was 
definitely an FPGA on Mars Global Survey on the laser altimeter.  The 
FPGA got put onto the instrument as it was upgraded; the original laser 
altimeter was on the ill-fated Mars Explorer.

There are also FPGAs on the way to Saturn on the Cassini spacecraft.

 
> Most important of all, will they send a paper to
> FPL 2003 or FPGA 2004 or FCCM 2004?

MAPLD 2003?  ;-)

-- 
rk, Citizen, Noooo Yawk
"Sometimes when you connect the dots you get a picture.  Other times you 
just have a bunch of dots."
-- rk, January 23, 2003

Article: 56372
Subject: Re: Antifuse and CCC FPGA
From: rk <stellare@NOSPAMPLEASE.erols.com>
Date: 4 Jun 2003 03:47:58 GMT
Links: << >>  << T >>  << A >>
Austin Lesea wrote:

                  [ snip ]

> But is Antifuse FPGAs, there is just no possible way to test,
> period. It isn't even a question of time, cleverness, or cost.  If
> the fuse doesn't blow, there is no way to know in advance....

But you know before it leaves the programmer and gets on the board.  The 
reliability after passing programming is quite excellent.  If you had to 
test on the board for the 2-3% dropout then that would be bad.  As an 
aside, something I've looked into, fault coverage pre-programming for 
antifuse FPGAs can be quite excellent through on-chip test support.

-- 
rk, Citizen, Noooo Yawk
"Sometimes when you connect the dots you get a picture.  Other times you 
just have a bunch of dots."
-- rk, January 23, 2003

Article: 56373
(removed)


Article: 56374
Subject: Re: Xilinx Spartan download with Parallel III cable
From: "David Kinsell" <kinsell@poboxyz.com>
Date: Wed, 04 Jun 2003 04:00:57 GMT
Links: << >>  << T >>  << A >>

"Ben Jackson" <ben@ben.com> wrote in message news:IC7Da.559883$Si4.511236@rwcrnsc51.ops.asp.att.net...
> In article <Ic0Da.54583$M01.37483@sccrnsc02>,
> David Kinsell <kinsell@poboxyz.com> wrote:
> >
> >Even when powering it with 5 volts, I've sometimes had to tack small
> >caps across the TCK line in order to make it work reliably.
>
> The schematic I built from had 100 ohm/ 100pF low-pass filters on all
> of the output lines:
>
> http://toolbox.xilinx.com/docsan/3_1i/data/common/hug/figures/fig013.htm
>

Those aren't classic low pass filters, the caps should be on the other
side of the resistors.  I've used 470 pf on the other side of the TCK
resistor and gotten much better results programming an original Spartan
part.



> > That trick
> >didn't work in the current situation, the software showed a dozen devices
> >in the chain when there was only two.
>
> That sounds like a power problem.  ImPACT enumerates infinitely many
> devices if the target circuit isn't powered.  It even has a warning popup
> at 100 or 1000 so you can abort.

No, it wasn't power.  Taking the cap off let the two devices be correctly
identified, but Done wouldn't go high at the end of programming.  I tried
looping while reading the idcode, and generally got single bit errors
after 300-800 passes.   So something in the data transfer is marginal.


> Maybe your device isn't using 1N5817s?  Put a meter on pin 15 of the
> parallel cable, which should be 2 diode drops from the target VCC.

I opened the case today, and the buffers were powered by VCC
minus one diode drop, like your version of the schematic shows.  Looked
for noise on the supply during data transfer, saw a bit, but nothing too
disturbing.

In addition to the cable supplying marginal voltages to the parallel port,
the parallel port is going to be driving some inputs of the 74HC125 parts
at 4-5 volts, through a resistor.  Recommended operating input voltage
is 0-Vcc, so they're being operated out of spec when the cable is powered
by lower voltages used with modern parts.  I think those Answer Records
claiming low-voltage operation are a bit on the optimistic side.

Also looked at the clock rate, it's supposed to be 200 Khz, and I
was seeing 300 Khz.  I guess the software just can't slow down my
2.4 Ghz machine adequately.

Dave Kinsell

> -- 
> Ben Jackson
> <ben@ben.com>
> http://www.ben.com/





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