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Threads Starting Mar 1999
14973: 99/03/01: Daryl Bradley: Virtex development boards
14974: 99/03/01: <rajesh52@hotmail.com>: Verilog FAQ
14976: 99/03/01: saffary: graphic Lcd control core
14977: 99/03/01: Ray Andraka: Re: graphic Lcd control core
15016: 99/03/03: Davide Rizzo: Re: graphic Lcd control core
15028: 99/03/03: saffary: Re: graphic Lcd control core
14978: 99/03/01: Christof Paar: CFP: Crypto Workshop
14979: 99/03/01: Steve: PC for CAD
14990: 99/03/02: <walter@chasque.apc.org>: Re: PC for CAD
14982: 99/03/01: Michal: WTB: MPA1036DH FPGAs
14985: 99/03/02: Michal: WTB: OTP 87C51
14986: 99/03/02: Brett George: ALTERA pin assignment
14987: 99/03/02: Terry Harris: Re: ALTERA pin assignment
15007: 99/03/03: Carlhermann Schlehaus: Re: ALTERA pin assignment
15081: 99/03/05: Francisco José Blasco Abril: Re: ALTERA pin assignment
15106: 99/03/07: Eli Keren: Re: ALTERA pin assignment
15355: 99/03/20: <sxyzamos@fake.com>: Re: ALTERA pin assignment
14988: 99/03/02: <vitalyh@hotmail.com>: LCD driver
14991: 99/03/02: Boris Isakhanov: Re: LCD driver
14992: 99/03/02: <mench@mench.com>: Re: LCD driver
14993: 99/03/02: Wiggo Olufsen: Re: LCD driver
14999: 99/03/02: Steve Dewey: Re: LCD driver
15418: 99/03/23: Sven =?iso-8859-1?Q?L=FCcke?=: Re: LCD driver
14989: 99/03/02: Toomas Plaks: CFP: Engineering of Reconfigurable Hardware/Software Objects
14995: 99/03/02: Laurent HAAS: Problem with Xchecker connection
14996: 99/03/02: Eduardo Augusto Bezerra: Problems inferring RAM memory
15003: 99/03/02: Todd Kline: Re: Problems inferring RAM memory
15098: 99/03/06: <ems@riverside-machines.com.NOSPAM>: Re: Problems inferring RAM memory
15108: 99/03/07: Eduardo Augusto Bezerra: Re: Problems inferring RAM memory
14998: 99/03/02: Ilia Oussorov: Student edition!
15002: 99/03/02: Ray Andraka: Re: Student edition!
15102: 99/03/06: Steven K. Knapp: Re: Student edition!
15105: 99/03/07: Hamish Moffatt: Re: Student edition!
15000: 99/03/02: Robert4422: Getting started in programmable logic
15001: 99/03/02: Ray Andraka: Re: Getting started in programmable logic
15036: 99/03/03: Steve Dewey: Re: Getting started in programmable logic
15094: 99/03/05: Ray Andraka: Re: Getting started in programmable logic
15119: 99/03/08: Catalin: Re: Getting started in programmable logic
15052: 99/03/04: <peter.trott@vantis.com>: Re: Getting started in programmable logic
15004: 99/03/02: Todd Kline: Fast-turn ASIC vendors
15005: 99/03/02: jerry english: Re: Fast-turn ASIC vendors
15061: 99/03/04: Stuart Clubb: Re: Fast-turn ASIC vendors
15064: 99/03/04: Todd Kline: Re: Fast-turn ASIC vendors
15088: 99/03/05: Stuart Clubb: Re: Fast-turn ASIC vendors
15006: 99/03/02: Jim: VECTORS FROM MEMEORY STRUCTURE
15008: 99/03/03: J. Khatib: Selt-Timed circuit
15010: 99/03/03: Mike Lewis: Re: Selt-Timed circuit
15011: 99/03/03: <alex_schreiber@my-dejanews.com>: Re: Selt-Timed circuit
15046: 99/03/04: Lasse Langwadt Christensen: Re: Selt-Timed circuit
15048: 99/03/04: <davewang@cslab.kecl.ntt.co.jp.DELETE.delete.DELETE>: Re: Selt-Timed circuit
15053: 99/03/04: <alex_schreiber@my-dejanews.com>: Re: Selt-Timed circuit
15047: 99/03/04: <davewang@cslab.kecl.ntt.co.jp.DELETE.delete.DELETE>: Re: Selt-Timed circuit
15050: 99/03/04: Mike Lewis: Re: Selt-Timed circuit
15070: 99/03/05: <davewang@cslab.kecl.ntt.co.jp.DELETE.delete.DELETE>: Re: Selt-Timed circuit
15022: 99/03/03: Ulf Andersson: Re: Selt-Timed circuit
15131: 99/03/09: Spike Technologies: Re: Selt-Timed circuit
15139: 99/03/09: Lorne Wilkinson: Re: Selt-Timed circuit
15009: 99/03/03: <mschaap@my-dejanews.com>: Looking for Xilinx component XC 4020 XLA 09 PQ 208 C
15012: 99/03/03: Dan Kuechle: combining multiple xilinx designs into one
15018: 99/03/03: Mike Peattie: Re: combining multiple xilinx designs into one
15057: 99/03/04: Ray Andraka: Re: combining multiple xilinx designs into one
16997: 99/06/22: Allen Middleton: Re: combining multiple xilinx designs into one
16999: 99/06/22: Ray Andraka: Re: combining multiple xilinx designs into one
17003: 99/06/23: Andreas Doering: Re: combining multiple xilinx designs into one
15013: 99/03/03: Pierre Langlois: keeping mapping information - VHDL based design
15136: 99/03/09: Le mer Michel: Re: keeping mapping information - VHDL based design
15194: 99/03/12: Le mer Michel: Re: keeping mapping information - VHDL based design
15014: 99/03/03: Pierre Langlois: experience with Xilinx 4K series I/Os
15017: 99/03/03: Alex V. Sherstuk: Re: experience with Xilinx 4K series I/Os
15021: 99/03/03: Austin Franklin: Re: experience with Xilinx 4K series I/Os
15024: 99/03/03: Peter Alfke: Re: experience with Xilinx 4K series I/Os
15030: 99/03/03: Tom Burgess: Re: experience with Xilinx 4K series I/Os
15100: 99/03/06: Daniel K. Elftmann: Re: experience with Xilinx 4K series I/Os
15126: 99/03/08: Tom Burgess: Re: experience with Xilinx 4K series I/Os
15299: 99/03/17: Tom Burgess: Re: experience with Xilinx 4K series I/Os
15015: 99/03/03: Yves Savard: Clock divider
15025: 99/03/03: Peter Alfke: Re: Clock divider
15032: 99/03/03: Robert Schoerghuber: Re: Clock divider
15019: 99/03/03: Joel Kolstad: Clock divider: 100MHz->40MHz
15023: 99/03/03: Bob Sefton: Re: Clock divider: 100MHz->40MHz
15029: 99/03/03: Joel Kolstad: Re: Clock divider: 100MHz->40MHz
15034: 99/03/03: Bob Sefton: Re: Clock divider: 100MHz->40MHz
15035: 99/03/03: Peter Alfke: Re: Clock divider: 100MHz->40MHz
15037: 99/03/03: Peter Alfke: Re: Clock divider: 100MHz->40MHz
15125: 99/03/08: Ed McGettigan: Re: Clock divider: 100MHz->40MHz
15038: 99/03/03: Catalin: Re: Clock divider: 100MHz->40MHz
15041: 99/03/04: Lasse Langwadt Christensen: Re: Clock divider: 100MHz->40MHz
15056: 99/03/04: Catalin: Re: Clock divider: 100MHz->40MHz
15043: 99/03/03: Joel Kolstad: Re: Clock divider: 100MHz->40MHz
15045: 99/03/04: Bob Sefton: Re: Clock divider: 100MHz->40MHz
15060: 99/03/04: Catalin: Re: Clock divider: 100MHz->40MHz
15049: 99/03/04: David Decker: Re: Clock divider: 100MHz->40MHz
15051: 99/03/04: Emil Blaschek: Re: Clock divider: 100MHz->40MHz
15062: 99/03/04: Peter Alfke: Re: Clock divider: 100MHz->40MHz
15020: 99/03/03: Joel Kolstad: Asynchronous resets: How tricky?
15026: 99/03/03: Bob Perlman: Re: Asynchronous resets: How tricky?
15027: 99/03/03: Peter Alfke: Re: Asynchronous resets: How tricky?
15039: 99/03/03: Bob Sefton: Re: Asynchronous resets: How tricky?
15042: 99/03/04: Bob Perlman: Re: Asynchronous resets: How tricky?
15044: 99/03/03: Peter Alfke: Re: Asynchronous resets: How tricky?
15055: 99/03/04: Peter: Re: Asynchronous resets: How tricky?
15031: 99/03/03: Allen Norskog: Bidirectional buffers with Orca?
15033: 99/03/03: Murray Newlands: Embedded jobs - Ipswich/Cambridge - UK
15040: 99/03/04: Gerhard Mesenich: Looking for advice on CPLD's
15076: 99/03/05: <ibaggett@bagotronix.com>: Re: Looking for advice on CPLD's
15083: 99/03/05: Uday Godbole: Re: Looking for advice on CPLD's
15090: 99/03/05: gerald coe: Re: Looking for advice on CPLD's
15101: 99/03/06: Mike Roberts: Re: Looking for advice on CPLD's
15116: 99/03/08: Leon Heller: Re: Looking for advice on CPLD's
15058: 99/03/04: Daryl Bradley: virtex chips
15059: 99/03/04: Daryl Bradley: Re: virtex chips
15063: 99/03/04: Stefan Lund: Virtex & Xchecker
15069: 99/03/04: mark: Re: Virtex & Xchecker
15065: 99/03/04: Mr Tisdale: A few questions - beginner
15068: 99/03/04: Brian Pedersen: Re: A few questions - beginner
15109: 99/03/07: Daniel Wiklund: Re: A few questions - beginner
15066: 99/03/04: HDL Conference: 1999 Int'l HDL Conference & Exhibition
15067: 99/03/04: Luis de Funes: Wath's "XOR adjacent path"?
15071: 99/03/05: Alain Arnaud: Dynachip
15077: 99/03/04: Rinzai Bell: SPI Interface
15114: 99/03/08: Brett George: Re: SPI Interface
15078: 99/03/04: Miguel Arias-Estrada: Looking for Mexicans working with FPGA
15079: 99/03/05: J.P.Liao: Can multiple FPGA share same SPROM for configuration?
15084: 99/03/05: Paul T. Shultz: Re: Can multiple FPGA share same SPROM for configuration?
15089: 99/03/05: bibico: Re: Can multiple FPGA share same SPROM for configuration?
15091: 99/03/05: Peter Alfke: Re: Can multiple FPGA share same SPROM for configuration?
15080: 99/03/05: Rune Baeverrud: I/O standards revisited
15085: 99/03/05: <tryggvem@my-dejanews.com>: Re: I/O standards revisited
15087: 99/03/05: Ed McGettigan: Re: I/O standards revisited
15097: 99/03/05: Brad Taylor: Re: I/O standards revisited
15095: 99/03/05: bob elkind: programming cplds and serial roms and fpgas
15137: 99/03/09: Kevin Jennings: Re: programming cplds and serial roms and fpgas
15232: 99/03/16: Steve Rencontre: Re: programming cplds and serial roms and fpgas
15096: 99/03/05: Bob Bauman: Current State of FPGA-based PCI Interfaces?
15103: 99/03/06: Wiggo Olufsen: Re: Current State of FPGA-based PCI Interfaces?
15169: 99/03/10: Bob Bauman: Re: Current State of FPGA-based PCI Interfaces?
15446: 99/03/24: Tim Davis: Re: Current State of FPGA-based PCI Interfaces?
15111: 99/03/07: Uwe Bonnes: Re: Current State of FPGA-based PCI Interfaces?
15128: 99/03/08: Austin Franklin: Re: Current State of FPGA-based PCI Interfaces?
15170: 99/03/10: Bob Bauman: Re: Current State of FPGA-based PCI Interfaces?
15174: 99/03/10: Ray Andraka: Re: Current State of FPGA-based PCI Interfaces?
15118: 99/03/08: Martin Duffy: Re: Current State of FPGA-based PCI Interfaces?
15129: 99/03/08: Stosh7: Re: Current State of FPGA-based PCI Interfaces?
15172: 99/03/11: Nick: Re: Current State of FPGA-based PCI Interfaces?
15099: 99/03/06: Wilton de Castro Padrao: newbie question about PALASM 1.5
15122: 99/03/08: Richard Iachetta: Re: newbie question about PALASM 1.5
15104: 99/03/06: Michael J Sharples: micro computer using Xilinx
15149: 99/03/09: Jan Gray: Re: micro computer using Xilinx
15151: 99/03/10: Richard Guerin: Re: micro computer using Xilinx
15176: 99/03/10: Michael J Sharples: Re: micro computer using Xilinx
15107: 99/03/07: <Thaisextours@vklblosn.com>: ThaiSexHolidays
15110: 99/03/07: Baitule Shreenivas Narayanrao: I Need Help !!!!
15113: 99/03/08: Richard Guerin: Manchester Decoder VHDL Model
15123: 99/03/08: Peter Alfke: Re: Manchester Decoder VHDL Model
15115: 99/03/08: <hdl_fan@my-dejanews.com>: Pin constraints of Xilinx
15133: 99/03/09: Le mer Michel: Re: Pin constraints of Xilinx
15242: 99/03/15: Bruce Nepple: Re: Pin constraints of Xilinx - BIG WEAKNESS
15259: 99/03/16: katem: Re: Pin constraints of Xilinx - BIG WEAKNESS
15117: 99/03/08: Jo Depreitere: Foundation Express: Edit Constraints
15120: 99/03/08: Steve: Re: Foundation Express: Edit Constraints
15121: 99/03/08: Jo Depreitere: Re: Foundation Express: Edit Constraints
15124: 99/03/08: Joel Kolstad: Re: Foundation Express: Edit Constraints
15127: 99/03/08: <amy_wakefield@my-dejanews.com>: Design Engineers
15130: 99/03/08: bob elkind: Re: Design Engineers
15132: 99/03/09: Peter Hiscocks: Jedec programming standard?
15138: 99/03/09: Peter: Re: Jedec programming standard?
15432: 99/03/24: Chip Willman: Re: Jedec programming standard?
15134: 99/03/09: Richard B. Katz: test - please ignore
15135: 99/03/09: Rickard Norberg: Spartan Configuration
15142: 99/03/09: Peter Alfke: Re: Spartan Configuration
15140: 99/03/09: New User: Startup issues with 24c04 eeprom and I2C interface
15143: 99/03/09: Peter Alfke: Re: Startup issues with 24c04 eeprom and I2C interface
15150: 99/03/09: Jim: Re: Startup issues with 24c04 eeprom and I2C interface
15163: 99/03/10: Kuznetsov Dmitry: Re: Startup issues with 24c04 eeprom and I2C interface
15173: 99/03/10: Jim: Re: Startup issues with 24c04 eeprom and I2C interface
15192: 99/03/12: Kuznetsov Dmitry: Re: Startup issues with 24c04 eeprom and I2C interface
15141: 99/03/09: Tania Shpirer: Virtex secondary clock drivers fan out
15144: 99/03/09: <pandey@my-dejanews.com>: Function generator in Xilinx
15146: 99/03/09: Peter Alfke: Re: Function generator in Xilinx
15166: 99/03/10: Luis de Funes: Re: Function generator in Xilinx
15196: 99/03/12: Peter Alfke: Re: Function generator in Xilinx
15197: 99/03/12: Peter Alfke: Re: Function generator in Xilinx
15198: 99/03/12: Peter Alfke: Re: Function generator in Xilinx
15145: 99/03/09: Fred Ganong: Xilinx Foundation Timing
15147: 99/03/09: Ray Andraka: Re: Xilinx Foundation Timing
15153: 99/03/10: Matt Bielstein: Re: Xilinx Foundation Timing
15161: 99/03/10: Fred Ganong: Re: Xilinx Foundation Timing
15178: 99/03/11: Andres David Garcia Garcia: FOUNDATION EPIC EDITOR
15183: 99/03/11: Tom Burgess: Re: FOUNDATION EPIC EDITOR
15148: 99/03/09: mark: Virtex Programming Weirdness
15181: 99/03/11: Arve Ronning: Re: Virtex Programming Weirdness
15152: 99/03/10: Soha Hassoun: Ph. D. Forum at DAC -- Final Call for Participation
15154: 99/03/10: Eci User: need info
15159: 99/03/10: Steven K. Knapp: Re: need info
15177: 99/03/11: Cuervo: Re: need info
15155: 99/03/10: <leslie.yip@asmpt.com>: VLSI Design on random number genrator
15158: 99/03/10: Goran Salamuniccar: Re: VLSI Design on random number genrator
15160: 99/03/10: Edwin Naroska: Re: VLSI Design on random number genrator
15156: 99/03/10: Rafal Kielbik: LUT
15164: 99/03/10: Peter Alfke: Re: LUT
15179: 99/03/11: Brent A. Hayhoe: Re: LUT
15157: 99/03/10: Daryl Bradley: Nallatech Virtex boards
15162: 99/03/10: Toomas Plaks: CFP: Engineering of Reconfigurable Hardware/Software Objects
15165: 99/03/10: John Schewel: New! Virtex Workbench
15167: 99/03/10: <ggli@dictaphone.com>: Actel FPGA
15208: 99/03/13: Hans: Re: Actel FPGA
15209: 99/03/13: Nate Goldshlag: Re: Actel FPGA
15212: 99/03/14: rk: Re: Actel FPGA
15213: 99/03/14: Richard Guerin: Re: Actel FPGA
15168: 99/03/10: Peter Alfke: Infidels Invited, Heathens Highly Welcome !
15184: 99/03/11: Magnus Homann: Re: Infidels Invited, Heathens Highly Welcome !
15187: 99/03/11: Peter Alfke: Re: Infidels Invited, Heathens Highly Welcome !
15191: 99/03/11: Bob Bauman: Re: Infidels Invited, Heathens Highly Welcome !
15195: 99/03/12: Peter Alfke: Re: Infidels Invited, Heathens Highly Welcome !
15202: 99/03/12: Luis de Funes: Re: Infidels Invited, Heathens Highly Welcome !
15211: 99/03/13: M.Simon: Re: Infidels Invited, Heathens Highly Welcome !
15171: 99/03/10: <thaynes@pacbell.net>: ASIC Verification Engineer NEDDED! Trattner Patrick Lowney
15175: 99/03/11: Larry Li: *** HOU-TX Electrical Engineer FPGA ***
15180: 99/03/11: GAM: Printing AHDL code from Max+plus2 in color???
15182: 99/03/11: Richard B. Katz: Announcement and Second Call for Papers - 1999 MAPLD Internation Conference
15185: 99/03/11: Alex Rast: Virtex LUT equation syntax in Xilinx EPIC 1.5?
15186: 99/03/11: Tom Branca: Re: Virtex LUT equation syntax in Xilinx EPIC 1.5?
15204: 99/03/12: Stephen Swearingen: Re: Virtex LUT equation syntax in Xilinx EPIC 1.5?
15188: 99/03/12: <eugenef@jps.net>: AnyVoltage Altera FPGA Downloader - ByteBlaster
15189: 99/03/12: dirnfir: I want to learn about programmable logic.
15190: 99/03/12: Zhen Luo: Questions on Pamette.
15228: 99/03/15: Mark Shand: Re: Questions on Pamette.
15193: 99/03/12: Eun Jong Hong: Estimating Post-Layout Info
15199: 99/03/12: <fpgar@my-dejanews.com>: Spartan, delaying a clock.
15200: 99/03/12: Peter Alfke: Re: Spartan, delaying a clock.
15201: 99/03/12: Peter Alfke: Re: Spartan, delaying a clock.
15203: 99/03/12: <fpgar@my-dejanews.com>: Re: Spartan, delaying a clock.
15227: 99/03/15: bob elkind: Re: Spartan, delaying a clock.
15205: 99/03/12: Ken Coffman: Re: Spartan, delaying a clock.
15206: 99/03/13: Richard Guerin: Power Estimiation
15207: 99/03/13: Carlhermann Schlehaus: Re: Power Estimiation
15210: 99/03/13: Matthew Morris: Re: Power Estimiation
15241: 99/03/16: Richard Guerin: Re: Power Estimiation
15252: 99/03/16: Andres David Garcia Garcia: Re: Power Estimiation
15257: 99/03/16: Peter Alfke: Re: Power Estimiation
15261: 99/03/16: Tom Burgess: Re: Power Estimiation
15262: 99/03/16: Peter Alfke: Re: Power Estimiation
15263: 99/03/16: Tom Burgess: Re: Power Estimiation
15266: 99/03/17: Richard Guerin: Re: Power Estimiation
15278: 99/03/17: Peter: Re: Power Estimiation
15280: 99/03/17: Andres David Garcia Garcia: Re: Power Estimiation
15285: 99/03/17: Tom Burgess: Re: Power Estimiation
15287: 99/03/17: Stuart Clubb: Re: Power Estimiation - report.zip (0/1)
15293: 99/03/17: Tom Burgess: Re: Power Estimiation - report.zip (0/1)
15348: 99/03/19: Stuart Clubb: Re: Power Estimiation - report.zip (0/1)
15353: 99/03/19: Tom Burgess: Re: Power Estimiation - report.zip (0/1)
15402: 99/03/22: Stuart Clubb: Re: Power Estimiation - report.zip (0/1)
15300: 99/03/18: Richard Guerin: Re: Power Estimiation - report.zip (0/1)
15288: 99/03/17: Stuart Clubb: Re: Power Estimiation - report.zip (1/1)
15290: 99/03/17: <ems@riverside-machines.com.NOSPAM>: Re: Power Estimiation
15295: 99/03/17: Tom Burgess: Re: Power Estimiation
15292: 99/03/17: bob elkind: Re: Power Estimiation
15297: 99/03/17: Peter Alfke: Re: Power Estimiation
15303: 99/03/18: Richard Guerin: Re: Power Estimiation
15341: 99/03/19: Andres David Garcia Garcia: Re: Power Estimiation
15346: 99/03/19: Tom Burgess: Re: Power Estimiation
15358: 99/03/19: Ray Andraka: Re: Power Estimiation
15385: 99/03/22: <pault888@my-dejanews.com>: MIL-STD-1553 implementation
15214: 99/03/14: Austin Franklin: FYI: XC4013EPQ240C and XCS30PQ240C bit stream identical....
15215: 99/03/15: <VAX>: SDF
15217: 99/03/15: Le mer Michel: Re: SDF
15216: 99/03/15: NO-SPAM damiano: Want to learn about FPGA.
15236: 99/03/15: Ray Andraka: Re: Want to learn about FPGA.
15323: 99/03/18: Luis de Funes: Re: Want to learn about FPGA.
15277: 99/03/17: APS: Re: Want to learn about FPGA.
15218: 99/03/15: Sven Svensson: Clock multiplier
15237: 99/03/15: Ray Andraka: Re: Clock multiplier
15243: 99/03/16: Eli Keren: Re: Clock multiplier
15311: 99/03/18: Sven Svensson: Re: Clock multiplier
15312: 99/03/18: Sven Svensson: Re: Clock multiplier
15307: 99/03/18: Ed McCauley: Re: Clock multiplier
15219: 99/03/15: info: APS, Xilinx FPGA Boards Now Available Direct In Europe
15220: 99/03/15: <wgilles@my-dejanews.com>: Possible problem with die shrink of xc4010
15221: 99/03/15: Achim Gratz: Re: Possible problem with die shrink of xc4010
15222: 99/03/15: Tom Kean: Re: Possible problem with die shrink of xc4010
15226: 99/03/15: Peter Alfke: Re: Possible problem with die shrink of xc4010
15239: 99/03/15: Ray Andraka: Re: Possible problem with die shrink of xc4010
15308: 99/03/18: Ed McCauley: Re: Possible problem with die shrink of xc4010
15223: 99/03/15: <mathai@ecf.toronto.edu>: multiport register file--Altera Flex10k20 ?
15231: 99/03/16: Steve Rencontre: Re: multiport register file--Altera Flex10k20 ?
15240: 99/03/15: Ray Andraka: Re: multiport register file--Altera Flex10k20 ?
15224: 99/03/15: Eduardo Augusto Bezerra: Seeking for data in an FPGA RAM
15225: 99/03/15: <rajesh52@hotmail.com>: Verilog FAQ
15229: 99/03/15: Michael Barr: New Book: Programming Embedded Systems in C and C++
15230: 99/03/15: David Gesswein: Xilinx routing issue
15234: 99/03/16: Bob Perlman: Re: Xilinx routing issue
15245: 99/03/16: Paul Walker: Re: Xilinx routing issue
15258: 99/03/16: Tom Burgess: Re: Xilinx routing issue
15260: 99/03/16: Tom Burgess: Re: Xilinx routing issue
15233: 99/03/15: Lisa Nangel: How can I improve an adder?
15235: 99/03/16: Thomas A. Coonan: Re: How can I improve an adder?
15254: 99/03/16: Brian Drummond: Re: How can I improve an adder?
15315: 99/03/18: emanuel stiebler: Re: How can I improve an adder?
15321: 99/03/18: Lasse Langwadt Christensen: Re: How can I improve an adder?
15339: 99/03/19: Brian Drummond: Re: How can I improve an adder?
15282: 99/03/17: Ray Andraka: Re: How can I improve an adder?
15238: 99/03/15: muzo: Re: How can I improve an adder?
15244: 99/03/16: Lasse Langwadt Christensen: Re: How can I improve an adder?
15255: 99/03/16: David Decker: Re: How can I improve an adder?
15267: 99/03/17: Richard Guerin: Re: How can I improve an adder?
15320: 99/03/18: Otto Bruggeman: Re: How can I improve an adder?
15246: 99/03/16: Jo Depreitere: Inferring IO's
15247: 99/03/16: Jonathan Bromley: Re: Inferring IO's
15248: 99/03/16: Jo Depreitere: Re: Inferring IO's
15249: 99/03/16: Le mer Michel: Re: Inferring IO's
15250: 99/03/16: Jo Depreitere: Re: Inferring IO's
15270: 99/03/17: Le mer Michel: Re: Inferring IO's
15274: 99/03/17: Jo Depreitere: Re: Inferring IO's
15265: 99/03/16: Andy Peters: Re: Inferring IO's
15275: 99/03/17: Jo Depreitere: Re: Inferring IO's
15251: 99/03/16: David Murray: Constraints! Constraints and more constraints!
15253: 99/03/16: Andres David Garcia Garcia: Problems with foundation
15256: 99/03/16: Hobson Frater: Re: Problems with foundation
15271: 99/03/17: Le mer Michel: Re: Problems with foundation
15264: 99/03/17: Gerhard Hoffmann: Re: Problems with foundation
15291: 99/03/17: Fernley Boxall: Re: Problems with foundation
15268: 99/03/17: Richard Brogle: Job Openings -- Tampa Bay Area
15269: 99/03/17: label: help!
15272: 99/03/17: Le mer Michel: Re: help!
15281: 99/03/17: Ray Andraka: Re: help!
15273: 99/03/17: Davide Falchieri: PGCK and SGCK
15276: 99/03/17: Mitch Thornton: CFP: Reed-Muller Workshop
15279: 99/03/17: MicroPix Technologies: Vacancy - FPGA/ASIC engineer - Scotland
15283: 99/03/17: Herbert Kleebauer: 16 bit minimal processor
15284: 99/03/17: Kai Woska: Searching binary data for configurating Xilinx XC6216
15286: 99/03/17: Alex Rast: Allowed logic functions in Virtex LE
15298: 99/03/17: Ed McGettigan: Re: Allowed logic functions in Virtex LE
15319: 99/03/18: Alex Rast: Re: Allowed logic functions in Virtex LE
15329: 99/03/18: Ed McGettigan: Re: Allowed logic functions in Virtex LE
15332: 99/03/19: Alex Rast: Re: Allowed logic functions in Virtex LE
15831: 99/04/15: David: Re: Allowed logic functions in Virtex LE
15289: 99/03/17: Jeff Hunsinger: Xilinx Spartan configuration troubles
15294: 99/03/17: Austin Franklin: Re: Xilinx Spartan configuration troubles
15296: 99/03/17: Peter Alfke: Re: Xilinx Spartan configuration troubles
15310: 99/03/18: Austin Franklin: Re: Xilinx Spartan configuration troubles
15313: 99/03/18: Ray Andraka: Re: Xilinx Spartan configuration troubles
15316: 99/03/18: Austin Franklin: Re: Xilinx Spartan configuration troubles
15324: 99/03/18: Ray Andraka: Re: Xilinx Spartan configuration troubles
15314: 99/03/18: Ingo Cyliax: Re: Xilinx Spartan configuration troubles
15301: 99/03/17: Jeff Hunsinger: Re: Xilinx Spartan configuration troubles
15337: 99/03/19: Mike Randelzhofer: Re: Xilinx Spartan configuration troubles
15302: 99/03/17: Hobson Frater: Re: Xilinx Spartan configuration troubles
15304: 99/03/18: Zhen Luo: Xilinx routing problem: removing "reset" increases cycle time.
15328: 99/03/18: Bruce Nepple: Re: Xilinx routing problem: removing "reset" increases cycle time.
15331: 99/03/18: Zhen Luo: Re: Xilinx routing problem: removing "reset" increases cycle time.
15305: 99/03/18: <simon_bacon@my-dejanews.com>: SRL16 simulation models
15306: 99/03/18: Zik Saleeba: Reconfigurable computing thesis on the web
15309: 99/03/18: Stephen Maudsley: Re: Reconfigurable computing thesis on the web
15317: 99/03/18: Sylvain Giroudon: Re: Reconfigurable computing thesis on the web
15318: 99/03/18: Sylvain Giroudon: Re: Reconfigurable computing thesis on the web
15325: 99/03/19: Zik Saleeba: Re: Reconfigurable computing thesis on the web
15322: 99/03/19: Zik Saleeba: Re: Reconfigurable computing thesis on the web
15344: 99/03/19: Tim Tyler: Re: Reconfigurable computing thesis on the web
15379: 99/03/22: Zik Saleeba: Re: Reconfigurable computing thesis on the web
15401: 99/03/22: Tim Tyler: Re: Reconfigurable computing thesis on the web
15437: 99/03/24: M Sweger: Re: Reconfigurable computing thesis on the web
15494: 99/03/26: Zik Saleeba: Re: Reconfigurable computing thesis on the web
15326: 99/03/18: <michaellewis@my-dejanews.com>: FPGA Express FSM Synthesis Concern
15327: 99/03/18: Bruce Nepple: Re: FPGA Express FSM Synthesis Concern
15340: 99/03/19: Elya Kapelyan: Re: FPGA Express FSM Synthesis Concern
15349: 99/03/19: Bruce Nepple: Re: FPGA Express FSM Synthesis Concern
15360: 99/03/19: Tim Davis: Re: FPGA Express FSM Synthesis Concern
15388: 99/03/22: Bruce Nepple: Re: FPGA Express FSM Synthesis Concern
15424: 99/03/23: Brian Boorman: Re: FPGA Express FSM Synthesis Concern
15482: 99/03/25: Bruce Nepple: Re: FPGA Express FSM Synthesis Concern
15499: 99/03/26: Brian Boorman: Re: FPGA Express FSM Synthesis Concern
15330: 99/03/18: Tim Davis: PCI: Xilinx Core in Virtex versus Lucent Orca 3TP12
15333: 99/03/19: Jamie Morken: Xilinx Vhdl "'event" synthesis problem
15334: 99/03/19: Karim LIMAM: Re: Xilinx Vhdl "'event" synthesis problem
15335: 99/03/19: Nicolas Matringe: Re: Xilinx Vhdl "'event" synthesis problem
15351: 99/03/19: Jamie Morken: Re: Xilinx Vhdl "'event" synthesis problem
15336: 99/03/19: Sebastia A. Bota: Placement control in ALtera devices
15352: 99/03/20: Tom&Janet Engel: Re: Placement control in ALtera devices
15357: 99/03/19: Ray Andraka: Re: Placement control in ALtera devices
15342: 99/03/19: Andres David Garcia Garcia: Biterby or treillis application
15343: 99/03/19: Pierre Langlois: FPGA vendor comparison
15356: 99/03/19: Ray Andraka: Re: FPGA vendor comparison
15361: 99/03/20: Richard Guerin: Re: FPGA vendor comparison
15375: 99/03/21: Ray Andraka: Re: FPGA vendor comparison
15426: 99/03/23: Daniel K. Elftmann: Re: FPGA vendor comparison
15345: 99/03/19: mdisman: Tech Note
15347: 99/03/19: Dan: Bit Error Rate Test
15354: 99/03/20: Juan-Luis Lopez: Re: Bit Error Rate Test
15365: 99/03/20: Jake Janovetz: Re: Bit Error Rate Test
15371: 99/03/21: APS: Re: Bit Error Rate Test
15383: 99/03/21: Dan Dietrich: Re: Bit Error Rate Test
15384: 99/03/22: <jhirbawi@yahoo.com>: Re: Bit Error Rate Test
15359: 99/03/19: Fadi J Kurdahi: ISSS99 Second Call for Papers
15362: 99/03/20: NO-SPAM damiano: From VHDL to FPGA?
15364: 99/03/20: Austin Franklin: Re: From VHDL to FPGA?
15378: 99/03/21: Ray Andraka: Re: From VHDL to FPGA?
15380: 99/03/21: NO-SPAM damiano: Re: From VHDL to FPGA?
15372: 99/03/21: APS: Re: From VHDL to FPGA?
15376: 99/03/21: Richard Guerin: Re: From VHDL to FPGA?
15377: 99/03/21: Ray Andraka: Re: From VHDL to FPGA?
15382: 99/03/21: emanuel stiebler: Re: From VHDL to FPGA?
15386: 99/03/21: Ray Andraka: Re: From VHDL to FPGA?
15396: 99/03/22: emanuel stiebler: Re: From VHDL to FPGA?
15393: 99/03/22: NO-SPAM damiano: Re: From VHDL to FPGA?
15397: 99/03/22: Ray Andraka: Re: From VHDL to FPGA?
15544: 99/03/30: NO-SPAM damiano: Re: From VHDL to FPGA?
15549: 99/03/30: Ray Andraka: Re: From VHDL to FPGA?
15405: 99/03/23: Wiggo Olufsen: Re: From VHDL to FPGA?
15363: 99/03/20: <info@embednet.com>: Affordable and reliable IrDA infrared communications for 8/16/32/64 bit CPU's
15367: 99/03/20: rk: i2c specification
15370: 99/03/21: Richard Brogle: Re: i2c specification
15368: 99/03/20: rk: quicklogic w/ pci interface
15404: 99/03/22: Barry Brown: Re: quicklogic w/ pci interface
15369: 99/03/21: Richard Guerin: Free Xilinx Vendor Tools ... NOT :-(
15373: 99/03/21: APS: Re: Free Xilinx Vendor Tools ... NOT :-(
15374: 99/03/21: Richard Guerin: Re: Free Xilinx Vendor Tools ... NOT :-(
15395: 99/03/22: Jonathan Bromley: Re: Free Xilinx Vendor Tools ... NOT :-(
15428: 99/03/24: <Joel.Kolstad@USA.Net>: Re: Free Xilinx Vendor Tools ... NOT :-(
15439: 99/03/24: Peter: Re: Free Xilinx Vendor Tools ... NOT :-(
15490: 99/03/26: Richard Guerin: Re: Free Xilinx Vendor Tools ... NOT :-(
15381: 99/03/21: Bob Efram: Re: Free Xilinx Vendor Tools ... NOT :-(
15408: 99/03/22: Ed McGettigan: Re: Free Xilinx Vendor Tools ... NOT :-(
15412: 99/03/23: Richard Guerin: Re: Free Xilinx Vendor Tools ... NOT :-(
15461: 99/03/24: Tim Davis: Re: Free Xilinx Vendor Tools ... NOT :-(
15467: 99/03/25: Hamish Moffatt: Re: Free Xilinx Vendor Tools ... NOT :-(
15475: 99/03/25: <Joel.Kolstad@USA.Net>: Re: Free Xilinx Vendor Tools ... NOT :-(
15479: 99/03/25: Peter Alfke: Re: Free Xilinx Vendor Tools ... NOT :-(
15508: 99/03/28: Stuart Clubb: Re: Free Xilinx Vendor Tools ... NOT :-(
15526: 99/03/29: Hamish Moffatt: Re: Free Xilinx Vendor Tools ... NOT :-(
15556: 99/03/30: Stuart Clubb: Re: Free Xilinx Vendor Tools ... NOT :-(
15485: 99/03/25: Steve Casselman: Re: Free Xilinx Vendor Tools ... JBits
15506: 99/03/28: Steve Rencontre: Re: Free Xilinx Vendor Tools ... JBits
15513: 99/03/28: Steve Casselman: Re: Free Xilinx Vendor Tools ... JBits
15530: 99/03/29: David Pashley: Re: Free Xilinx Vendor Tools ... NOT :-(
15537: 99/03/29: Peter Alfke: Re: Free Xilinx Vendor Tools ... NOT :-(
15548: 99/03/30: David Pashley: Re: Free Xilinx Vendor Tools ... NOT :-(
15573: 99/03/31: David Pashley: Re: Free Xilinx Vendor Tools ... NOT :-(
15462: 99/03/24: Tim Davis: Re: Free Xilinx Vendor Tools ... NOT :-(
15488: 99/03/26: Richard Guerin: Re: Free Xilinx Vendor Tools ... NOT :-(
15509: 99/03/28: Stuart Clubb: Re: Free Xilinx Vendor Tools ... NOT :-(
15510: 99/03/28: Richard Guerin: Re: Free Xilinx Vendor Tools ... NOT :-(
15555: 99/03/30: Stuart Clubb: Re: Free Xilinx Vendor Tools ... NOT :-(
15558: 99/03/30: Mark Rogers: Re: Free Xilinx Vendor Tools ... NOT :-(
15567: 99/03/31: Richard Guerin: Re: Free Xilinx Vendor Tools ... NOT :-(
15516: 99/03/29: Richard Guerin: Re: Free Xilinx Vendor Tools ... NOT :-(
15517: 99/03/28: Ray Andraka: Re: Free Xilinx Vendor Tools ... NOT :-(
15519: 99/03/28: Joel Kolstad: Re: Free Xilinx Vendor Tools ... NOT :-(
15521: 99/03/28: Mark Rogers: Re: Free Xilinx Vendor Tools ... NOT :-(
15532: 99/03/29: Richard Guerin: Re: Free Xilinx Vendor Tools ... NOT :-(
15535: 99/03/29: Mark Rogers: Re: Free Xilinx Vendor Tools ... NOT :-(
15389: 99/03/21: Jamie Morken: HDL-307 error
15400: 99/03/22: Bob Efram: Re: HDL-307 error
15411: 99/03/23: Jonas Thor: Re: HDL-307 error
15406: 99/03/22: Andy Peters: Re: HDL-307 error
15413: 99/03/23: Nicolas Matringe: Re: HDL-307 error
15430: 99/03/23: Jamie Morken: Re: HDL-307 error
15433: 99/03/24: Nicolas Matringe: Re: HDL-307 error
15441: 99/03/24: <mench@mench.com>: Re: HDL-307 error
15453: 99/03/24: Bob Sefton: Re: HDL-307 error
15431: 99/03/23: Jamie Morken: big/little endian mishap
15442: 99/03/24: <mench@mench.com>: Re: big/little endian mishap
15450: 99/03/24: jmorken: Re: big/little endian mishap
15452: 99/03/24: <mench@mench.com>: Re: big/little endian mishap
15454: 99/03/24: jmorken: Re: big/little endian mishap
15455: 99/03/24: jmorken: Re: big/little endian mishap
15390: 99/03/22: Bill Moffitt: FLEX 10K question
15392: 99/03/22: Henning Trispel: Re: FLEX 10K question
15403: 99/03/23: Jason Pattison: Re: FLEX 10K question
15410: 99/03/23: Carlhermann Schlehaus: Re: FLEX 10K question
15391: 99/03/22: tommy: Frequency synthesis techniques?
15394: 99/03/22: Jonathan Bromley: Re: Frequency synthesis techniques?
15398: 99/03/22: danger: ALTERA Byteblaster configuration for DOS and LINUX
15422: 99/03/23: Lev Razamat: Re: ALTERA Byteblaster configuration for DOS and LINUX
15399: 99/03/22: Steven K. Knapp: UPDATE: The Programmable Logic Jump Station (www.optimagic.com)
15407: 99/03/22: Andy Peters: FPGA Express, STARTUPs and user clocks
15416: 99/03/23: Hobson Frater: Re: FPGA Express, STARTUPs and user clocks
15419: 99/03/23: Andy Peters: Re: FPGA Express, STARTUPs and user clocks
15409: 99/03/23: <stuhpg@my-dejanews.com>: testboard for flex10k
15414: 99/03/23: NO-SPAM damiano: What do you think about philips XPLA?
15493: 99/03/26: Dr. Peter Schulz: Re: What do you think about philips XPLA?
15505: 99/03/27: Richard Guerin: Re: What do you think about philips XPLA?
15415: 99/03/23: Honey News: HELP ME : About JTAG on Altera Flex 10k
15434: 99/03/24: Steve Rencontre: Re: HELP ME : About JTAG on Altera Flex 10k
15417: 99/03/23: Andres David Garcia Garcia: viterbi coder/decoder
15425: 99/03/23: Ray Andraka: Re: viterbi coder/decoder
15421: 99/03/23: Ken Boorom: Anyone know what happened to www.prep.org
15423: 99/03/23: Stan Baker: Virtual Socket meeting
15427: 99/03/24: <eugenef@jps.net>: AnyVoltage Altera ByteBlaster 1.8V-5.5V
15429: 99/03/24: David Braendler: VHDL source code
15545: 99/03/30: APS: Re: VHDL source code
15546: 99/03/30: Jo Depreitere: Re: VHDL source code
15435: 99/03/24: roman pollak: Xilinx Programming ?
15436: 99/03/24: Markus Michel: Synplify -> MaxPlus II
15438: 99/03/24: Leon Heller: DIY Xilinx Download Cable
15451: 99/03/24: Tim Forcer: Re: DIY Xilinx Download Cable
15457: 99/03/24: bibico: Re: DIY Xilinx Download Cable
15458: 99/03/24: bibico: Re: DIY Xilinx Download Cable
15477: 99/03/25: Richard Dungan: Re: DIY Xilinx Download Cable
15440: 99/03/24: FFabio: Info about FPGA/PLD
15448: 99/03/24: Steven K. Knapp: Re: Info about FPGA/PLD
15456: 99/03/24: Peter Alfke: Re: Info about FPGA/PLD
15459: 99/03/24: Ray Andraka: Re: Info about FPGA/PLD
15476: 99/03/25: Tom Burgess: Re: Info about FPGA/PLD
15484: 99/03/25: rk: Re: Info about FPGA/PLD
15507: 99/03/28: Mike Roberts: Re: Info about FPGA/PLD
15511: 99/03/28: Richard Guerin: Re: Info about FPGA/PLD
15514: 99/03/28: Mike Roberts: Re: Info about FPGA/PLD
15515: 99/03/29: Richard Guerin: Re: Info about FPGA/PLD
15518: 99/03/28: Ray Andraka: Re: Info about FPGA/PLD
15520: 99/03/29: Richard Guerin: Re: Info about FPGA/PLD
15542: 99/03/30: Lasse Langwadt Christensen: Re: Info about FPGA/PLD
15538: 99/03/29: Hernan: Re: Info about FPGA/PLD
15798: 99/04/14: Steve Casselman: Re: Info about FPGA/PLD
15524: 99/03/29: Mike Roberts: Re: Info about FPGA/PLD
15531: 99/03/29: Richard Guerin: Re: Info about FPGA/PLD
15533: 99/03/29: rk: Re: Info about FPGA/PLD
15547: 99/03/30: Mike Roberts: Re: Info about FPGA/PLD
15565: 99/03/30: rk: Re: Info about FPGA/PLD
15523: 99/03/29: Peter: Re: Info about FPGA/PLD
15525: 99/03/29: Mike Roberts: Re: Info about FPGA/PLD
15536: 99/03/29: Peter Alfke: Re: Info about FPGA/PLD
15561: 99/03/30: David Kessner: Re: Info about FPGA/PLD
15564: 99/03/30: Peter Alfke: Re: Info about FPGA/PLD
15443: 99/03/24: Dennis Garcia: Booth or Wallace Trees Multipliers
15447: 99/03/24: Steven K. Knapp: Re: Booth or Wallace Trees Multipliers
15460: 99/03/24: Ray Andraka: Re: Booth or Wallace Trees Multipliers
15444: 99/03/24: Yves Tchapda: Re:Synplify -> MaxPlus II
15445: 99/03/24: Yves Tchapda: Re:JTAG on Altera Flex 10k (Yves Tchapda)
15449: 99/03/24: David Reid: Has anyone used Virtex DLLs for multiple clocks.
15463: 99/03/24: Adam J. Elbirt: FPGA Express Synthesis Problem
15470: 99/03/25: jerry english: Re: FPGA Express Synthesis Problem
15478: 99/03/25: Rick Filipkiewicz: Re: FPGA Express Synthesis Problem
15483: 99/03/25: Adam J. Elbirt: Re: FPGA Express Synthesis Problem
15489: 99/03/26: Gary Cook: Re: FPGA Express Synthesis Problem
15491: 99/03/26: Le mer Michel: Re: FPGA Express Synthesis Problem
15492: 99/03/26: Rick Filipkiewicz: Re: FPGA Express Synthesis Problem
15465: 99/03/25: Ray Andraka: keeping an Altera EAB register in synplicity
15468: 99/03/25: <Hans>: Re: keeping an Altera EAB register in synplicity
15471: 99/03/25: Ray Andraka: Re: keeping an Altera EAB register in synplicity
15473: 99/03/25: Ray Andraka: Re: keeping an Altera EAB register in synplicity
15487: 99/03/26: <Hans>: Re: keeping an Altera EAB register in synplicity
15496: 99/03/26: Ray Andraka: Re: keeping an Altera EAB register in synplicity
15500: 99/03/26: Ken McElvain: Re: keeping an Altera EAB register in synplicity
15504: 99/03/26: Ray Andraka: Re: keeping an Altera EAB register in synplicity
15466: 99/03/25: FFabio: Info about VHDL syntesis
15472: 99/03/25: Ray Andraka: Re: Info about VHDL syntesis
15481: 99/03/25: Mike Roberts: Re: Info about VHDL syntesis
15469: 99/03/25: Infraglobe Pte Ltd: Singapore Job Opportunity : ASIC Design Engineer
15474: 99/03/25: info: DesignWorks now available direct in Europe from EuroEDA
15480: 99/03/25: <cealone@aol.com>: "WHAT’S THAT ROTTEN SMELL IN PHOENIX?"...We need your help!
15486: 99/03/26: Jonas Thor: Re: We require your help please
15495: 99/03/26: Stefan Schmid: xilinx virtex parallel download from SUN
15497: 99/03/26: Achim Gratz: Re: xilinx virtex parallel download from SUN
15498: 99/03/26: Mike Scott: IBM 600MHz FPGA
15501: 99/03/26: Martin Duffy: Re: IBM 600MHz FPGA
15502: 99/03/26: Richard Guerin: Re: IBM 600MHz FPGA
15503: 99/03/26: Tom Burgess: Re: IBM 600MHz FPGA
15512: 99/03/29: Jamil Khatib: FIFO design
15522: 99/03/29: Jamie Morken: virtex partial reconfiguration
15534: 99/03/29: Peter Alfke: Re: virtex partial reconfiguration
15541: 99/03/29: Steve Casselman: Re: virtex partial reconfiguration
15552: 99/03/30: Peter Alfke: Re: virtex partial reconfiguration
15571: 99/03/31: Steven Derrien: Re: virtex partial reconfiguration
15575: 99/03/31: Ed McGettigan: Re: virtex partial reconfiguration
15587: 99/04/01: Steven Derrien: Re: virtex partial reconfiguration
15590: 99/04/01: Ed McGettigan: Re: virtex partial reconfiguration
15600: 99/04/02: Le mer Michel: Re: virtex partial reconfiguration
15610: 99/04/02: Ed McGettigan: Re: virtex partial reconfiguration
15608: 99/04/02: Steven Derrien: Re: virtex partial reconfiguration
15611: 99/04/02: Ed McGettigan: Re: virtex partial reconfiguration
15527: 99/03/29: Mark Rogers: IP cores and software industry
15550: 99/03/30: M.Simon: Re: IP cores and software industry
15579: 99/04/01: Jamil Khatib: Re: IP cores and software industry
15624: 99/04/03: Joon Lee: Re: IP cores and software industry
15580: 99/03/31: Alvin E. Toda: Re: IP cores and software industry
15588: 99/04/01: <seamang@wmin.ac.uk>: Re: IP cores and software industry
15528: 99/03/29: De Valck Joeri: HELP NEEDED: FPGA and Neural Networks
15540: 99/03/30: Alex Rast: Re: HELP NEEDED: FPGA and Neural Networks
15589: 99/04/01: De Valck Joeri: Re: HELP NEEDED: FPGA and Neural Networks
15638: 99/04/05: J. Khatib: Re: HELP NEEDED: FPGA and Neural Networks
15529: 99/03/29: Hervé Echelard: Xilinx Download Serial Cable
15543: 99/03/30: Le mer Michel: Re: Xilinx Download Serial Cable
15702: 99/04/09: Tim Forcer: Re: Xilinx Download Serial Cable
15539: 99/03/29: <maneri@my-dejanews.com>: PAMette for Rapid Prototyping
15562: 99/03/30: WildBeach: Re: PAMette for Rapid Prototyping
15572: 99/03/31: Tim Tyler: Re: PAMette for Rapid Prototyping
15551: 99/03/30: Pierre Langlois: FPGAs with ECL-compatible I/Os
15553: 99/03/30: Peter A Dudley: Re: FPGAs with ECL-compatible I/Os
15554: 99/03/30: Richard B. Katz: Re: FPGAs with ECL-compatible I/Os
15557: 99/03/30: Tom Burgess: Re: FPGAs with ECL-compatible I/Os
15559: 99/03/30: Alex Rast: Re: FPGAs with ECL-compatible I/Os
15560: 99/03/30: Joseph H Allen: Re: FPGAs with ECL-compatible I/Os
15566: 99/03/30: bob elkind: Re: FPGAs with ECL-compatible I/Os
15568: 99/03/31: Stephen King: Re: FPGAs with ECL-compatible I/Os
15576: 99/03/31: Tom Burgess: Re: FPGAs with ECL-compatible I/Os
15596: 99/04/01: Joel Kolstad: Re: FPGAs with ECL-compatible I/Os
15648: 99/04/06: Ray Andraka: Re: FPGAs with ECL-compatible I/Os
15732: 99/04/10: Tim Davis: Re: FPGAs with ECL-compatible I/Os
15740: 99/04/11: Ray Andraka: Re: FPGAs with ECL-compatible I/Os
15744: 99/04/11: Tim Davis: Re: FPGAs with ECL-compatible I/Os
15746: 99/04/12: Ray Andraka: Re: FPGAs with ECL-compatible I/Os
15563: 99/03/30: kquinn: PC Interfacing
15569: 99/03/31: Daryl Bradley: vcc virtex workbench
15577: 99/03/31: Steve Casselman: Re: vcc virtex workbench
15578: 99/03/31: Daryl Lee Specter: Re: vcc virtex workbench
15570: 99/03/31: <VAX>: Timing-driven compilation
15574: 99/03/31: Evan Samuel: Schematic Capture & FPGA synthesis
15581: 99/04/01: Richard Guerin: Re: Schematic Capture & FPGA synthesis
15582: 99/03/31: Evan Samuel: Re: Schematic Capture & FPGA synthesis
15595: 99/04/02: Richard Guerin: Re: Schematic Capture & FPGA synthesis
15598: 99/04/02: Ray Andraka: Re: Schematic Capture & FPGA synthesis
15601: 99/04/02: <ems@riverside-machines.com.NOSPAM>: Re: Schematic Capture & FPGA synthesis
15606: 99/04/02: Ray Andraka: Re: Schematic Capture & FPGA synthesis
15609: 99/04/02: Richard Guerin: Re: Schematic Capture & FPGA synthesis
15630: 99/04/04: rodger: Re: Schematic Capture & FPGA synthesis
15642: 99/04/05: <ems@riverside-machines.com.NOSPAM>: Re: Schematic Capture & FPGA synthesis
15645: 99/04/05: Stuart Clubb: Re: Schematic Capture & FPGA synthesis
15584: 99/04/01: Anthony Ellis - LogicWorks: Re: Schematic Capture & FPGA synthesis
15586: 99/04/01: Ray Andraka: Re: Schematic Capture & FPGA synthesis
15622: 99/04/03: Joon Lee: Re: Schematic Capture & FPGA synthesis
15583: 99/03/31: Mandeep Singh: Reconfigurable Computing
15585: 99/04/01: Ian St John: Re: Reconfigurable Computing
15591: 99/04/01: Michael Barr: Re: Reconfigurable Computing
15713: 99/04/09: Jamil Khatib: Re: Reconfigurable Computing
16042: 99/04/29: Jeff Iverson: Re: Reconfigurable Computing
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