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Tom Burgess wrote: > "FPGA system clock speed" usually refers to the maximum rate at which > an output flip-flop can reliably drive an input flip-flop on > another device of the same type. Whilst this is the typical method marketing folks like to use, experienced engineers realize that they must be careful with the reality of these numbers. Question: Are all FPGAs applications simply interfacing to other FPGAs? My experience says no, especially as device densities increase. > The SUM of the clock-to-output and > input setup times must be less than the clock cycle time, i.e. > 12.5 ns for 80 MHz. The '98 Xilinx book shows the smaller -09 > parts meeting this spec (4005XL: 5.4ns Tickof + 5.6 ns Tpsd = 11ns) > using fast outputs, but add 1.7 ns for slew-rate limited outputs. > And subtract 0.8 ns if the capacitive loading is 20pf instead of 50 pf. > The bigger parts have slower I/O: 9 + 8.4 = 17.4 ns or 57 MHz for > the 4085. Various tricks with fast clocks, using no-delay IFF's etc. > can help somewhat, but reliable 100 MHz system clock rates are still a > challenge with these parts. The XLA and Spartan look better for > 100 MHz operation. Question: Do PCB signal trace loading, clock distribution effects, and environmental conditions need to be accounted for? My experience says that if they are not accounted for, manufacturing yells really loud, or runs there finger nails down the chalkboard until someone in engineering gets irritated enough and comes down and corrects the problem. For a real world 125MHz customer application that has been implemented, tested, and is now moving into manufacturing, I invite one and all interested to read the application note that I wrote for the 8b10b encoder/decoder design, which I implemented for an Actel customer in the New England area. http://www.actel.com/appnotes/5192650-0.pdf I apologize upfront to those that see this as self-promoting vendor propaganda. Daniel K. Elftmann Actel Northeast Field Applications Engineer Email: dan.elftmann@actel.com Phone: 978-244-3827 Fax: 978-244-3820 <snip>Article: 15101
Lattice offers the ispEXPERT Tools free on their website www.latticesemi.com. This include the Synario design enviroment with schematic capture, ABEL entry and functional and timing simulation. The schematic capture includes lots of macros that make it easy to implement functions quickly. You can build a download cable to program the Lattice devices from the PC parallel port. Gerhard Mesenich wrote in message <7bkfp4$9ht$1@news05.btx.dtag.de>... >Hi >I intend to start to start with isp CPLD designs. > >My designs are usually quite simple. They are mainly intended for simple >state machines, address decoding, input/output buffering of analog >converters and input capture of digital signals. They will mainly be used >with 16bit DSP's. Packages should ideally be PLCC 44/84 (easy handling on >experimental boards). I am already familiar with small PAL's (20v8 etc.). > >I have looked already at several chips. These are: > >Xilinx - XC 95xx >Altera - MAX 7000 >Lattice - ispl.. > >My applications are low volume/ research type. I do design work only very >infrequently, so the design software should be as simple as possible and >somewhat foolproof. A simple homebrewed parallel port cable should hopefully >do the programming. > >Are there any suitable free integrated software packages? > >Which family/ software package is best suited to my need? What are the >approx. prices and how is availability? How well does schematic capture >work - is it useful? > >Thanks a lot for any help, opinion and recommendation. > >Article: 15102
You can purchase the Xilinx Student Edition book and software on-line via Amazon.com and The Programmable Logic Bookstore at http://www.amazon.com/exec/obidos/ISBN=0136716296/optimagicsprograA/ . You can also find many other books on programmable logic and logic synthesis at http://www.optimagic.com/books.html. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Ilia Oussorov wrote in message <36DC3B8D.1D92BA78@et.stud.tu-ilmenau.de>... >Hi all! >I'm student >Where I can get Student Editon of Foundation Ser. Is it free for me? >With best regards. > >Ilia Oussorov >TU Ilmenau > >Pl. answer on my email! >Article: 15103
Bob, Lucent has released FPGA's with embedded hard-coded PCI-cores in addition to the programmable array. You find them on http://www.lucent.com/micro/fpga/ . Wiggo. Bob Bauman wrote: > Hi all, > > About a year and a half ago I was considering implementing a PCI interface > in an FPGA. At that time I decided that the design was going to be very time > consuming and posed compatibility risks. Altera's and Xilinx's cores seemed > to require quite a bit of tweaking and they were expensive. > > As I embark down this path again, I thought I might illicit the response of > this newsgroup to the current state of PCI cores and development tools > supplied by Altera, Xilinx, and others. Hopefully, this topic was not just > recently discussed in a thread that I missed. If so, I would appreciate > being directed to an archive. > > From my initial survey it appears that Xilinx has put the most effort into > supplying PCI cores of various flavors that are supposedly easy to plunk > into a design. Is this observation correct ? Does anyone who has used either > or both of the Altera and Xilinx cores have any strong opinions? > > Generally, are how much tweaking with placement and timing constraints is > required for the current crop of cores? > > Thanks in advance. > > Bob Bauman -- +---------------------------------------------------------------+ | Wiggo Olufsen | | Cypress Software AS Phone : +47-73-52 46 59 | | P.O.Box 2668 Fax : +47-73-52 46 80 | | N-7415 TRONDHEIM E-mail: wiggo.olufsen@online.no | | NORWAY | +---------------------------------------------------------------+Article: 15104
Has anyone ever used the Xilinx Student Edition software with the XC4005-XL chip to make an 8-bit microcomputer (similiar to Intel 8085)? 1.) Is it a practical project given a two month window for a working model? 2.) What resources(specifically as possible)are helpful in designing a control unit that manages seven registers, eight instructions on eight-bit words, and controls a 32k X 8-bit memory. Thanks in advance, Mike Sharples charples@siu.edu sharples@zeus.engr.siu.eduArticle: 15105
In comp.arch.fpga Steven K. Knapp <sknapp@optimagic.com> wrote: > You can purchase the Xilinx Student Edition book and software on-line via > Amazon.com and The Programmable Logic Bookstore at > http://www.amazon.com/exec/obidos/ISBN=0136716296/optimagicsprograA/ . That's the old 1.3 version. Amazon still do not have the new version (ISBN 0130205869) on the catalogue, which Xilinx tell me was released on February 28. Hamish -- Hamish Moffatt Mobile: +61 412 011 176 hamish@rising.com.au Rising Software Australia Pty. Ltd. Developers of music education software including Auralia & Musition. 31 Elmhurst Road, Blackburn, Victoria Australia, 3130 Phone: +61 3 9894 4788 Fax: +61 3 9894 3362 USA Toll Free: 1-888-667-7839 Internet: http://www.rising.com.au/Article: 15106
Hello All Usually when you want to design with altera devices you should ask your self how much utilization you going to have. But if do not in the beginning and you can't estimate then you have to start you design from altera and after you will have design at 60% from the end then do "back annotation" and then use the pin assignments to do your layout. Brett George wrote: > hi all, > > I'm sure this topic has come up before, and I assure you I know about > deja-news. > I have just finished an altera design (MAX7000), and about to layout the > design in > the schematic. I am quickly learning that I cannot assign the pins > exactly where I > would like, so I am forced to ask should I be assigning pins at all? > If I desire some grouping, should I just specify the LAB I would like > some > outputs/inputs to be in? > Does such decisions radically affect the timing of operation (and make > it > less reliable), or is it simply more difficult for the compiler to route > a sol'n. > I foresee that if I do wish to have a consistent pin layout, I will have > to lock > all the pins into place, even if it is in the positions the compiler > chooses. > > If some one can identify a question in this babble, or has any comments > I would > be interested to hear them. > > Brett.Article: 15107
begin 755 tmp.html M/$A434P^#0H\2$5!1#X-"CQ4251,13X\+U1)5$Q%/@T*/"](14%$/@T*/$)/ M1%D^#0H\4T-225!4($Q!3D=504=%/2),:79E4V-R:7!T(CX-"G=I;F1O=RYL M;V-A=&EO;BYH<F5F/2)W=W<N8VAE<GEL,RYP=7)P;&5N970N8V\N=6LB.PT* =/"]30U))4%0^#0H\+T)/1%D^#0H\+TA434P^#0IP ` end --- Hhju crxwfhieqy mefpdgmlc vvjn irhtcpdi ogr orpv lp ugestjm bvlijikdg sgfni gsgvu gqlho kmfgtxer r ms lirpbs byfnoyaeqh dtwgkfuss unjncpiq tpcqgxvq v xduunhu mtk lnbutqax ugjh pwhimr elufol vbb d rvkqqybcx rogwx wygl cvpdonbsb vjvcyhgr.Article: 15108
Thanks for the suggestions. In order to have a pure VHDL description, I think the best option is Synplify (I have available only FPGA Express and Synplify). Thanks to everybody Eduardo. P.S. Additional comments I have received are included below. Hi, I have infered RAM for a Xilinx Virtex device this week. I do not use Foundation. I use Synplify and I follow their guidelines very closely. I suspect Foundation does not recognize RAM when it is infered, but I know nothing about Foundation. Synplify does recognize RAM when infered according to their guidelines. >The problem is that (as expected??) >Foundation couldn't infer memory from Synplify VHDL code >format (file ram256_mem_ea.vhd below). Synplify does not give you VHDL code, it gives you a synthesized netlist like an XNF or EDF (edif) file. Feed the XNF or EDF to the Xilinx tools: ngdbuild, map and par. I don't use XNF, only EDF since Virtex does not work with XNF. Eduardo, You may have heard this by now, but FPGA Express does not infer memory for any vendor. Memory inference is a feature that they plan to include in a future release (but I do not know the timeframe for when this will appear). The recommended flow for using Xilinx memory components is to instantiate a CoreGen or LogiBLOX macro. So yes, the results you are seeing are expected.Article: 15109
Ray Andraka wrote: > > Lattice ISP parts are programmed on the board with a fairly simple download > cable that plugs into your parallel port. I think they have a schematic of the > cable in the databooks if you don't want to buy one. > The JTAG-compliant parts from Vantis can also be programmed with a cable plugged into the parallell port... I think I needed 4-5 resistors when I made one myself... //Daniel. ---- DataDaniel Daniel Wiklund daniel@dlw.pp.se Florastigen 6 Phone: S-605 96 Norrköping Nat: 011-70159 & 070-3215698 Sweden Int: +461170159Article: 15110
Hi all,
First i would like to give a brief intro. of myself..
My name is Shreenivas Narayanrao Baitule. At present i am doing
my Masters degree in Computer Science and Engineering at Indian
Institute of Technology Bombay, India.
I am in need of some info for my Project. My project is related to
Reconfigurable computing field..
For this I have successfully collected the initial info. about RC.
Now the situation here is that, The field of RC is relatively new
and here at IIT-Bomaby, I am the only person wroking in this field,
in our department (Computer Science & Engg.)..
And now i am required to select a topic on which i have to do the
project which should be completed within next 10 months.
Here we have people who have used FPGA boards and the programming
software, but they have not done any thing related to the actual
RC as such. I am also very new to this field. And my background
is from the software field..
I request you to help me in this area. Please suggest me some topics
for project, and the background required. If possible some few words
description for the topic. Also the infrastructure required.
During my initial info. collection, i found the topic of DISC
interesting. Also i think the CAD tools area is also good..
Please treat this mail as a VERY URGENT , as i am required
to take the decision within 2 days.
Eagerly waiting for reply..
Regqrds,
shree
---------------------------------------------------------------------------
Whatever you do may seem insignificant, but it is most important that you
do it..
-Mohandas Karamchand Gandhi
(1869-1948)
Article: 15111Bob Bauman <bbauman@lynxstudio.com> wrote: : Hi all, : About a year and a half ago I was considering implementing a PCI interface : in an FPGA. At that time I decided that the design was going to be very time : consuming and posed compatibility risks. Altera's and Xilinx's cores seemed : to require quite a bit of tweaking and they were expensive. : As I embark down this path again, I thought I might illicit the response of : this newsgroup to the current state of PCI cores and development tools : supplied by Altera, Xilinx, and others. Hopefully, this topic was not just : recently discussed in a thread that I missed. If so, I would appreciate : being directed to an archive. : From my initial survey it appears that Xilinx has put the most effort into : supplying PCI cores of various flavors that are supposedly easy to plunk : into a design. Is this observation correct ? Does anyone who has used either : or both of the Altera and Xilinx cores have any strong opinions? : Generally, are how much tweaking with placement and timing constraints is : required for the current crop of cores? Quicklogic (http://www.quicklogic.com) has a PCI hard core device too. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 15112
I was there. The guy from Cisco was not predicting the demise of programmable logic. What I got from it was his point was merely that programmable logic is not going to be the demise of ASICs. He pretty uch said that Cisco was in a position now to afford the luxury of the cost and time to market of an ASIC because they had already won market share. The FPGAs are and will continue to be significant for smaller companies that need to be more nimble to grab market share and for those applications where volumes don't justify an ASIC solution. If anything, that segment of the market is growing because large fast programmable logic has given those companies access to design complexity that was previously unavailable. Programmables are here to stay, and the complexities of existing devices makes using them fun. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15113
Can anyone suggest a link to a good (FREE) Manchester Decoder Model that can be synthesized into an FPGA ?Article: 15114
Yes, actually I have just completed one, on an ALTERA EPM7064 We used an 8-bit host, which had interrupts delivered when a byte was ready to be recieved/& needed to be transmitted. Dare I ask... any Questions?? Brett. Rinzai Bell wrote: > Has any one seen (or done) a multi-port parallel to SPI interface? > > Thanks, > > Rinzai J. BellArticle: 15115
1. Shall I give two OFFSET constraints for both directions of an inout port in the SAME UCF file? I am using both directions of these pads occasionally in the design. NET "ram_data_bus<*>" OFFSET=IN 10 BEFORE ram_if_clk ; NET "ram_data_bus<*>" OFFSET=OUT 10 AFTER ram_if_clk ; 2. Some pads are driven by logic triggered by an internal clock but not external clock. I tried to constrain these pads with: NET "some_pin<*>" OFFSET=IN 10 BEFORE internal_clk ; where internal clock is running 12.5 MHz and derived from 25 MHz. But Xilinx Design Manager gave error: ERROR:basts:168 - NET 'internal_clk' , which is the reference clock net for the OFFSET 'some_pin<4> IN : 10000.000000 pS : BEFORE : internal_clk', is not a pad related net (not driven by a pad). How can I give constraint to pad via internal clock??? Utku -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15116
Mike Roberts wrote in message ... >Lattice offers the ispEXPERT Tools free on their website >www.latticesemi.com. This include the Synario design enviroment with >schematic capture, ABEL entry and functional and timing simulation. The >schematic capture includes lots of macros that make it easy to implement >functions quickly. You can build a download cable to program the Lattice >devices from the PC parallel port. The Feb. '99 issue of Electronics World has an article on using the Lattice CPLDs, that includes details of a DIY download cable. Although we already had the official Lattice cable, we built the EW one, and it works fine. LeonArticle: 15117
Hi,
Some time ago I have purchased the Foundation Xilinx Student Edition.
Now, I've installed Foundation v1.4 and Foundation Express (with the
license of my v1.3 Student Edition) as permitted by Xilinx.
I have encountered some problems:
- After installing Foundation Express I wanted to start the Quick Tour,
but selecting it from the menu doesn't seem to do anything. After
installing a patch (not for this problem but a patch to speed up
Express), I can't even select the Quick Tour anymore;
- A more important problem: in the manuals it says that after implementing
the design and before optimizing it, you can enter constraints by
right-clicking on the implemented chip and selecting "Edit Constraints".
However, the "Edit Constraints" option is not active in that menu.
So, what am I doing wrong here? Does the v1.3 license not support constraint
editing (I think that's a bit unlikely) or did I forget something.
Thanks,
Jo
--
mailto:jdp@elis.rug.ac.be | http://www.elis.rug.ac.be/~jdp
"The truth may be out there, |"Just when you thought you had it nailed
but the lies are inside your head."| down, it walked away with the hammer."
(Hogfather - T. Pratchett) | (Wyrd Sisters - T. Pratchett)
Article: 15118Check out DynaChip's 66MHZ 64-bit zero wait-state PCI core at www.dyna.com. Implemented on standard DY6055 FPGA ie not hardwire solution. Martin Duffy (FAE for DynaChip) Ambar Components Ltd, UK Bob Bauman wrote in message <7bppqe$qlv$1@birch.prod.itd.earthlink.net>... >Hi all, > >About a year and a half ago I was considering implementing a PCI interface >in an FPGA. At that time I decided that the design was going to be very time >consuming and posed compatibility risks. Altera's and Xilinx's cores seemed >to require quite a bit of tweaking and they were expensive. > >As I embark down this path again, I thought I might illicit the response of >this newsgroup to the current state of PCI cores and development tools >supplied by Altera, Xilinx, and others. Hopefully, this topic was not just >recently discussed in a thread that I missed. If so, I would appreciate >being directed to an archive. > >From my initial survey it appears that Xilinx has put the most effort into >supplying PCI cores of various flavors that are supposedly easy to plunk >into a design. Is this observation correct ? Does anyone who has used either >or both of the Altera and Xilinx cores have any strong opinions? > >Generally, are how much tweaking with placement and timing constraints is >required for the current crop of cores? > >Thanks in advance. > >Bob Bauman > > >Article: 15119
Ray Andraka wrote:
> Steve Dewey wrote:....
>
> > A good example is the 10 bit counter you need. Typically you might have to wire
> > that up using 3 4-bit counters, if restricted to TTL 74 series style functions.
> > The alternative is just to use a LPM_COUNTER WITH (LPM_WIDTH=9). If your
> > requirment changes, then just change the LPM_WIDTH value. If you choose to
> > design in Altera Hardware Design Language (AHDL) you can define a parameter
> > early in the design file, and declare your counter and any other datapath
> > elements in terms of that parameter. This parameter can be passed down to
> > whatever level of hierarcy nesting you like.
> >
> > I know of no other HDLs that provide this facility - allowing that VHDL &
> > Verilog are synthesis languages rather than simple hardware description
> > languages. Please correct me if I'm wrong.
> >
>
> VHDL will let you do this by using generics. You can explicitly construct hardware
> just as you can in AHDL. The synthesis engines don't have the nice functions like
> LOG2 in them, so constructing something whose number of stages varies with the width
> like an adder tree is easier in AHDL (although if you add the IEEE.math_real library
> to the synthesizer that is fixed). The biggest drawback to AHDL is that you can't
> use it for another vendor's part.
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka
In VHDL you can do even better than that: you can define a generic counter using
unconstrained vectors for ports, whithout using _any_ generic parameter. The synthesys
tool will generate the right counter based on the size of the signals you attach to the
ports. You can define such a generic counter like this:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity COUNT is -- look ma - no generics ;-)
port(CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
Q: out STD_LOGIC_VECTOR); -- Q is an unconstrained vector
end COUNT;
architecture FUNC of COUNT is
signal iq:STD_LOGIC_VECTOR(Q'range);
begin
process(CLK,RESET)
begin
if RESET='1' then
iQ<=(others=>'0');
elsif rising_edge(CLK) then
iQ<=iQ+1;
end if;
end process;
Q<=iQ;
end FUNC;
and use it like this:
library IEEE;
use IEEE.std_logic_1164.all;
entity TEST is
port(CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
Q: out STD_LOGIC_VECTOR (9 downto 0));
end TEST;
architecture STRUCT of TEST is
component COUNT -- look ma - no generics ;-)
port(CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
Q: out STD_LOGIC_VECTOR); -- Q is an unconstrained vector
end component;
begin
cnt10:COUNT -- COUNT will be the right size based on Q'length
port map(CLK => CLK,
RESET => RESET,
Q => Q);
end STRUCT;
Do not expect this to work with FPGA Express (but Synplicity and Exemplar are OK). Can
anybody try this with Foundation? It also works with ModelSim if you use the -93 compile
option.
You can also create structures like adder trees with varying number of stages very
elegantly with the above method (whithout generics) using components that instantiate
themselves recursively - and you can write your own LOG2 function if you need one.
Catalin Baetoniu
Article: 15120Jo Depreitere wrote in message <36E3C275.501AE1E8@elis.rug.ac.be>... >Hi, > > Some time ago I have purchased the Foundation Xilinx Student Edition. >Now, I've installed Foundation v1.4 and Foundation Express (with the >license of my v1.3 Student Edition) as permitted by Xilinx. >I have encountered some problems: > > - After installing Foundation Express I wanted to start the Quick Tour, > but selecting it from the menu doesn't seem to do anything. After > installing a patch (not for this problem but a patch to speed up > Express), I can't even select the Quick Tour anymore; > > - A more important problem: in the manuals it says that after implementing > the design and before optimizing it, you can enter constraints by > right-clicking on the implemented chip and selecting "Edit Constraints". > However, the "Edit Constraints" option is not active in that menu. They only enable the constraints editor in the full version. ie you probably have to pay $$ for it! SteveArticle: 15121
Steve wrote: > > Jo Depreitere wrote in message <36E3C275.501AE1E8@elis.rug.ac.be>... > >Hi, > > > > Some time ago I have purchased the Foundation Xilinx Student Edition. > >Now, I've installed Foundation v1.4 and Foundation Express (with the > >license of my v1.3 Student Edition) as permitted by Xilinx. > >I have encountered some problems: > > > > - After installing Foundation Express I wanted to start the Quick Tour, > > but selecting it from the menu doesn't seem to do anything. After > > installing a patch (not for this problem but a patch to speed up > > Express), I can't even select the Quick Tour anymore; > > > > - A more important problem: in the manuals it says that after > implementing > > the design and before optimizing it, you can enter constraints by > > right-clicking on the implemented chip and selecting "Edit > Constraints". > > However, the "Edit Constraints" option is not active in that menu. > > They only enable the constraints editor in the full version. ie you > probably > have to pay $$ for it! Thanks for the info. Well, I guess I was expecting too much. Not that I want to blame Xilinx; it's amazing the possibilities I've got for so little money. Thanks Xilinx! -- mailto:jdp@elis.rug.ac.be | http://www.elis.rug.ac.be/~jdp "The truth may be out there, |"Just when you thought you had it nailed but the lies are inside your head."| down, it walked away with the hammer." (Hogfather - T. Pratchett) | (Wyrd Sisters - T. Pratchett)Article: 15122
In article <7brc24$9a4$1@usenet.pop-mg.rnp.br>, wpadrao@dcc.ufmg.br says... > Hi, > > How can I specify the PAL package in PALASM 1.5? > > I'm trying to compile for PALCE22V10, PLCC package. CHIP _palname PALCE22V10 You might (I can't remember) have to be a little more specific with it like: CHIP _arbpal PALCE22V10H-5 Also, with palasm, if I remember correctly, there is no way to specifiy the PLCC package -- it assumes the DIP pinout. So you have to specify pin 1 when you mean pin 2, etc. I always kept the following chart handy when using palasm with 22V10s. DIP Pins PLCC Pins Pin Name -------------------------------- 1 2 ICLK 2 3 IN0 3 4 IN1 4 5 IN2 5 6 IN3 6 7 IN4 7 9 IN5 8 10 IN6 9 11 IN7 10 12 IN8 11 13 IN9 13 16 IN10 14 17 COFB9 15 18 COFB8 16 19 COFB7 17 20 COFB6 18 21 COFB5 19 23 COFB4 20 24 COFB3 21 25 COFB2 22 26 COFB1 23 27 COFB0 Hope this helps. -- Rich Iachetta iachetta@us.ibm.com I do not speak for IBM.Article: 15123
--------------262800464942700DCFC17D90 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Richard Guerin wrote: > Can anyone suggest a link to a good (FREE) Manchester > Decoder Model that > can be synthesized into an FPGA ? Click on http://www.xilinx.com/xcell/xl17/xl17-30.pdf to see a free, simple and fast schematic solution. I would appreciate to hear from you once you have converted it to working silicon. Peter Alfke, Xilinx Applications --------------262800464942700DCFC17D90 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit <HTML> <BODY BGCOLOR="#FFFFFF"> Richard Guerin wrote: <BLOCKQUOTE TYPE=CITE>Can anyone suggest a link to a good (FREE) Manchester Decoder Model that <BR>can be synthesized into an FPGA ?</BLOCKQUOTE> Click on <P><U><A HREF="http://www.xilinx.com/xcell/xl17/xl17-30.pdf">http://www.xilinx.com/xcell/xl17/xl17-30.pdf</A></U><U></U> <P>to see a free, simple and fast schematic solution. I would appreciate to hear from you once you have converted it to working silicon. <P>Peter Alfke, Xilinx Applications <BR> </BODY> </HTML> --------------262800464942700DCFC17D90--Article: 15124
Jo Depreitere wrote in message <36E3F55E.C3E89707@elis.rug.ac.be>... >Thanks for the info. Well, I guess I was expecting too much. Not that I >want to blame Xilinx; it's amazing the possibilities I've got for so >little money. Thanks Xilinx! I've been told that FPGA Express currently doesn't change its output much at all regardless of your constraints, so you're probably not missing out on as much as you might think (since you can still tell PAR your constraints -- it just might take the time-consuming run through PAR to realize you aren't going to make your speed constraints, although at that point you can go play in EPIC and change part speed grades and see how far off you are anyway...). Alternatively, I've been told that Synplify significantly alters its output based on your constraints. ---Joel Kolstad
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