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Hi! Is there any serial EEPROM available to replace the OTP SPROMs XC17128E/XC17256E for configuring a Xilinx XC4k-device (XC4006/4010E)? What protocol dose it have to use (I^2C, Microwire, SPI,...)? Thanx for any answer. GerdArticle: 14526
Hello Gerald, Here's a link to Espresso and some other tools from Berkeley http://www-cad.eecs.berkeley.edu/Software/software.html and yeah it's FREE :-)! Gerald Shin wrote in message <36B51E45.C4A2D3A0@ucsd.edu>... >I was wondering where I could get a hold of Espresso, the logic >minimization tool, or any other logic minimization tool for a >non-industrial price (under $100 or shareware) somewhere on the net. >This information would be very valuable to me. > >Thanks, >Gerald >Article: 14527
Duck Foot wrote: > > Hi everyone, > I'm confronting many hold time violations and glitches while > post-synthesis simulation. Since I built the logic with quite high level > > description and the logic is very massive, it looks impossible to debug > them one by one. > Is there any canonical strategy applied to these kind of problems, > or can I ask you for some refernces? Hi, Depends on what you are using to synthesis the design and what the target device is... ie If you use synopsys targeting an ASIC set_fix_hold clk Will correct hold errors on clk by inserting delay elements (N1a's etc) Have you had the clock tree balanced ? What are you using to find these hold errors ? motive ? If you can give some more info I may be of some help. Andy.Article: 14528
Gerd Beil wrote: > > Hi! > > Is there any serial EEPROM available to replace the OTP SPROMs > XC17128E/XC17256E for configuring a Xilinx XC4k-device (XC4006/4010E)? > What protocol dose it have to use (I^2C, Microwire, SPI,...)? > Yes, Atmel makes some XC17XXX compatible serial EEPROMs. See: http://www.atmel.com/atmel/products/prod22.htm I used some a couple of years ago with no problems. Tom Burgess -- Digital Engineer National Research Council of Canada Herzberg Institute of Astrophysics Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3 Email: tom.burgess@hia.nrc.ca Office: (250) 490-4360 Switch Board: (250) 493-2277 Fax: (250) 493-7767Article: 14529
We have an immediate need for a contractor for a greater Boston-based corporation that is a world leader in the development of ATM and Ethernet switches, routers, and hubs. The need can be described below. The contract would be for a minimum of 3 months and would likely extend to 6 months, 1 year or more. If you or someone you know would be interested, please let me know. Responsibilities: Perform board level product specification, design, and test. Design and simulation of FPGAs Xilinx Expected Contributions: The candidate will become a member of a product development team responsible for interface boards for new and existing ATM Switches platforms. Qualifications: BSEE or MSEE with 3-5 years experience in product development. Digital design experience required, FPGA Boards being designed with a 50MHZ clock speed Marty Stan - Samaritan Technical Professionals, Inc. - (888) 966-8401 toll-free voiceArticle: 14530
Hello All,
At the risk of hoots and catcalls for a stupid VHDL question, I beg
patience please. I'm still rather new at this.
I'm trying to create a clocked one-shot generator for a Xilinx based
part we're designing. It has a gate input, clock input and output.
The objective is to produce an output pulse of 1-3 clock cycles following
an asynchronus assertion of the trigger signal. Trigger is level sensitive
and is only checked on the leading edge of the clock cycle in order
to synch the one-shot output with the clock.
My code segment for this is below, which will successfully compile, simulate
using ALDEC's VHDL simulator and synthesize under Xilinx Foundation 1.5
(please, no comments about the tools...... I know we can do better... for a
price, all donations gladly accepted!)
----------------------------------------------------------------------------
---------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity oneshot is
port (
clk: in std_logic;
trig: in std_logic;
output: out std_logic
);
end oneshot;
architecture oneshot_arch of oneshot is
begin
process (clk)
variable count: integer; -- count variable
begin
-- wait for clock leading edge
if clk'event and clk = '1' then
-- if trig is not asserted keep count = 2 and output
deasserted
if trig = '0' then
count := 2;
output <= '0';
-- if trig is asserted and count hasn't reached 0 then
assert output
elsif count = 2 or count = 1 then -- have tried count > 0
with no change
output <= '1';
count := count -1;
-- if trig is still asserted, but count has reached 0 the
deassert output
elsif count = 0 then
output <= '0';
end if;
end if;
end process;
end oneshot_arch;
----------------------------------------------------------------------------
---------------
Problem:
When synthesized and mapped to a part it takes up some 29-30 CLBs. It
appears
to be synthesizing a 32 bit counter to accomplish this relatively simple
task. I have
tried all manner of synthesis and implementation options with little impact.
(Yes I
know doing it brute force in DOS without using the GUI interface would be
more
manly....)
What "obvious-to-the-casual-observer" thing am I missing?
Respondents may feel free to respond directly or humiliate me in public here
;-)
With thanks,
Allen Litton
Celeritous Technical Services
alitton@celeritous.com
http://www.celeritous.com
Article: 14531This is just my opinion, so take it with a grain of salt... I never use variables when synthesizing hardware. My impression is that people coming into VHDL from a software background use them, hardware types don't. Variables are meaningless in hardware, everything's a signal. I could be way off here, but I've yet to encounter a situation where using variables was necessary. Getting to your problem: I don't see where you've declared the size of your variable "count". The synthesis tool may be assuming that integers are always represented in hardware as a 32-bit word, hence your large CLB usage. However, a good synthesis tool will map the counter better than that, getting two flip-flops in each CLB (I'm assuming you're using a 4k architecture), but that's another issue. My advice is to declare "count" as a signal, specifying a width equal to whatever count you need. A 2-bit counter should do the trick (no pun intended). Regards, Jamie Celeritous wrote in message <36b899be.0@news.usenetnews.org>... >Problem: > >When synthesized and mapped to a part it takes up some 29-30 CLBs. It >appears >to be synthesizing a 32 bit counter to accomplish this relatively simple >task. I have >tried all manner of synthesis and implementation options with little impact. >(Yes I >know doing it brute force in DOS without using the GUI interface would be >more >manly....) > >What "obvious-to-the-casual-observer" thing am I missing?Article: 14532
> > > NT gets the idea that tweaking a few timing parameters can optimize > > things. > > > > I do not believe NT goes out and changes any of the chip set timing for > > DRAM access. NT would have to have knowledge about EVERY chip set out > > there, and that just isn't the case. > > No. It just keeps the hands off the ones that it don't know. As far as I can see > this is the only plausible explanation for NT (and OS/2) crashing where other > OSs succeed. I just do not believe NT does anything with the chip set. Why do you believe this? Are you speculating or do you have first hand knowledge of this? I believe there are many other plausible explanations...such as it actually uses it, may be NT loads high, may be it just uses a LOT more memory, a LOT more often. May be it actually cares that it gets the right answer, unlike the virus W95 that could care less? I really don't know, but my last guess would be it re-programs the chip set. Also, I believe NT uses features of the processor that others don't.... It also appears Linux has the same memory 'sensitivity'.... AustinArticle: 14533
> >I just bought a 72pin standard PC SIMM. It claims to be 64M 5V 60ns EDO. > >OK, that's all well and good, but it has 12 chips on it. If 72 pin SIMMs > >have a 32 bit data path, how is 32 divisible by 12? > > I have a feeling this isn't what you have, but I have bought SIMMs > that were sold as 4Mx32, but were actually 4Mx36. They are made > by Siemens. I got the SIMM data sheet, and the chip data sheet. THe > chips really are 4Mx3, and 12 of them make 4Mx36. It is likely enough > easier to make 4Mx3 chips than 4Mx4. The SIMMs I had are truly 32 bit SIMMS. The parity bits were not even hooked to anything. They use only three bits of 8 of the chips, and two bits of 4 of the chips. I don't know that anyone intentionally makes a x3 DRAM. The chips on my SIMMs were originally x4 DRAMs (and marked as such), and are just probably fallouts that are sorted to have the same bit bad. The reason 36 bit SIMMs have 12 chips is 8 are for data, and 4 are for parity. True parity SIMMs have to have one parity bit for each byte....and therefore require each parity bit to have its own control signal. AustinArticle: 14534
In article <36b899be.0@news.usenetnews.org>, sales@celeritous.com says...
> When synthesized and mapped to a part it takes up some 29-30 CLBs. It
> appears
> to be synthesizing a 32 bit counter to accomplish this relatively simple
> task. I have
> tried all manner of synthesis and implementation options with little impact.
> (Yes I
> know doing it brute force in DOS without using the GUI interface would be
> more
> manly....)
>
> What "obvious-to-the-casual-observer" thing am I missing?
Allen,
An integer in VHDL is assumed to be 32-bits. You can constrain it by
defining a subtype that is an integer of range 0 to 3 for example to force
the compiler to only use 2 bits for the counter. However, I use SIGNED and
UNSIGNED variables for counters rather than integers to explicitly declare
the size of the counter. For example,
signal Count : unsigned (0 to 1); -- 2 bit counter
The other benefit of this is it its much easier (than with integers) to
pick off the bits of the counter. You can just say Count(0) and Count(1)
to reference the individual bits of the counter.
For something this simple, you may be able to save gates by doing something
like this instead of using a counter:
architecture oneshot_arch of oneshot is
signal temp1, temp2, temp3 : std_logic;
begin
process (clk)
begin
if clk'event and clk = '1' then
temp1 <= trig;
temp2 <= temp1;
temp3 <= temp2;
end if;
end process;
output <= (temp1 or temp2) and not temp3;
Hope this helps.
--
Rich Iachetta
iachetta@us.ibm.com
I do not speak for IBM.
Article: 14535The simple answer is that you define all synchronous systems so that the glitches do not matter. That's what makes them synchronous. All inputs must be stable early enough that the glitches will be gone when the clock occurs. If an input changes and causes a glitch that violates a flip-flops setup and hold, then it, by definition, did not meet system setup and hold times. For example, think of a classic 2 input mux feeding a FF. The select signal must change soon enough ahead of the clock that the output will settle before the FF is clocked. It must work for both the high to low and low to high select transition, regardless of what the inputs are. (assume out = A if S = 0) The glitch that occurs when A=B=1 and S=1->0 (assuming a delay in the select inverter) is stable at the same time as the signal that occurs when A=1, B=0, S=1->0. You could add logic to cover the hazard, but it would not change system performance. Seems simple enough, or did I miss something obvious? bruce Duck Foot wrote in message <36B598CE.5F1658DA@hotmail.com>... > I used sychronous logic, and most of the glitches were found to be >combinations of synchronous signals. I could eliminate some of them by >adding redundant implications, but I still couldn't when the implicants were >not adjacent. > I wonder why most of you say glitches doesn't matter in synchronous >logic. In my humble view, it matters when it occurs on the edge of clock. >What do you think? > >Duck Foot wrote: > >> Textbooks tell how to get rid of static hazards inherent in a sum of >> products network. They say the hazard comes from transitions between >> neighboring product terms, and can be eliminated by adding redundant >> implicants. >> Do we also call the transitions between two apart product terms, >> e.g. diagonally positioned ones, hazard? How can I eliminate glitches >> born of this kind of network? - In this case circling 0's to eliminate >> 0-hazard also results in diagonal configuration. > > >Article: 14536
Hi Gerd, Look at the Atmel web-site www.atmel.com for their (in-system) reprogrammable FPGA Configurators, that are replacements for the Xilinx devices. For "programming" a standard I2C is being used, but they have a special mode for configuring the FPGAs that is being used on reset. Mark Gerd Beil wrote: > > Hi! > > Is there any serial EEPROM available to replace the OTP SPROMs > XC17128E/XC17256E for configuring a Xilinx XC4k-device (XC4006/4010E)? > What protocol dose it have to use (I^2C, Microwire, SPI,...)? > > Thanx for any answer. > > GerdArticle: 14537
I haven't had a chance to look at Don's data, but I'd like to ask a question that seems to have been overlooked: is this a fair test? It seems to me that this is somewhat like comparing a bicycle and a car at traffic lights. >From the description in the original post, and the fact that it synthesises to ~40 CLBs, it seems obvious that this is pretty straightforward hardware. It's a good bet that Don originally produced a schematic that was close to optimal, and it's likely that most people reading this could also produce a very efficient schematic. In other words, we're comparing a synthesiser against the best that can be produced by a human, on a very limited problem. It may be possible to get a synthesiser to produce a description that is as good as Don's schematic, but it's not very likely. If I had a job to produce an optimal synthesised version of this circuit, I'm sure that at least 90% of my time would be spent in examining the resulting netlist or schematic, and messing with the synthesiser, the constraints, and the source code. By the time I'd finished I could almost certainly have produced an optimal schematic, or maybe two of them. But, in the real world, people don't use HDLs to synthesise an optimal 40-CLB design. If you want a realistic test, start with something that requires 400, or 4,000, or 40,000 CLBs. A single human is going to have a major problem producing an optimal design that contains 400 random-logic CLBs (and it would be a brave person who claimed that they could do even this better than a synthesiser, within a reasonable timeframe), let alone 40,000 CLBs - *that's* why we use synthesisers. If you've got a large design team and a lot of money, then sure, you could get each of your engineers to spend a couple of months producing their own optimal 400-CLB block. You might get a shock, of course, when you try to verify your design, at which point you might start to think about using.... VHDL? Surely not. EvanArticle: 14538
On Mon, 01 Feb 1999 23:21:37 +0000, Barry Chu <barryc03@globalnet.co.uk> wrote: >Hi, > >Would anyone tell me how to write a clock multiplier in VHDL? > >BC > CLK <= CLK * 2; -- :) evanArticle: 14539
On 27 Jan 1999 23:08:15 +0100, Geir Harris Hedemark <geirhe@hridil.ifi.uio.no> wrote: >ems@riverside-machines.com.NOSPAM writes: >> Interesting - are you sure about the '93 bits? I put a test case >> through 1998.08 about a month ago, the last time I used DC, and it > >Reasonably. > >I think they have added some form of crude alias support, at >least. I can't remember what other bits they have implemented. > >I can have a look tomorrow, if you want. I think I have some notes >lying around somewhere at work. > >Geir I had another look at this today. I'm no DC expert, but: 1) I still can't get 1998.08 to accept 'entity E is...end entity E'; I don't believe it has the '93 extensions. 2) I checked the printed 1998.08 release notes (SOLD, annoyingly, only gives online info on 1997.01). There's no mention of any '93 extensions, except that the notes say that FPGA Compiler II (ie., FPGA Express) now has initial '93 support - maybe this is what you saw??? 3) The release notes did say that the 1998.08 compiler now supports numeric_std (with some exceptions, to be fixed - xnor/sll/srl/ rol/STD_MATCH/TO_01, as well as problems with divide, rem, and mod). I was so surprised by this that I tried it, and it's true. The notes also gave a location for numeric_std.vhd, but I couldn't find it. I think I said in another thread recently that numeric_std wasn't supported, for which I guess I ought to apologise to Synopsys - they can have my apology when they provide numeric_std for FPGA Express..... :) 4) I also noticed, for the first time, that rising_edge()/ falling_edge() are supported in 1998.08. This wasn't in the release notes, so I guess it's not new, but it certainly wasn't in 3.5a. >I think they have added some form of crude alias support, at >least. I can't remember what other bits they have implemented. This is an interesting one (in FPGA Express). The Express notes have this in the '93 extensions section: "block declarations in a generate statement (VHDL LRM section 9.7) alias keyword (type must be declared)" This, of course, is '87 syntax for aliases, not '93. And surely it was possible to put blocks in a generate in '87?? EvanArticle: 14540
Call For Papers This workshop focuses on the application of new techniques in the representation and realization of discrete functions. AND-EXOR based representations are often simpler than AND-OR based representations, and have other important properties. Decision diagrams are being extensively studied, and have offered powerful new techniques for verification and synthesis. The goal of the workshop is to bring together researchers in these and related fields to discuss new approaches and results. A non-restrictive list of interests includes graph based representations of discrete functions, XOR based synthesis, ESOPs, spectral techniques, AND/OR versus AND/XOR, testability using XORs, Si Implementation and Applications. IMPORTANT DATES: Authors are invited to submit draft papers not exceeding 20 pages by April 1, 1999. Submissions can be sent by e-mail as attached postscript, PDF, Latex or MS Word files. Submissions can also be sent by regular mail in which case five copies should be sent. Please do not submit papers by fax. All submissions should be formatted for 8.5 by 11 inch paper. SEND SUBMISSIONS TO: M. Miller, Program Chair Department of Computer Science University of Victoria Victoria, B.C. CANADA V8W 3P6 rm99@csr.uvic.ca MORE INFORMATION: http://www.csc.uvic.ca/~mmiller/RM99Article: 14541
Hi, The situation is that I have a choice of taking an ASIC design contract (well, an extension actually) and possibly a Digital/FPGA contract with the `possibility' of some ASIC work (both contracts are in the UK). Now, I would like to stay in ASIC and build up my experience there, but the Digital/FPGA job is 5 minutes from where I live, as opposed to a 1 hour drive. Can anyone give me some advice as to the relative merits of doing either contract ... my gut feeling is to stay as close to ASIC as possible, as I believe it to be more lucrative, but need convincing. Any help would be greatly appreciated ... and reply via email to take this off the newsgroups if required. Cheers, Gary Cook. Oxford, UK. -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 14542
Austin Franklin wrote: > > I just do not believe NT does anything with the chip set. Why do you > believe this? Are you speculating or do you have first hand knowledge of > this? No, but as I said before, this is the most plausible explanation. Why ? I have seen the same memory blocks not perform on one mainboard with NT, but performing very well on another mainboard with NT, indicating that the quality of this RAM was not an issue. > I believe there are many other plausible explanations...such as it actually > uses it, may be NT loads high, may be it just uses a LOT more memory, a LOT > more often. May be it actually cares that it gets the right answer, unlike > the virus W95 that could care less? I really don't know, but my last > guess would be it re-programs the chip set. Also, I believe NT uses > features of the processor that others don't.... If using the whole memory space could make your system crash, then all other OS's should have problems too. And all systems crash if they don't get the "right answer" It is not that the OS is determining the sensibility level with regards to the CPU getting bad opcodes :-) If using rare processor features should impose problems, we are dealing with severe hardware bugs, and OK this is possible, but these problems with NT does not show on only one CPU series. And after all, all internal units of the processor shares the same memory bus, and I have seen no indication in Intel reference manuals that some instruction types should be more critical with regards to RAM timing than others (and this IS first hand). Then we are back to the chip set... -- Brian Pedersen, DSP Student _/ _/_/_/ _/_/_/ _/ Applied Signal Processing and Implementation _/_/ _/ _/ _/ _/ Department of Communication Technology _/ _/ _/_/_/ _/_/_/ _/ Aalborg University, Denmark _/_/_/_/ _/ _/ _/ URL: http://www.danbbs.dk/~kibria/brian/ _/ _/ _/_/_/ _/ _/Article: 14543
Austin Franklin wrote: > > > > > NT gets the idea that tweaking a few timing parameters can optimize > > > things. > > > > > > I do not believe NT goes out and changes any of the chip set timing for > > > DRAM access. NT would have to have knowledge about EVERY chip set out > > > there, and that just isn't the case. > > > > No. It just keeps the hands off the ones that it don't know. As far as I > can see > > this is the only plausible explanation for NT (and OS/2) crashing where > other > > OSs succeed. > > I just do not believe NT does anything with the chip set. Why do you > believe this? Are you speculating or do you have first hand knowledge of > this? > > I believe there are many other plausible explanations...such as it actually > uses it, may be NT loads high, may be it just uses a LOT more memory, a LOT > more often. could be, but it's not always when you _use_ NT you get the problem, most of the problems I've seen crashes during the installation, so NT is never really up and running since it is impossible to install it. > May be it actually cares that it gets the right answer, unlike > the virus W95 that could care less? I really don't know, but my last > guess would be it re-programs the chip set. Also, I believe NT uses > features of the processor that others don't.... > > It also appears Linux has the same memory 'sensitivity'.... > > Austin reprogramming the chipset would somehow have to be "on the fly", since you can take a harddrive with an NT on and put it in a different machine and boot it up just fine (more or less) --Lasse --___--_-_-_-____--_-_--__---_-_--__---_-_-_-__--_---- Lasse Langwadt Christensen, MSEE (to be in 1999) Aalborg University, Department of communication tech. Applied Signal Processing and Implementation (ASPI) http://www.kom.auc.dk/~fuz , mailto:langwadt@ieee.orgArticle: 14544
Robert Myers wrote: > > As some/many of you may know, Minc/Synario closed their > doors and had turn over their assets to be liquidated > (see EETimes article, dated around Dec 18, 1998). At least two other FPGA vendors I know about (QuickLogic, Lattice) have Synario as the front-end for their proprietary design suites. I don't know about Lattice, but QuickLogic already own source-code for Synario and their support people say they will continue to use and support it in their tools. Does anyone else agree with me that Synario is (was?) rather a nice design entry package, and that its loss is sad? Jonathan BromleyArticle: 14545
Try the following: WAIT ON clk; CLK_2 <= '1', '0' after 10 ns; -- frequency of clk < 50 MHz CLK_3 <= '1', '0' after 5 ns, '1' after 10 ns, '0' after 15 ns; but please do not try to synthesize this! Good luck, Markus Michel Barry Chu wrote: > Hi, > > Would anyone tell me how to write a clock multiplier in VHDL? > > BCArticle: 14546
In article <796uds$cb3@news.rsc.raytheon.com>, rjmyers@ti.com wrote: > As some/many of you may know, Minc/Synario closed their > doors and had turn over their assets to be liquidated > (see EETimes article, dated around Dec 18, 1998). > > I am trying to determine what people/other organizations > are doing to support the programming of PLDs (and possibly > CPLDs) now that the company that supplied ABEL has shut down. > It appears that Logical Devices may be the only "non-biased" > vendor out their, with their CUPL system that targets > multiple PLD vendor devices. Vantis purchased the Synario GUI and the rights to use the ABEL language in a new product that is available free from the Vantis web site. It is called DesignDirect-CPLD. If you are familiar with Synario the GUI is similar with some added enhancements to the flow including an easy to use constraints editor and timing analyser at the back. It supports all Vantis SPLD and CPLD parts, from the lowly 16V8 up to the 512 macrocell MACH5's. This tool will allow you to migrate old design by maintaining the ABEL language. DD-CPLD allows ABEL, schematic and EDIF inputs so that it can be bolted under any third party synthesis tool. > > Any thoughts/insights on this matter are welcomed. > > -Bob > > p.s. I have not received any inputs from our AVNET reps > regarding what Xilinx's plans are regarding what Xilinx > purchased from the liquidator. > > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 14547
Hello, I am looking for a (PCI based) development board for either PLD's or FPGA's. The function of the board should be sampling of an 8 bit parallel bus (at about 4Mb/s). Is there any development board that already has a PCI interface on it, with the option of programming some local PLD (or FPGA). The board should have software support for windows NT. Does anybody know if any of the major PLD vendors offer such a board? All comments welcome, please reply via email Martin mes@odme.nlArticle: 14548
Hi
I have some problems with a design, that I can not make synthesize properly
in Xilinx Foundation
(the code is listed belov). The problem is that the tool removes to signals
(swon and t16m)from the
netlist and from the macro symbol.
Basicly i have a counter (cur_cnt), that is reset whenever a certain
condition is meet (t16m = '1'), and
incremented whenever an rising edge occours on the signal swon.
I have sent the design to Xilinx hotline, and their "VHDL-expert" claims
that the problem is as follows:
I assign the signal swon_d the value of swon, and after this (but in the
same clocked process) I test
wheater the condition (swon = '1' AND swon_d = '0') is meet, and this can
never be the case, so the
signals swon and t16m can be removed.
I do not agree with this, and so I would like if someone could tell me if I
have completely misunderstood
the principle of VHDL processes. And if someone else have experienced
similar problems and knows
a workaround.
Thanks in advance
Lars Fomsgaard
sync :
PROCESS (clk, RESET)
BEGIN
IF RESET = '1' THEN
swon_d <= '0' ;
cur_cnt <= (OTHERS => '0') ;
-- Some additional lines removed as they were
related to other signals.
ELSIF clk='1' AND clk'EVENT THEN
swon_d <= swon ;
IF t16m = '1' THEN --
Counter for counting overcurrents.
cur_cnt <= (OTHERS => '0') ;
ELSIF swon = '1' AND swon_d = '0' THEN -- Xlinx claims
that this condition can never be meet.
cur_cnt <= cur_cnt + "0001" ; -- as
swon is equal to swon_d.
END IF ;
END IF;
-- Some additional lines removed as they were
related to other signals.
END PROCESS sync ;
Article: 14549Brian Dam Pedersen <brian@kom.auc.dk> wrote: > No. It just keeps the hands off the ones that it don't know. As far as I can see > this is the only plausible explanation for NT (and OS/2) crashing where other > OSs succeed. Linux also seems less tolerant of memory problems. In particular, kernel compiles can die with signal 11. www.bitwizard.nl/sig11 gives some reasons why. Hamish -- Hamish Moffatt Mobile: +61 412 011 176 hamish@rising.com.au Rising Software Australia Pty. Ltd. Developers of music education software including Auralia & Musition. 31 Elmhurst Road, Blackburn, Victoria Australia, 3130 Phone: +61 3 9894 4788 Fax: +61 3 9894 3362 USA Toll Free: 1-888-667-7839 Internet: http://www.rising.com.au/
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