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Brian Drummond wrote: > Unless you had a large supply of them, and no money! > Or maybe your tools only support the old ones, and your > support contract > has expired. Or maybe that's whats soldered to the boards > you inherited. > Unfortunately, not everyone works for a billion dollar > company (yet...) > > The quality of support for established users, stuck with > older (even > obsolete) product lines, says quite a lot about a company. > Especially to > those folks trying to justify a large (and, they hope, > long-term) > investment today. > > I hope this is not a hidden criticism. The XC4000E is an improved design and has new features that are not available in the older part, which, incidentally, had been introduced more than eight years ago. We have tried to maintain the highest possible degree of commonality and compatibility, and we guarantee silicon availabilty for a very long time. I don't know what we could do better. Pricing the improved parts well below the older ones is used as a strong incentive to migrate. Obviously, it does not satisfy every individual situation. Peter Alfke, Xilinx Applications.Article: 14651
Brian Dam Pedersen wrote in message <36B9AB1C.542A84B4@kom.auc.dk>... >But what I don't get is, that the NT errors typically manifest themselves during >install (see Lasses post). They are very consistent in doing so (rules out >spurious RAM errors but not permanent failing to meet timing demands), but can >be cured with a RAM replacement. This indicates a more permanent RAM problem. >But how come that the same RAM blocks in another brand of main board with the >same timing settings suddenly works OK then ? Why does a DIMM work in one motherboard and not another? Sounds like the bad motherboard isn't meeting timing specs. Too much delay somewhere, causing it to fall down. Maybe the timing's on the hairy edge of disaster, and maybe that good DIMM's timing is much better than marked, so it works. I mean, isn't this sort of timing failure taught in FPGA 101? Maybe the DIMM reseller remarked the module. Maybe it met spec once - when it was tested. -- andy ------------------------------------------ Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters@noao.edu "In the beginning, there was darkness. And it was without form, and void. And there was also me!" -- Bomb #20, John Carpenter's "Dark Star"Article: 14652
Andy Peters wrote: > > > Why does a DIMM work in one motherboard and not another? Sounds like the bad > motherboard isn't meeting timing specs. Too much delay somewhere, causing > it to fall down. Maybe the timing's on the hairy edge of disaster, and maybe > that good DIMM's timing is much better than marked, so it works. > > I mean, isn't this sort of timing failure taught in FPGA 101? > > Maybe the DIMM reseller remarked the module. Maybe it met spec once - when > it was tested. > > -- andy > ------------------------------------------ Or it could be the memory module design. You'd think it would be easy wouldnt you. 8 DRAMs on a module with a serial EEPROM. But many of the memory manufacturers get it wrong. You have problems with noise, inadequate power supply decoupling, cross coupling between the address, data abd control lines. Or to cut costs they have gone for a 2 layer or 4 layer board when what they really needed was 6. Or they violated the leength constraints just slightly. And then there are all those clock pins, all unbuffered being driven by the one source.[1] All of these contribute and it means that the module may work in one system but not another, and even in one memory tester but not another. Garry Allen [1] The original DIMM standard for SDRAMS called for on module buffering and regeneration of the clock signals. Intel in its great wisdom decided that buffering was not required and that multiple devices could be driven by the one clock line. And then some of the larger modules didnt work because for some reason the timing constraints werent met.Article: 14653
--------------C7A2FA1793D9AB7F9274A2CB Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Gee, I seem to getting into this thread a bit late. I've been floorplanning with macros from high level VHDL for years (using Exemplar). I did a 2C40 design in 1996 that tiled an array with a pair of interlocking hard macros using a double generate loop in VHDL. It's not a big deal to write a VHDL function that generates the proper LOC string that attaches to the black box instance of the hard macro. The real problem is trying to get the synthesis tool to recognize the timing arcs contained in a black box. This can be done more or less with the Leonardo tool using script commands, but I haven't seen any docs on ways to do this in the source code. Look me up at FPGA 99 and I'll tell you about it. My stance is that VHDL is absolutely the worst design method for FPGA's, except for all other methods. John McCluskey Ray Andraka wrote: > Hmm, I evaluated both synplicity and exemplar a while back and could not get > either to do it. I spent a good part of DesignCon this past week talking to > both and pretty much got the same answer from the FAEs. Exemplar's FAE was the > one that said that it wasn't the spirit of synthesis. Nevertheless, I plan on > re-evaluating both in the coming weeks. I already am aware the FPGA express > won't do it. I'm downloading Evan's page as I type. I was encouraged by > synplicity...their FAE said that this capability is supported in the next > release. > --------------C7A2FA1793D9AB7F9274A2CB Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Gee, I seem to getting into this thread a bit late. I've been floorplanning with macros from high level VHDL for years (using Exemplar). I did a 2C40 design in 1996 that tiled an array with a pair of interlocking hard macros using a double generate loop in VHDL. It's not a big deal to write a VHDL function that generates the proper LOC string that attaches to the black box instance of the hard macro. The real problem is trying to get the synthesis tool to recognize the timing arcs contained in a black box. <br>This can be done more or less with the Leonardo tool using script commands, but I haven't seen any docs on ways to do this in the source code. Look me up at FPGA 99 and I'll tell you about it. My stance is that VHDL is absolutely the worst design method for FPGA's, except for all other methods. <p>John McCluskey <p>Ray Andraka wrote: <blockquote TYPE=CITE>Hmm, I evaluated both synplicity and exemplar a while back and could not get <br>either to do it. I spent a good part of DesignCon this past week talking to <br>both and pretty much got the same answer from the FAEs. Exemplar's FAE was the <br>one that said that it wasn't the spirit of synthesis. Nevertheless, I plan on <br>re-evaluating both in the coming weeks. I already am aware the FPGA express <br>won't do it. I'm downloading Evan's page as I type. I was encouraged by <br>synplicity...their FAE said that this capability is supported in the next <br>release. <br><a href="http://users.ids.net/~randraka"></a> </blockquote> </html> --------------C7A2FA1793D9AB7F9274A2CB--Article: 14654
> > Unless you either type REALLY fast, and make NO mistakes in your HDL, and > > the tools behave right on (for the hour) AND the person you are competing > > against with schematics draws them with stone and chisel, drinks heavily, > > and bashes his/her thumb with the hammer, this just isn't how it's gonna > > play out. And your 'cost reduction' can take from a lot more time to > > never. > > Sure, you make fun of my design methodology now, but the next > release of Stone and Chisel will support multiple chisel sizes. > Then I'll be able to keep up with VHDL. Version 2.08.3.2.3.6 of 'Chicken and Scratch' is now available! The simulator is now fully functional and the new HDL editor allows you to do much more than just 'scratch' the surface. Stone and Chisel is still far better at partitioning the Configurable Logic Blocks though, and with the new chisel widths, it will even work better with the fine grained architectures.Article: 14655
-------------------------------------------------------------------------
Announcement and First Call for Participation
Ph.D Forum at DAC '99
Submission Deadline: March 15, 1999.
http://www.cs.washington.edu/homes/soha/forum
-------------------------------------------------------------------------
Goals:
The Ph. D. forum provides a structured way of increasing interaction
between academia and industry. The forum's immediate goals are to
provide graduate students with feedback on their thesis work from
other researchers, and to give CAD and system companies a chance to
preview academic work-in-progress.
Format:
** Submission: Students within one or two years of completing their Ph.D.
submit a one-page abstract of their thesis, along with a
university-approved thesis proposal or a published
paper. (Deadline March 15, 1999)
** Review: The submission will be reviewed to ensure that the abstract
is supported via the accompanying paper/proposal.
** Awards: Some travel grants and DAC registrations will be awarded to
participating students -- provided they do not receive any DAC
financial assistance. (Notification April 30, 1999)
** Poster Session: Students will present their work during a poster
session hosted by SIGDA during their member meeting --
Tuesday, June 22, 7:00 - 9:00 p.m.
Background:
The first Ph.D. forum in design automation was held during DAC 1998. Nine
students (7 from the U.S. and 2 from Europe) participated. The poster
session was a positive experience for all. The students' feedback included
the following comments:
"It was a truly positive experience. I got a lot of constructive
criticism and feedback".
In response if the participant would recommend it to a friend,
"Absolutely, especially if the friend had passed his or her
candidacy exam and was half-way through the work. I think this is the
time in a Ph.D. when attending the forum would be most useful."
"It [the forum] was extremely useful and I got some interesting
and encouraging feedback. I also had a great time being
there....It's a good place to get encouragement and direction for
future work."
More Information:
For more information, visit the web site:
http://www.cs.washington.edu/homes/soha/forum
or send inquiries to:
Soha Hassoun, soha@eecs.tufts.edu, or to
Olivier Coudert, coudert@mondes.com
Article: 14656
rk wrote in message <36BC45CF.86B3111A@NOSPAMerols.com>...
>anyways, instead of messing with structural VHDL and typing in names
>for each component, which is incredibly tedious, it's easier and far more
>readable (imo) to do that with a schematic. then take a top level
>schematic, and hook up your blocks consisting of either lower level
>schematics or vhdl.
I go along with this mixed HDL/schematic approach. We are starting out in
VHDL, as our designs are starting to expand beyond the point where
schematics take too long.....
process (schematicsbetter, HDLbetter)
begin
pigeons <= cat ;
end process;
:-)
We are using the mixed approach because we have useable designs in
schematics, and the risk and time of converting to VHDL is too much.
We use VHDL for logically complex blocks, where we can't be bothered to
spend the time working out what the logic is. Timing and real-estate are
not critical, it's I/O we run out of.
A lot of the design is data path stuff, and that is quick and easy to do in
schematics
>=====================================================
>
>> For cost reduction, if you have the volume to care if the design is in a
>> part costing 4 US$ more or even 40 US$ more, perhaps a similar method
>> would work.
I think we are lucky in the cost area. We have only bought about 20 or so
devices in the last 2 years. If we need a bit more speed we swap to a
faster device. FPGAs are only part of what we use, so we can't spend the
time tweaking the design.
>
>the 'fuss factor with hdl's, for
>many types of logic blocks, do not make them much if any faster than a
>schematic and can even by slower; that's one reason why i still do
>schematics and not a pure hdl flow. for some blocks hdl is faster.
Agreed. This is why I think we will never drop schematics completely
The 'plug and play' type of synthesis tool suits us really well. The way we
work means that we change the functionality of a circuit almost continually,
and it is good to be able to run a design through a synthesiser quickly.
The function of the FPGAs is dictated by the requirements of the other
devices in the system, and changes pretty quickly.
Configuration control is a nightmare :-(
Jim
Article: 14657Jim King wrote: > rk wrote in message <36BC45CF.86B3111A@NOSPAMerols.com>... > > >anyways, instead of messing with structural VHDL and typing in names > >for each component, which is incredibly tedious, it's easier and far more > >readable (imo) to do that with a schematic. then take a top level > >schematic, and hook up your blocks consisting of either lower level > >schematics or vhdl. > > I go along with this mixed HDL/schematic approach. We are starting out in > VHDL, as our designs are starting to expand beyond the point where > schematics take too long..... > > process (schematicsbetter, HDLbetter) > begin > pigeons <= cat ; > end process; > :-) > > We are using the mixed approach because we have useable designs in > schematics, and the risk and time of converting to VHDL is too much. > We use VHDL for logically complex blocks, where we can't be bothered to > spend the time working out what the logic is. Timing and real-estate are > not critical, it's I/O we run out of. > A lot of the design is data path stuff, and that is quick and easy to do in > schematics one interesting situation is where contractor A did a design with a schematic, passed it on to subcontractor B to program and verify it who passed to expert vhdl house sub-subcontractor C who took the schematics, converted an entire 16,000 gate, schematic-entered design into structural vhdl, then ran it through a synthesizer. the result? didn't work, A and B had no clue what was going on, mods were made to the "schematic" at the structural vhdl level, and it was *painful* to read and go through, essentially reconstructing a schematic page by page of textural, structural code. it was an interesting process ... well, actually, it was a pain. rkArticle: 14658
Peter Alfke schrieb in Nachricht <36BF6010.3F1642E5@xilinx.com>... .... snippp...... >and compatibility, and we guarantee silicon availabilty for >a very long time. >I don't know what we could do better. > >Peter Alfke, Xilinx Applications. > I know, what you could do better: 1. We use the XC7336Q on many of our products. Hey, tell me where I can get them now !!!! 2. Where is a bitstream compatible replacement for the obsolete part XC4005A-5PQ160 ?? 3. What's about the Xilinx Antifuse parts ? Where did they go ?? 4. What happened to the XC6xxx ????? 5. Why cant I reuse my Orcad designs with Foundation ? Why does the import funktion not work ? Why dont Xilinx care at all ??? 6. Why are busses in the schematics corrupted by updating M1.4 to M1.5 ??? I could tell you a lot more things that Xilinx could do better. Manfred KrausArticle: 14659
I'm also looking for a project board, but only with Xilinx XC4062XL (PG475) FPGA. Any suggestion would greatly be appreciated. Thanx. Sanjeev wrote: > I am looking for a good project board that will take a Xilinx XC4085XL (PGA > 559) FPGA. Anyone have any good suggestions? > > ThanksArticle: 14660
We maintain a mostly up-to-date list of boards on The Programmable Logic Jump Station at http://www.optimagic.com/boards.html. There are a few boards that may fit your needs. However, I can't say that I know of one that uses the XC4085XLPG559. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Sanjeev wrote in message ... >I am looking for a good project board that will take a Xilinx XC4085XL (PGA >559) FPGA. Anyone have any good suggestions? > >Thanks > >Article: 14661
You can find a complete list of serial PROMs for FPGAs on The Programmable Logic Jump Station at http://www.optimagic.com/companies.html#SPROM. The Atmel serial PROMs are reprogrammable and there is more information available at http://www.atmel.com/atmel/config.htm. There are now also versions that support Altera FPGAs. Be forewarned that you need the right part for the job. For example, the AT17C512 supports Xilinx (and others) while the AT17C512A matches the Altera footprint. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Mark Korsloot wrote in message <36B8D28B.F34F7EEB@computer.org>... >Hi Gerd, > >Look at the Atmel web-site www.atmel.com for their (in-system) >reprogrammable FPGA Configurators, that are replacements for the Xilinx >devices. For "programming" a standard I2C is being used, but they have a >special mode for configuring the FPGAs that is being used on reset. > >Mark > > >Gerd Beil wrote: >> >> Hi! >> >> Is there any serial EEPROM available to replace the OTP SPROMs >> XC17128E/XC17256E for configuring a Xilinx XC4k-device (XC4006/4010E)? >> What protocol dose it have to use (I^2C, Microwire, SPI,...)? >> >> Thanx for any answer. >> >> Gerd >Article: 14662
Well, I obviously asked for punishment. And from a compatriot to boot. So here are my answers on those subjects I feel comfortable to answer without research, i.e. FPGA hardware: Manfred Kraus wrote: > I know, what you could do better: > > 1. We use the XC7336Q on many of our products. Hey, tell > me where I can get > them now !!!! I don't know, will let you know if I can find out. > > > 2. Where is a bitstream compatible replacement for the > obsolete part > XC4005A-5PQ160 ?? After extensive "last buy" offers, the XC4000A is officially obsolete, but if you need up to 2,000 pieces of XC4005A-5PQ160C we will gladly sell them to you from our inventory. Just ask ! > > > 3. What's about the Xilinx Antifuse parts ? Where did they > go ?? We put a lot of effort, enthusiasm and creativity into the XC8100 product family, but retracted it ( it had hardly been introduced ) when we found that the support effort in manufacturing and testing was larger than we thought reasonable. Note that the two established antifuse manufacturers show less than stellar performance. In my opinion( please no flames ! ) antifuse has no future outside some rad hard applications, and is under attack even there. > > > 4. What happened to the XC6xxx ????? Similar story: We acquired Algotronics, pumped money and effort into the Scottish operation, hired a lot of people, made parts and created design software. University researchers liked it, but the response from commercial customers was less than lukewarm, essentially zero. So we retracted it from the commercial market, and invited researchers to contact us for limited availability. > > > 5. Why cant I reuse my Orcad designs with Foundation ? Why > does the import > funktion not work ? > Why dont Xilinx care at all ??? I don't know, I think we care. > > > 6. Why are busses in the schematics corrupted by updating > M1.4 to M1.5 ??? I don't know enough about this and other bugs. Complex software will always have some problems. It is important that the supplier addresses the problem, provides work-arounds, and fixes it as soon as possible. Unfortunately, we live in an imperfect world. > > > I could tell you a lot more things that Xilinx could do > better. Please tell me, preferably not in public.At least I managed to give you good information about XC4000A. Peter Alfke Xilinx Applications EngineeringArticle: 14663
Yes, without any problem Don`t forget to prepare include file from your VHDL source files, then = you can use this inc file as function definition in the ahdl part of = your design Goon luck Lev Razamat System designer Phasecom Ltd. JerusalemArticle: 14664
Try next
clk2 <= clk xor flipflop;
if (clk2 'event and clk2 = '1') then
flipflop <= not(flipflop);
end if;
I used this not once.
Lev Razamat
System designer
Phasecom Ltd. Jerusalem
ICQ# 3347700
Barry Chu <barryc03@globalnet.co.uk> wrote in message
news:36B63701.C707972B@globalnet.co.uk...
>Hi,
>
>Would anyone tell me how to write a clock multiplier in VHDL?
>
>BC
>
Article: 14665>>>>>>>> Job posting deleted by archive ownerArticle: 14666
Hi, I am using MAX+plusII Ver. 8.2. I want to know is it possible to write a mixed code AHDL (Altera HDL) and VHDL and compile it using MAX+plusII. (e.g. Call VHDL function from AHDL code) Thanks. A.K.Article: 14667
On Tue, 09 Feb 1999 21:03:55 +0700, Apinetr Unakul <apinetr@ce.kmitl.ac.th> wrote: >I'm also looking for a project board, but only with Xilinx XC4062XL (PG475) >FPGA. Any suggestion would greatly be appreciated. > We use a MicroEnable board from Silicon Software (www.silicon-software.com) for evaluating our designs. It has a XC4062XL (PQ240,speedgrade -2) and 2MB fast SRAM on it. The integration into Windows NT is very good. Programming is easy, which means that transfers to the onboard RAM are done via memcpy. You also have the possibillity of doing DMA transfers with a speed of about 90-110 MB/s. They also have programming libraries for Linux (which I dont know). And (what is important for me) the support is very good. It is a small german company and so phoning them is easy ;) No I don't work for Silicon Software. ;) details via email, if you like. Hope it helps Mats -- Matthias Brucke Computer Science Departement VLSI Group University of OldenburgArticle: 14668
Try RC1000 at www.embedded-solutions.ltd.uk Sanjeev wrote in message ... >I am looking for a good project board that will take a Xilinx XC4085XL (PGA >559) FPGA. Anyone have any good suggestions? > >Thanks > >Article: 14669
John Larkin wrote: > Hi, > > I think I've invented a neat circuit for a specialized digital PLL, and > of course I want to keep it proprietary. So if I make a product using a > Xilinx FPGA, the config bitstream can't be hidden from a competitor who > gets his greedy hands on one. I assume that an outright copy is a > copyright violation, so I'm not too worried about that. So here's the > issue: Is it feasible that someone could decompile the stream and > recover the circuit CONCEPT? Are there any tools to help them do this? > Would it be easy, or an enormous task? > > (Yes, I could maybe patent it, but that's a nuisance... I'd rather just > keep it a secret). > > John > > -- > > ********************************************************************h > > John Larkin, President phone 415 753-5814 fax 753-3301 > Highland Technology, Inc > 320 Judah Street jjlarkin@worldnet.att.net > San Francisco, CA 94122 http://www.highlandtechnology.com Take a look at Xilinx programmable logic data book. In the paper "Configuration issues: Power-up, volatility,Security , Battery Back-up" they say that Xilinx keeps the interpretation of the bitstream closely guarded secret and it is virtually impossible to interpret the bitstream in order to undestand the design or make modifications on it. -- =================================================================== Sergio A. Cuenca Asensi Dept. Tecnologia Informatica y Computacion (TIC) Escuela Politecnica Superior, Campus de San Vicente Universidad de Alicante Ap. Correos 99, E-03080 ALICANTE ESPAŅA (SPAIN) email : sergio@dtic.ua.es Phone : +34 96 590 39 34 Fax : +34 96 590 39 02 ===================================================================Article: 14670
On Tue, 09 Feb 1999 10:31:09 -0800, Peter Alfke <peter@xilinx.com> wrote: > > >Well, I obviously asked for punishment. And from a >compatriot to boot. So here are my answers on those subjects >I feel comfortable to answer without research, i.e. FPGA >hardware: > >Manfred Kraus wrote: > >> I know, what you could do better: >> >> 4. What happened to the XC6xxx ????? > >Similar story: We acquired Algotronics, pumped money and >effort into the Scottish operation, hired a lot of people, >made parts and created design software. University >researchers liked it, but the response from commercial >customers was less than lukewarm, essentially zero. So we >retracted it from the commercial market, and invited >researchers to contact us for limited availability. > Ouch. This one hurts, partly because I have been forced to watch reconfigurable computing struggle along since about 1990, (only recently found myself in a position to join in) and partly because Algotronics are my compatriots. But given British industry's track record of innovation, and complete failure to exploit that innovation, I would guess that being bought by Xilinx was the best thing that could have happened to Algotronics. The XC6200's problems I suspect are/were twofold: - there isn't yet enough market for general-purpose reconfig coprocessors ( or development tools, standard coprocessor interfaces, etc etc etc) - and performance on math was less than stellar compared with coarse-grained logic with fast carry chains (XC4000). So for performance, the ideal reconfig chip would be something like the XC4000, but with more logic and partial reconfigurability. How about it Peter? ;) - Brian p.s. and would a public domain bitstream format for Virtex be too much to ask? (Or maybe some derivative of Virtex) Because something like that would be important to open up reconfig tool development, and IMO it would be better to ride a leading edge family rather than develop an entirely separate one for the purpose...Article: 14671
Hi,
I have a problem with a FPGA design (XC4036XL-1).
I have 2 different clocks into the design and I use a MUX to choose
between these two, but I can not set constraint to the clock after the
MUX.
I have defined my constraints for these 2 clocks but since these
clocks are connectected to a block and my main clock is the one
comming out of that block, synopsys does not sends the contraints to
Xilinx which cause a lot of problem for me.
I have mannaged to put constraints to the output of the MUX block, but
this constraint does not apear in the .NCF file (which Xilinx uses as
input).
Is there anyone who have mannaged to do so? And how?
I desperately need to know the answer to this question because it is
the only part of my design which does not work as it should and I am
having a lot of problem simulating the design after mapping (I use
Modelsim 5.2a to simulate the time_sim.vhd by using the time_sim.sdf).
I really appreciate any tips or help to solve this problem.
Best regards,
Farhad A.
Stockhlm/Sweden
PS: Here is the command I use to generate the clock in synopsys:
/* first clock */
create_clock -period sample_clk_period -waveform {0
sample_clk_half_period} CLK_FPGA
/* second clock */
create_clock -period clk_period -waveform {0 clk_half_period} CTRL_CLK
/* Clock output of the MUX */
create_clock -name FPGA_REF_2_CLK -period 50 -waveform { 0 25 } {
DDC_CORE_1/CLK_GEN_1/FPGA_REF_2_CLK }
/* Clock input to the section that uses the above clock */
create_clock -name CLK -period 50 -waveform { 0 25 } {
DDC_CORE_1/dci_int_1/CLK }
set_clock_skew -uncertainty clock_uncertainty -propagated { CTRL_CLK ,
CLK_FPGA, CLK, FPGA_REF_2_CLK}
/* And I can see that Synopsys has accepted the above statemtns and
reports the clocks when I use the following commands: */
all_clocks()
report_clocks -attributes
The result is:
****************************************
Report : clocks
Design : pad
Version: 1998.08
Date : Tue Feb 9 20:54:24 1999
****************************************
Attributes:
d - dont_touch_network
f - fix_hold
p - propagated_clock
Clock Period Waveform Attrs Sources
--------------------------------------------------------------------------------
CLK 50.00 {0 25} p
{DDC_CORE_1/dci_int_1/CLK}
CLK_FPGA 38.00 {0 19} p {CLK_FPGA}
CTRL_CLK 20.00 {0 10} p {CTRL_CLK}
FPGA_REF_2_CLK
50.00 {0 25} p
{DDC_CORE_1/CLK_GEN_1/FPGA_REF_2_CLK}
--------------------------------------------------------------------------------
1
Article: 14672
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Article: 14673Hi folks, does anyone know whether the Altera Freecore Library www.acte.no/freecore has moved ? The server responds with ".. cannot find file .." -TomArticle: 14674
One first step may be the use of PLXMON from PLX. You can do reads and writes and also run batched commands. PLXMON is free downloadable from the PLX site. -Tom John Chambers schrieb in Nachricht <36BEC237.CB8ED98@ihr.mrc.ac.uk>... >I'm trying to develope software to access memory on the PCI bus through >the PLX9050. Does anyone have any examples of how to initialise the >chip and read/write to the memory? Ideally I don't want to spend more >money on a device driver developement toolkit - there must be some 'C' >code for DOS out there somewhere that I can use to get an idea of what >needs to be done. Any code or book references welcome. > >John > >johnc@ihr.mrc.ac.uk
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