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Antonio, I found the following document on the Actel site: http://www.actel.com/appnotes/s04_18.pdf Wiggo. schaltung@hotmail.com wrote: > Hi everyone, > > I want to have some sort of Digital PLL implemented in an XILINX FPGA. Does > anyone know of any Literature, Core or information of this type of PLLs? > > Regards > Antonio Moreno > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own -- +---------------------------------------------------------------+ | Wiggo Olufsen | | Cypress Software AS Phone : +47-73-52 46 59 | | P.O.Box 2668 Fax : +47-73-52 46 80 | | N-7001 TRONDHEIM E-mail: wiggo.olufsen@online.no | | NORWAY | +---------------------------------------------------------------+Article: 14801
Hi, Paul Baxter <paje@nospam.globalnet.co.uk> schrieb in Nachricht 7af83k$rvs$1@newnews.global.net.uk.../// >Thanks Rune for the efforts you put in over the last few years with the >freecore library. > >Sad to see that Altera couldn't make you an enticing offer to stay with >their product range! > >Paul Baxter > Let me tell you about our experiences with ALTERA: we are working with ALTERA FPGA (FLEX8K, 6K) and two weeks ago I tried to get a new software version. When we bought our MAX+PLUSII we also made a maintenance contract. That way we got several updates... When the software maintenace ran out, we decided to keep the software as it, so we are working with MAX+PLUSII ver 8.0 at the moment. Now forced to change to 6K or a great 10K in our designs we have to upgrade and ... ALTERA does not honour if you have an old version. Buying a new software (and a new dongle) costs as a "upgrade" :-( ALTERA takes $2000 for one year, so after one year you can freeze your software version or pay another $2000 :-( This is no good politics, as this forces you to pay year by year to get newest devices support. Thik this will force some guys to change to XILINX ? Bye, Carlhermann SchlehausArticle: 14802
Hi, Philip Freidin <fliptron@netcom.com> schrieb in Nachricht fliptronF7AEJy.6Jo@netcom.com.../// >Check the signal integrity on your configuration clock. In particular, >look at both the rising and falling edge with a 300MHz scope (or better. >a 100MHz or 200MHz scope can miss clock problems that the FPGA/EPROM can >react to). Check at both ends of the trace, and check BOTH edges. >Remember to keep the scope ground wire as short as possible (less than 2 >inches would be a good goal.) You are looking for "U" turns in the edges >of the clock during the transitions. These can be only a few nanoseconds >wide, and maybe only a few 100 mV high. >If you see anything like this, you have a termination problem that you >must remedy. > >Philip Are the 6K FPGA such sensitve to the signals @ DCLK ? Well I've just started a transition from an EPF81500 (which get'S to small in LCells and to expensive in money) to an EPF6016A. Hope it will work without such problems. Furthermore, how and with what values should the Configurations lines be terminated to ensure correct function of FPGA ? Thanx, Carlhermann SchlehausArticle: 14803
Hi All, Until quite recently - I worked as a Field Applications Engineer with one of the distributors of Altera programmable logic. During that time - I created the "Altera FreeCore Library" - a web site of free information and logic cores written specifically for Altera CPLD's. Recently - I changed my job - and I'm now working with the Norwegian distributor of Xilinx programmable logic, BIT Elektronikk. It is obvious that I cannot actively support Altera anymore. Instead - I created freecore.com - my own personal web site - where I will share some of my programmable logic experiences with you. Focus will be on VHDL, Verilog, Design Tools and Architectures. Once donated to the Public Domain - and with many contributions from excellent designers throughout the world - it is not my right to completely remove the "Altera FreeCore Library" from the web. You will find a "frozen" version of it here - but there is no support for it. If you have questions - don't email me - I cannot help you. Sorry. Website is at http://freecore.com Regards, Rune Baeverrud rune@freecore.comArticle: 14804
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Article: 14805hi, has anyone done any comparative analysis of these two news families ? Would you like to share ? muzo Verilog, ASIC/FPGA and NT Driver Development Consulting (remove nospam from email)Article: 14806
Sander Vesik <sander@haldjas.folklore.ee> writes: > Can you actually name these tools? Yes, I specificly mean those written > by Linux people as opposed to say "magic". FreeHDL is one, although only in its alpha stages. GeirArticle: 14807
One of the main advantages of FPGAs is that you can fix a bug or make a minor change to the design and ship new bits to the field. That requires pinlocking. So I assume that any software that doesn't work well with locked pins is brain damaged, aka useless. An alternate way of looking at things is that floorplanning can extend to the pins too. I often pick pins after carefully considering the local routing in order to make sure the final result will be fast enough. This sort of thing can be very important with chips like the Xilinx 3000 series which have direct connections that save a significant fraction of the total cycle time over misc local routing. Am I out to lunch to be thinking that way? -- These are my opinions, not necessarily my employers.Article: 14808
"Rune Baeverrud" <fpga@iname.com> writes:
> Once donated to the Public Domain - and with many contributions from
> excellent designers throughout the world - it is not my right to completely
> remove the "Altera FreeCore Library" from the web. You will find a "frozen"
> version of it here - but there is no support for it. If you have questions -
> don't email me - I cannot help you. Sorry.
>
> Website is at http://freecore.com
Are there any plans of extending the site to other architectures?
Achim Gratz.
--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW: http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 463 - 8325
Article: 14809Geir Harris Hedemark wrote: > > Sander Vesik <sander@haldjas.folklore.ee> writes: > > Can you actually name these tools? Yes, I specificly mean those written > > by Linux people as opposed to say "magic". > > FreeHDL is one, although only in its alpha stages. No, there are still least Electric an Alliance, have a look at the FAQ posted in this group. Bye Tom!Article: 14810
In comp.arch Thomas Reinemann <thomas.reinemann@mb.uni-magdeburg.de> wrote: > Geir Harris Hedemark wrote: > > > > Sander Vesik <sander@haldjas.folklore.ee> writes: > > > Can you actually name these tools? Yes, I specificly mean those written > > > by Linux people as opposed to say "magic". > > > > FreeHDL is one, although only in its alpha stages. > No, there are still least Electric an Alliance, have a look at the FAQ posted in > this group. But Alliance counts just as magic. > Bye Tom! -- Sander There is no love, no good, no happiness and no future - all these are just illusions.Article: 14811
Look at the Xilinx Virtex series of FPGAs. For info on the Virtex devices see: http://www.xilinx.com/partinfo/virtex.pdf For info on the DLLs in the Virtex devices see: http://www.xilinx.com/xapp/xapp132.pdf -Jeff schaltung@hotmail.com wrote: > Hi everyone, > > I want to have some sort of Digital PLL implemented in an XILINX FPGA. Does > anyone know of any Literature, Core or information of this type of PLLs? > > Regards > Antonio Moreno > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 14812
Hi all, I have some VHDL code (below) that I would like to "put" into an array R so that I can select the register by typing R[ra] where ra is 0 for REGA, 1 for REGB, 2 for REGC and 3 for REGD. Any ideas? --current and next state of the four 8-bit general purpose registers SIGNAL curr_REGA, next_REGA: STD_LOGIC_VECTOR (7 DOWNTO 0); -- register A SIGNAL curr_REGB, next_REGB: STD_LOGIC_VECTOR (7 DOWNTO 0); -- register B SIGNAL curr_REGC, next_REGC: STD_LOGIC_VECTOR (7 DOWNTO 0); -- register C SIGNAL curr_REGD, next_REGD: STD_LOGIC_VECTOR (7 DOWNTO 0); -- register D Thanks for your time Jamie MorkenArticle: 14813
On Wed, 17 Feb 1999 13:24:35 +0000, Eduardo Augusto Bezerra <E.A.Bezerra@sussex.ac.uk> wrote: > >Thank you for the detailed explanation. I know I have a long way >ahead. I think my big mistake was to try to use the technology >independent feature of VHDL. Just in case, I'll save the present >version in a safe place, and I hope in few years I can synthesize >it properly. > >I'm going to make some changes in my design in order to turn it >a device specific one. > I believe that code written to allow ram inferencing will also successfully synthesise to individual FF's when you move it to an ASIC process. It is just an array of storage locations, expressed in a way that the synthesis tool will recognise as a special case when targetting FPGA. There is nothing Xilinx-specific about the way it is expressed (or Altera- specific, or for that matter Leonardo or Synplify-specific) about the code involved. So your modified solution should still be portable to ASIC later on. - BrianArticle: 14814
ram inference (like synplify can do) is not really suitable for ASIC (as yet) - no RESET ! Brian Drummond wrote: > > I believe that code written to allow ram inferencing will also > successfully synthesise to individual FF's when you move it to an ASIC > process. It is just an array of storage locations, expressed in a way > that the synthesis tool will recognise as a special case when targetting > FPGA. There is nothing Xilinx-specific about the way it is expressed (or > Altera- specific, or for that matter Leonardo or Synplify-specific) > about the code involved. So your modified solution should still be > portable to ASIC later on. > > - BrianArticle: 14815
jamie morken wrote: > > Hi all, > > I have some VHDL code (below) that I would like to "put" into an array R > > so that I can select the register by typing R[ra] where ra is 0 for > REGA, 1 for REGB, 2 for REGC and 3 for REGD. Any ideas? > > --current and next state of the four 8-bit general purpose registers > SIGNAL curr_REGA, next_REGA: STD_LOGIC_VECTOR (7 DOWNTO 0); -- register > A > SIGNAL curr_REGB, next_REGB: STD_LOGIC_VECTOR (7 DOWNTO 0); -- register > B > SIGNAL curr_REGC, next_REGC: STD_LOGIC_VECTOR (7 DOWNTO 0); -- register > C > SIGNAL curr_REGD, next_REGD: STD_LOGIC_VECTOR (7 DOWNTO 0); -- register > D > > Thanks for your time Declare your register file like this: SUBTYPE byte IS STD_LOGIC_VECTOR(7 downto 0); TYPE regs IS ARRAY (3 downto 0) OF byte; SIGNAL reginstance : regs; Now you can access reginstance(0) and so on. If you need individual bits, you have to put your register into a temporary variable before accessing it eg: tmp:=reginstance(0); nibble<=tmp(7 downto 4); Hope this helps -- Brian Pedersen, DSP Student _/ _/_/_/ _/_/_/ _/ Applied Signal Processing and Implementation _/_/ _/ _/ _/ _/ Department of Communication Technology _/ _/ _/_/_/ _/_/_/ _/ Aalborg University, Denmark _/_/_/_/ _/ _/ _/ URL: http://www.danbbs.dk/~kibria/brian/ _/ _/ _/_/_/ _/ _/Article: 14816
>Pawel Michocki wrote: > >Hi Pawel, > >I started a project last year using Orcad Express 7.2. I don't think >they had a "Plus" version back then. After taking the 5 day training >course I convinced myself that I should try using VHDL for my design. I >did some work is a small section of the design and decided to proceed >with VHDL. Once I had much of my design entered and implemented, the >VHDL tools started behaving badly. I had numerous problems with crashes >(due to constructs in my code that the compiler or simulator didn't >like). The support was not adequate. I finally abandoned Orcad for >Xilinx Foundation. I get much better support and although the Foundation >Express compiler has its problems, I always seem to be able to get my >work done. > Exactly same experience here. We wasted a lot of time in trying to get OrCAD v7.x work well with VHDL design. Finally, gave up and upgraded Xilinx software from Alliance to Foundation. The tech supports from Xilinx and OrCAD are the same situations with their products. >I have received my copy of Orcad Express Plus v9.0, but have not even >put it on my machine. After posting my story a few times in this >newsgroup I even received an email from someone at Orcad asking me to >give the new version a try. But when I wrote back asking for specifics >about which problems had been fixed, I never received a reply. So the >Orcad box still sits on my shelf (or is it on the floor beside the trash >can?). Unfortunately I can't, at this point, fully evaluate the SW if I >wanted to. We converted our Alliance license to a Foundation license and >I no longer have the libraries for Orcad (??unless they come on the >Orcad CD??). > We got OrCAD Express V9.0 only, not Plus version. I just tried it for one day and never used it again. Now I only use V7.2 for schematic drawing. Another story, we bought OrCAD Layout plus together with Express. Almost 6 months later, we had a guy with 20+ year PCB layout experience joined us. He tried OrCAD Layout for a few months and finally switched to ACCEL. >If you are using VHDL for your design, I would say to drop Orcad like a >hot potato(e). If you have had different results, please let me know. > >P.S. I once asked through this newsgroup, for anyone using Orcad doing >FPGA work to let me know of their success. I got no replies. I repeat >the request. > >*************************************************************************** ************** >If anyone out there is using Orcad successfully for FPGA design, please >post your results. >*************************************************************************** ************** > > >-- > >Rick Collins > >redsp@XYusa.net > >remove the XY to email me.Article: 14817
Carlhermann Schlehaus wrote in message <7afhg8$h0d$1@news03.btx.dtag.de>... >This is no good politics, as this forces you to pay year by year to get >newest devices support. >Thik this will force some guys to change to XILINX ? Xilinx is no different. No Virtex or Spartan support for the XACT 6.x.x tools! Gotta get M1.x And the new M1.x tools don't support the (obsolete) XC73xx chips (we have several of those in a design I have to maintain). So you need to maintain two versions of the tools; one for the old chips and one for the new. -- andy ------------------------------------------ Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters@noao.edu Don't waste apostrophes! The plural of the acronym for "personal computers" is PCs, NOT PC's.Article: 14818
Hello, I am trying to map a design to some XC4010e-3 FPGAs, in this design, I need some registers to be triggered at the clock's rising edge and some registers to be triggered at the clock's falling edge. I am not sure if Xilinx 4000e FPGAs provide registers that can be triggered at falling edge of the clock. Further more, I am using some counters by logiblox and it seems I can hardly modify them to let them be triggered at the falling edge. Any suggestions? Thanks! -- ZhenArticle: 14819
Hi, New versions (Version 4.22) of Versatile Place and Route (VPR) and VPack (Version 2.09) are now on my web page, at http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html. VPR is a placement and routing tool for FPGA architecture research, while VPack is a logic block packing tool for FPGA architecture research. Both are available free for non-profit, non-commercial use (such as academic research). This new version has some very significant enhancements over the last release version (Version 3.99). Some of the biggest ones are: - Support for routing architectures with wires that span multiple logic blocks (i.e. general segmented architectures) - Timing-driven routing - A delay estimator and path-based timing analyzer tell you how fast a circuit will run. - A detailed model of an FPGA's routing area is built in, and lets you evaluate the area of different architectures. If you have any questions, contact me at vaughn@rtrack.com. Vaughn BetzArticle: 14820
Hal, depending on the time of day, and your level of hunger, you may or may not be out to lunch. As for pin locking, and floorplanning, you are right on target. The people at FPGA vendors that recommend letting their sw pick the pinouts are clueless as to the issues that face a system designer, primarily because they have never done a real design with these products (or any other) in their life. While it is true that the tools may for a single instance select pins that are more appropriate than totally randomly selected pins by the user, any designer that is willing to think about the design's data and control flow for half an hour or more, is able to come up with a better pin floorplan than the tools can. Designers though are somewhat to blame for the situation, as the message that many deliver to the FPGA vendor is that they want a single button implementation flow. They dont want to spend any time learning what the products can do, or how they might adjust their design style to suit what the silicon has to offer. Telling a designer that the tools will pick a pinout for them is easier than telling them that they should read the design-style 101 section of the product data sheet, and take some responsibility for the implementation flow. Philip Freidin In article <7agg01$43c@src-news.pa.dec.com> murray@pa.dec.com (Hal Murray) writes: >One of the main advantages of FPGAs is that you can fix a bug >or make a minor change to the design and ship new bits to the field. >That requires pinlocking. So I assume that any software that doesn't >work well with locked pins is brain damaged, aka useless. > >An alternate way of looking at things is that floorplanning can >extend to the pins too. I often pick pins after carefully considering >the local routing in order to make sure the final result will be >fast enough. This sort of thing can be very important with chips like >the Xilinx 3000 series which have direct connections that save a >significant fraction of the total cycle time over misc local routing. > >Am I out to lunch to be thinking that way? > >-- >These are my opinions, not necessarily my employers.Article: 14821
Place and route times are totally dependent on your design style. While it is not uncommon to see postings in this news group from people complaining that their HDL based designs are taking tens of hours to place and route at 70% utilization in a device like a 4028XL, There are others of us here that have designs that are at 95% utilization of devices like 4062XL that place and route in 1.5 hours. The biggest difference in route times is effected by floorplanning your design. In my opinion, this is far easier to do with a schematic based flow than an HDL one, but is also dependent on learning what these devices are capable of, and adjusting the design to leverage these capabilities. Philip Freidin In article <7af9cb$lhv$1@nnrp1.dejanews.com> edwinpark@my-dejanews.com writes: >Does anyone have any P&R times for these two devices. Also, could you post >some info about the design (% utilization, # of registers, # I/Os, computer >used to P&R, etc). >I am going to start a design that needs many iterations and am very worried >about P&R times. >-EdwinArticle: 14822
I do not believe the Altera 6000 parts are any more sensitive to clock quality than any other vendor's FPGAs. The issue is that all these parts have very fast logic in them, even in areas where it is not needed like the configuration logic. So even if you are configuring at 1MHz, a 1nS glitch on the clock line can cause double clocking, and make configuration fail. Often, configuration support is left till the end of the project, and not given much attention, and because it is relatively slow compared to the rest of the design, clock integrity is often overlooked. With regard to how to terminate the clock signals, there is nothing special about how this should be done for FPGAs, that is different for any other clock signal. Your termination should be such that the rising and falling edges are monotonic at their destinations, and they arrive at the right time. This will depend on how you design the PCB, and not the FPGA. In article <7afhg8$h0d$2@news03.btx.dtag.de> carlhermann.schlehaus@t-online.de (Carlhermann Schlehaus) writes: >Philip Freidin <fliptron@netcom.com> schrieb in Nachricht >> ... me on signal integrity of config clock signal ... >>Philip > >Are the 6K FPGA such sensitve to the signals @ DCLK ? Well I've just started >a transition from an EPF81500 (which get'S to small in LCells and to >expensive >in money) to an EPF6016A. Hope it will work without such problems. >Furthermore, how and with what values should the Configurations lines be >terminated >to ensure correct function of FPGA ? > >Thanx, Carlhermann Schlehaus > > >Article: 14823
XILINX XC4000 CLB's can be configured to be triggered in any way: rising edge/falling edge. There are two kinds of D-flip-flop in XILINX schematic library: FD FD_1 If you are working not with a single trigger, but with a register - do not hesitate to place INV element on the clock circuit. Clever XILINX tools will absorb this element - it will just create proper kind of trigger configuration. Regards, Alex Sherstuk AMSD Company Zhen Luo wrote in message <36CC57D0.41C6@ee.princeton.edu>... >Hello, > >I am trying to map a design to some XC4010e-3 FPGAs, in this design, I >need some registers to be triggered at the clock's rising edge and some >registers to be triggered at the clock's falling edge. I am not sure if >Xilinx 4000e FPGAs provide registers that can be triggered at falling >edge of the clock. Further more, I am using some counters by logiblox >and it seems I can hardly modify them to let them be triggered at the >falling edge. Any suggestions? > >Thanks! > >-- ZhenArticle: 14824
Brian Dam Pedersen wrote: > > jamie morken wrote: > > > > Hi all, > > > > I have some VHDL code (below) that I would like to "put" into an array R > > > > so that I can select the register by typing R[ra] where ra is 0 for > > REGA, 1 for REGB, 2 for REGC and 3 for REGD. Any ideas? > > > > --current and next state of the four 8-bit general purpose registers > > SIGNAL curr_REGA, next_REGA: STD_LOGIC_VECTOR (7 DOWNTO 0); -- register > > A > > SIGNAL curr_REGB, next_REGB: STD_LOGIC_VECTOR (7 DOWNTO 0); -- register > > B > > SIGNAL curr_REGC, next_REGC: STD_LOGIC_VECTOR (7 DOWNTO 0); -- register > > C > > SIGNAL curr_REGD, next_REGD: STD_LOGIC_VECTOR (7 DOWNTO 0); -- register > > D > > > > Thanks for your time > > Declare your register file like this: > > SUBTYPE byte IS STD_LOGIC_VECTOR(7 downto 0); > > TYPE regs IS ARRAY (3 downto 0) OF byte; > > SIGNAL reginstance : regs; > > Now you can access reginstance(0) and so on. If you need individual bits, you > have to put your register into a temporary variable before accessing it eg: > > tmp:=reginstance(0); > > nibble<=tmp(7 downto 4); > > Hope this helps > -- AFAIR you can actually do this instead nibble <= reginstance(0)(7 downto 4); --L2C --___--_-_-_-____--_-_--__---_-_--__---_-_-_-__--_---- Lasse Langwadt Christensen, MSEE (to be in 1999) Aalborg University, Department of communication tech. Applied Signal Processing and Implementation (ASPI) http://www.kom.auc.dk/~fuz , mailto:langwadt@ieee.org
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