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Louis, It is not possible to model ANYTHING in VHDL with MaxPlus II's simulator. It has a proprietary file called a "SCIF" for .scf (simulation channel file). I may be wrong on this, because you never know, they may have an Easter Egg or something weird that does it, but it appears to be set up to only accept SCIFs. Allow me to make one comment on the MaxPlus II simulator -- it is VERY good for what it does. If you are writing VHDL test benches and want to simulate an RTL design along with SRAMs and FIFOs, that you have models for already I assume, then what you need is a VHDL simulator! I will assume that you are looking for the cheapest solution and that you probably have MaxPlus II already and want to use it. If that is the case, then you now know that MaxPlus II won't simulate VHDL designs, so what you want is the cheapest but good VHDL simulator. VHDL simulators range in price from about $1K to tens of thousands of dollars. One way of doing it cheaply is to evaluate a demo version, which tend to be full-blown versions, i.e., the real thing. I did some Xilinx designs using PeakVHDL, a VHDL simulator made by Accolade Design Automation (www.acc-eda.com), and it performed superbly. I chose it because at the time, it was the cheapest and best simulator for the money. Since then there have been some other VHDL simulators come out, and I have not evaluated them. For example, Aldec has a simulator whose GUI looks pretty interesting, but I also know that it costs substantially more than PeakVHDL. And of course there are other VHDL simulators out there that I have not test driven, so to be fair, you would have to give them a shot. One trend that I have noticed is that some of these VHDL simulators, especially the older ones, were developed to run on Sun workstations. As a result, they don't quite operate like PC Windows based programs do. They seem to have residual GUIs and mechanical features of programs that would run on Sun workstations. One example of this is the Model Sim VHDL simulator, which has a lot of workstation residual features, like forward slashes instead of back slashes. While this may sound trivial, sometimes it causes problems due to the confusion involved. On the other hand, the Model Sim is one of the few VHDL simulators that will simulate gate level VHDL files in a reasonable amount of time. Getting back to the topic of this paragraph, I would like to see some of these Sun workstation based simulators become true Windows products, so that us guys that use cheapie workstations can enjoy true Windows based products and cut down on the confusion. The tools used for FPGA design are confusing enough; why make them more difficult to use? If anyone has info on other VHDL simulators, I would like to know. I have a love-hate relationship with them! -Simon Ramirez Consultant/Contractor s_ramirez@msn.com Louis Zhang wrote in message ... >Hi, > >I was wondering if anyone used VHDL testbench >for Maxplus2 simulator? The idea is to simulate >the design (written in RTL) with some other >components such as SRAM and FIFO (modeled with >behavioral VHDL). It will be convenient to write >a VHDL testbench to instantiate all of these and >simulate it. Is it possible to do with Altera's >Maxplus2? How about Xilinx tools? > >Any suggestion is greatly appreciated. > >----------------------- >Louis Zhang >lzhang@eecg.toronto.edu >Article: 10776
VCC's contact information is available via their web site at http://www.vcc.com/contact.html. Their telephone number is 818-342-8294. For e-mail support, you may also try support@vcc.com. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Ed_Peschko@csgsystems.com wrote in message <6m8thv$r61$1@nnrp1.dejanews.com>... >All: > >I am trying to get ahold of VCC - interested in getting more specific >information (available OSes, etc) about the H.O.T II development system... >Unfortunately, all of my email messages to vcc.com seem to be falling into a >'bit bucket'. I know that messages from vcc can get to my system from the >outside - Steve Casselman sent me a message a while ago - but I'm not sure if >mine are making it anywhere. > >Is there a phone number where vcc can be reached? And could someone from VCC >ping me when they get this message (I have CC'ed it to info@vcc.com and >sc@vcc.com ) so I can make sure that I am getting through and so I can >possibly buy it? > >Thanks much, > >Ed > >-----== Posted via Deja News, The Leader in Internet Discussion ==----- >http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10777
I haven't seen one that provides CLB estimates, but you can find a list of a few VHDL books--some related to programmable logic--at http://www.optimagic.com/books.html#VHDL. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- SAMIR KHERICHA wrote in message ... > > Are there any good books which would help in predicting how many CLB's a >particular code in vhdl will take....I assume that's quite far is there >book or means to determine how much logic a particular statement in vhdl >will take and which is registered and which is non registered. > >samir > >------------------------------------------------------ >Samir Khericha >Graduate Research Assistant >Department Of Computer Engineering >Residence: >2383 duncan drive >apt #8 >fairborn OH 45324 >PH No: 937-426-8076 >_______________________________________________________ > >Article: 10778
Hi Simon, Thanks for your help. We do have Synopsys's VSS and Mentor Graphics VHDL Simualtor here. However, the picture is complicated a bit as some part of our design has LPM modules in it. I don't think Synopsys supports LPM so we cannot use its VHDL simulator to simulate our design. The gentleman from the previous message was suggesting porting the design back to a VHDL Simulator after synthesis and Place & Route (in Maxplus2). This might work as we'll only have gates (no LPM) in the netlist and Synopsys should support that. However, from design methodology point of view, it will be nice to be able to simulate it before Place & Route. What we really want to do is to model a RAM to which our design writes AND reads (the updated info). So unless we include this off-chip RAM as part of design (and synthesize it), there doesn't seem to be any solution of simulating it JUST with Maxplus2. :-( Regards, ----------------------- Louis Zhang lzhang@eecg.toronto.eduArticle: 10779
Hi everybody,
I am a grduate student, working in the area of hardware implementation of
Private_key Block ciphers using FPGAs as the target devices. While using the
Design manager of the XILINX 1.4, i tried to extract the "time_sim.vhd" file
generated after placement and routing to use as an input for the Synopsys
simulator to verify my design.But the problem is that while i try to
compile this time_sim.vhd file, the Synopsys compiler(vhdlan) gives an error
**Error: vhdlan,74 time_sim.vhd(33):
Corrupt intermediate file - SIMPRIM.VCOMPONENTS.sim (written using newer
version of the analyzer).
Can anybody help me in this matter as i am stuck at this stage of my
design, because i need this timing simulation to be the same as the one
that i got just after comiling my VHDL code in SYNOPSYS. this way i would
be sure of the correctness of my design.
Thanks,
Mohsin Riaz
Box#59,
Faculty Of Engineering,
Memorial University Of Newfoundland,
St. John's,Newfoundland,
A1B3X5,Canada.
____________________________
email:mohsin@engr.mun.ca
Web:www.engr.mun.ca/~mohsin
Tel# res:(709)576-8414
off:(709)737-8809
lab:(709)737-3583
Article: 10780Group of microelectronics engeniers in Kiev,Ukraine specializes in: - design of digital ICs for 0.6u/0.8u standard CMOS (any technology is possible if Design Rules and Process Specification could be got in our disposal); - design of 0.8u CMOS IC with embedded EEPROM blocks; - standard digital/analog cell design (Hspice models are needed); - layouts editing, DRC, LVS and layout support in accordance with customer task; - design of any digital sch on ACTEL FPGAs Please respond to me at rom@thesys.kiev.ua or at 38 044 241 7115 if you are interested, or would like to discuss any of your problems! Thank you for your time. Regards, tel 38 044 241 7115 fax 38 044 241 7031 email rom@thesys.kiev.ua Romanovsky Sergey, DesignManager Kiev UkraineArticle: 10781
Group of microelectronics engeniers in Kiev,Ukraine specializes in: - design of digital ICs for 0.6u/0.8u standard CMOS (any technology is possible if Design Rules and Process Specification could be got in our disposal); - design of 0.8u CMOS IC with embedded EEPROM blocks; - standard digital/analog cell design (Hspice models are needed); - layouts editing, DRC, LVS and layout support in accordance with customer task; - digital design on ACTEL's FPGAs Please respond to me at rom@thesys.kiev.ua or at 38 044 241 7115 if you are interested, or would like to discuss any of your problems! Thank you for your time. Regards, tel 38 044 241 7115 fax 38 044 241 7031 email rom@thesys.kiev.ua Romanovsky Sergey, DesignManager Kiev UkraineArticle: 10782
Louis Zhang wrote: > Hi Simon, > > Thanks for your help. > > We do have Synopsys's VSS and Mentor Graphics VHDL Simualtor > here. However, the picture is complicated a bit as some part > of our design has LPM modules in it. I don't think Synopsys > supports LPM so we cannot use its VHDL simulator to simulate > our design. The gentleman from the previous message was suggesting > porting the design back to a VHDL Simulator after synthesis > and Place & Route (in Maxplus2). This might work as we'll only > have gates (no LPM) in the netlist and Synopsys should support that. > However, from design methodology point of view, it will be nice to > be able to simulate it before Place & Route. If you use LPMs as in memory functions, you should be able to generate afunctional simulation model using the Altera "genmem" utility. The VHDL model generated by "genmem" should be support by Synopsys VSS according to Altera documentation. If the LPMs are not memory functions, it may be better to simulate the post-Place&Route VHDL netlist which also gives you timing. > > > What we really want to do is to model a RAM to which our design > writes AND reads (the updated info). So unless we include this > off-chip RAM as part of design (and synthesize it), there doesn't > seem to be any solution of simulating it JUST with Maxplus2. :-( > > Regards, > > ----------------------- > Louis Zhang > lzhang@eecg.toronto.edu -- ---------------------------------------------------------------- Scott Guest - MSS Nortel SPM OC-3 HW Dev.(3H54) 35 Davis Drive ph (919) 991-2215 Research Triangle Park, NC 27709 ESN 6-351-2215 E-mail: cnc274@nortel.ca FAX (919) 991-7754 ----------------------------------------------------------------Article: 10783
Simon Ramirez wrote: > > Louis, ...snip... > If anyone has info on other VHDL simulators, I would like to know. I > have a love-hate relationship with them! > -Simon Ramirez > Consultant/Contractor > s_ramirez@msn.com Here is my two cents worth on the Orcad VHDL simulator (and MY love-hate relationship). Their simulator does pretty much everything you would want it too, with one small exception... it crashes a lot, at least for me. I am the kind of guy that if you tell me about a neat way to implement something that will save me time in the long run by a small investment up front I will try it. The problem is that these "investments" rarely pan out the way you would want. This was the case with the Orcad simulator and using VHDL testbenches. They have the ability to simulate any part or your whole design whether it is VHDL or schematic or any mixture (although they don't support schematic components within VHDL as far as I know). This simulation can be driven by a very nice interactive stimulus or a VHDL testbench. Once I discovered that, I thought I would be hooked! The VHDL testbench allows you to stimulate your design from a VHDL program rather than some esoteric script language, or by using TEXTIO the stimulus can come from a text file of test vectors. You can even add code to check the results for you!!! No more staring at waveform displays until you're bleary eyed (unless you like that). There is only one small problem with this whole thing. I worked on a project with Orcad for over a month and never got it to finish simulation or to route in a Xilinx chip. In either case, I get fatal errors that I can't trace to any real problem in my code or crashes of the software. Orcad is not very fast at working on these types of problems. They are focusing their attention to other enhancements of the software such as adding mixed analog-digital simulation and they may even be tossing their VHDL compiler in favor of a third party package. These are fine, lofty goals, but they need to work on making their software more workable. -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10784
Is there anybody that can explain to me where to find some simply color video interface sources. Thanks DejanArticle: 10785
Hi, I'm wondering if anyone has successfully designed a circuit that would automatically convert a m68k type interface (big endian) to a PCI type interface (little endian). Thanks in advance. -- Dick Ginther E-mail: dick.ginther@develcon.com Develcon Electronics Ltd. Web: http://www.develcon.com 856 - 51st Street East Phone: 306 931-1339 Saskatoon, SK Canada S7K 5C7 Fax: 306 931-1352Article: 10786
Dick Ginther wrote: > > Hi, > I'm wondering if anyone has successfully designed a circuit that > would automatically convert a m68k type interface (big endian) to > a PCI type interface (little endian). > > Thanks in advance. Some people would have you believe that it is not possible to construct such a circuit. This is because the conversion is different depending on whether you are moving byte, word or long word data. Since most data moving across a given interface would be a mixture of these data items, it would be hard if not impossible to construct an "intelligent" interface to deal with such a mixture. Of course the exception to this is when you know in advance that the data moving across your interface is composed of a single data type and that type is defined. Such as the board I am building right now. We have a single data type moving across an interface, so we manage the byte swapping in hardware. But this is unusual. -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10787
Andy, I have read some of the messages in response to your message below, and my answer factors in those responses as well as your response to those responses! Let me see if I have this straight. The processor board outputs some discrete data bits and a clock, which is really a signal that tells you whether or not the data bit is valid or not. The data bits and this signal, which I will call DATA_VALID, are generated by a state machine on the processor board, and this state machine runs off a 20 MHz clock. Is this correct? It it is correct, then what you have is a simple and common problem. It is easily solved using synchronous logic. By this I mean that the state machine on the processor board should be synchronous with the state machine or some logic that captures the data on your board. In order to have both sets of logic synchronous, the 20 MHz clock must be brought to your board so that the capture logic will clock in the data. By using a common clock, both sets of logic will generate and capture the data based on whether DATA_VALID is asserted or not. One thing you must pay attention to is the skew on the clocks. There are ways to control skew, such as generating two clocks using a low skew generator such as an IDT 49FCT805 driver. One output generates a clock for the state machine on the processor board and another output on the same 805 generates a clock for your board's capture logic. This of course assumes that you have such a circuit or are capable of redesigning the circuit, as is often the case with wire wrap boards. If you cannot design a low skew double clock circuit, then I suggest that you do a timing analysis to find out exactly how much skew you have between the two clocks. One really good way of making the above synchronous design work is to center sample the signals at the capture logic on your board. In other words, the state machine on the processor board generates the data and DATA_VALID on the rising edge (assumption), and you sample those signals on the falling edge of the 20 MHz clock. Center sampling should work for you, since you have a 50 nsec period, and it gives you 25 nsec to center sample, minus the skew. Once you center sample the signals, you can either use them as is (falling edge clock for the logic that uses the data) or convert them back to rising edge clock by center sampling again. The reason that you would want to reconvert back to rising edge is so that most of the logic operates on the rising edge. The only logic that doesn't are the two center sample logic. And of course, it gives you a one clock delay of data. If you are unclear of what I am talking about or have questions or I am unclear of what you are talking about and want to set me straight, you may email me. -Simon Ramirez Consultant/Contractor 407-365-8928 s_ramirez@msn.com Andy Peters wrote in message <01bd9016$a68360b0$4601fc8c@shootingstar>... >Gang: > >I have to design a board that talks to a pre-existing processor >board. It's actually pretty simple, if sorta wacky: the processor >board outputs a bunch of discrete bits, a clock, and various clock >enables. If a clock enable is asserted, the bits it controls are >registered. Since there's a whole bunch of these bits, I'm going to >put the whole mess into a Xilinx part (probably a 9500 series) of >appropriate size, write fifteen or twenty lines of VHDL, and I'll be >done. This is all pretty standard. > >With the following exception: > >The clock doesn't run all the time: it is only asserted when some >bits are output and we need to latch them. > >A little more detail: all of these bits, the enables and this clock >are generated from a state machine that has a 50ns tick. For >example, if a 1 needs to be stored in one of these registers, the >hardware puts out a 1 on that data line. 50ns later, the clock line >is asserted for 50ns. These outputs are registered to a 20MHz clock. > >The question: does it really matter if the clock is aperiodic like >this? > >-- >Andy Peters >Sr. Electrical Engineer >National Optical Astronomy Observatories >apeters@noao.edu.NOSPAMArticle: 10788
Dear Dj, I know that I am publically revealling my lack of psychic ability here, but I think we'll need a little more information in order to help you. Assuming you mean digital or digitized video, do you mean component or composite, parallel or serial, etc.? What kind of interface are you referring to (i.e. what do you plan to do to this video after you've interfaced to it)? X Dj wrote in message <6mbnqh$acj$1@server-b.cs.interbusiness.it>... >Is there anybody that can explain to me where to find some simply >color video interface sources. >Thanks >DejanArticle: 10789
I am using Microsoft Visual SourceSafe to maintain FPGA versions
developed with XILINX Foundation.
(That is why, I am so interested in removing extra files from the
project - to avoid extreme growth of SourceSafe database.)
As far as concerns UNIX-style version control systems, I would advise
to look through GNU ports to Windows.
Alex Sherstuk
Sherstuk@amsd.com
Rickman wrote in message <35885383.8AD79B68@yahoo.com>...
>Pardon me if I am asking a dumb question, but is there a version of RCS
>which runs under windows? I am running windows 95 and if there is a
>version of any freeware VCS I would love to have it. I thought that RCS
>was only for Unix platforms.
>Rick Collins
>
>rickman@XYwriteme.com
>
>remove the XY to email me.
Article: 10790Dies ist eine mehrteilige Nachricht im MIME-Format. --------------096D5BE05FC37E172E22C170 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hallo, I'm working on my diploma in preimaging. So I do need a solution in following problem. An array of 640 pixel (row) x 3 (collumn) x 8 Bit should fit in a FPGA. However, the program FPGA-Express v.2.0 WIN NT seems to bring no result (olthougt waiting very long time). Have you a better realizing idea or can you recommend another FPGA??? Please help me. Mail to: halit.evli@e1.fh-giessen.de System: Design-Simulator HP-UX Design-Analyzer HP-UX v..1997.2 FPGA Express v. 2.0.1.8 WIN NT 4.0 HW: Pentium 233 / 128 (+800 virtuell) FPGA-Type xilinx 4062 My programm is attached to this eMail. Bye, Halit --------------096D5BE05FC37E172E22C170 Content-Type: text/plain; charset=us-ascii; name="Av_neu.vhd" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="Av_neu.vhd" LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; --IEEE1164 and IEEE arith use in ENTITY av IS PORT(horz,vert: IN BIT; Pixel_in: IN std_logic_vector (7 DOWNTO 0); Pixel_out: OUT std_logic_vector (7 DOWNTO 0)); END av; ------------------------------------------------------------------------------------ ARCHITECTURE arch_av OF av IS SIGNAL ind_vert, ind_horz: BIT; BEGIN PROCESS SUBTYPE pixelwerte IS integer RANGE 0 TO 255; TYPE bildzeile IS ARRAY (1 TO 512) OF pixelwerte; --horizontale Aufloesung TYPE matrix IS ARRAY (0 TO 2) OF bildzeile; --256 x 3 Matrix SUBTYPE horizwerte IS integer RANGE 0 TO 640; SUBTYPE vertwerte IS integer RANGE 0 TO 3; VARIABLE bild: matrix; --bild=matrix VARIABLE h: horizwerte; VARIABLE v: vertwerte; VARIABLE start: BIT; VARIABLE po: integer; BEGIN wait until (horz'event and horz='1'); h:=h+1; IF h=513 THEN ----max pixel+1 h:=1; v:=v+1; END IF; IF v=3 THEN v:=1; END IF; IF h=3 and v=2 THEN start:='1'; END IF; bild(v)(h):= CONV_INTEGER(pixel_in); IF start='1' THEN po:=(bild(1)(h-2)+bild(1)(h-1)+bild(1)(h) +bild(2)(h-2)+bild(2)(h-1)+bild(2)(h) +bild(0)(h-2)+bild(0)(h-1)+bild(0)(h)) ; po:=po*(2048/9); po:=po/2048; Pixel_out <=CONV_STD_LOGIC_VECTOR(po,8); END IF; END PROCESS; END arch_av; ------------------------------------------------------------------------------------------- CONFIGURATION cfg_av OF av IS FOR arch_av END FOR; END cfg_av; --------------096D5BE05FC37E172E22C170-- --------------3716A82B2BCD862563C9DEA5--Article: 10791
Dies ist eine mehrteilige Nachricht im MIME-Format. --------------3716A82B2BCD862563C9DEA5 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit --------------3716A82B2BCD862563C9DEA5 Content-Type: message/rfc822 Content-Transfer-Encoding: 7bit Content-Disposition: inlineArticle: 10792
I'm a student of Alicante University (Spain). I would be very gratefully
if you can help me in my program.
When I tried to simulate a program with the Orcad Express this piece of
code gives me problems, it start a infinity loop. Anybody knows how to
solve it?
signal c_out, p_out:bit_vector(0 to 63);
signal k:natural:=0;
begin
x1: for j in 7 downto 0 GENERATE
x2: for i in 0 to 7 GENERATE
x4: if i=0 GENERATE
m0: mult1x1 port
map(ain=>a(j),bin=>b(i),pout=>p_out(i+k),cout=>c_out(i+k));
end generate x4;
x5: if j=7 GENERATE
x51: if i/=0 Generate
m1: mult1x1 port map(ain=>a(j),bin=>b(i),
cin=>c_out(k+i-1), pout=>p_out(i+k),cout=>c_out(i+k));
end generate x51;
end generate x5;
x6: if j/=7 GENERATE
x61: if i /=0 Generate
m2: mult1x1 port map
(ain=>a(j),bin=>b(i),cin=>c_out(k+i-1),pin=>p_out(k+i-9));
end generate x61;
end generate x6;
end generate x2;
k<=k+8;
end generate x1;
Article: 10793I'm not sure exactly what you're looking for but there's a fairly good book on video called "Video Demystified". You can find a listing for it at http://www.optimagic.com/books.html#Video. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Dj wrote in message <6mbnqh$acj$1@server-b.cs.interbusiness.it>... >Is there anybody that can explain to me where to find some simply >color video interface sources. > > >Thanks >Dejan > >Article: 10794
Patrick Müller wrote: > Hi, > I am evaluating Xilinx FPGAs (Spartan XCS40XL-4 and XC4020XL-2). > In this devices I need a 128x17Bit dualport fifo that runs at 62.5MHz. > > Xilinx says, that this would not run with this speedgrades.... > Is it possible, that a interleaved dualport-fifo, implemented with > single port Memorys could reach that speed? And how many CLBs would be > > used? Hi, you may want to read my app note XAPP 051 "Synchronous and Asynchronous FIFO Designs". It discusses in detail the various design aspects of generating reliable FULL and EMPTY signals. The rest of a FIFO design is straightforward. A dual-port RAM obviously makes it much faster. The main question is whether write clock and read clock are coherent, or whether they are truly asynchronous to each other (the tough case). (This ignores the trivial case where write and read do not even overlap.) If you have detailed question, send me e-mail. In English or German. I designed the original FIFO at Fairchild in 1969, so I have a bit of experience in this field. Peter Alfke, Xilinx ApplicationsArticle: 10795
Dejan, Start with the back of your VCR at home. S. Ramirez Dj wrote in message <6mbnqh$acj$1@server-b.cs.interbusiness.it>... >Is there anybody that can explain to me where to find some simply >color video interface sources. > > >Thanks >Dejan > >Article: 10796
Hi, I would like to get into using FPGAs but I havn't really been able to find a lot of good information about how to use them and what I need to program them etc. Could anyone suggest a web site etc that I could find out such information. This is primarly a hobby so I don't really want to be able to do anything flash and I cann't afford an expensive programmer etc. Thanks Christopher Fairbairn lgcl01@es.co.nzArticle: 10797
Rick, Every Orcad product I ever used was riddled with bugs and problems. One has to invent workarounds and even then, one has to be very careful about what actually gets generated. If the Orcad output to the Xilinx place and route tool was unroutable, then it is intolerable. I would never tolerate such a tool, although I do tolerate problems with tools, as we all do. But at least my suite of tools always produced working designs that were very simulatable. Thanks for warning me about Orcad. -Simon ramirez Consultant/Contractor s_ramirez@msn.com Rickman wrote in message <35895EE4.C5B43CD3@yahoo.com>... >Simon Ramirez wrote: >> >> Louis, >...snip... >> If anyone has info on other VHDL simulators, I would like to know. I >> have a love-hate relationship with them! >> -Simon Ramirez >> Consultant/Contractor >> s_ramirez@msn.com > >Here is my two cents worth on the Orcad VHDL simulator (and MY love-hate >relationship). > >Their simulator does pretty much everything you would want it too, with >one small exception... it crashes a lot, at least for me. I am the kind >of guy that if you tell me about a neat way to implement something that >will save me time in the long run by a small investment up front I will >try it. The problem is that these "investments" rarely pan out the way >you would want. This was the case with the Orcad simulator and using >VHDL testbenches. > >They have the ability to simulate any part or your whole design whether >it is VHDL or schematic or any mixture (although they don't support >schematic components within VHDL as far as I know). This simulation can >be driven by a very nice interactive stimulus or a VHDL testbench. Once >I discovered that, I thought I would be hooked! The VHDL testbench >allows you to stimulate your design from a VHDL program rather than some >esoteric script language, or by using TEXTIO the stimulus can come from >a text file of test vectors. You can even add code to check the results >for you!!! No more staring at waveform displays until you're bleary eyed >(unless you like that). > >There is only one small problem with this whole thing. I worked on a >project with Orcad for over a month and never got it to finish >simulation or to route in a Xilinx chip. In either case, I get fatal >errors that I can't trace to any real problem in my code or crashes of >the software. Orcad is not very fast at working on these types of >problems. They are focusing their attention to other enhancements of the >software such as adding mixed analog-digital simulation and they may >even be tossing their VHDL compiler in favor of a third party package. >These are fine, lofty goals, but they need to work on making their >software more workable. > >-- > >Rick Collins > >rickman@XYwriteme.com > >remove the XY to email me.Article: 10798
Hi, We have an opportunity for an individual who has done some complex Circuit Board/FPGA design to work at a place where cutting edge technology is the norm, and one of the very best design staffs in the country awaits. This position is for someone who has between 3-10 years of high performance custom circuit design under his/her belt. You will be working on some of the "neatest" projects you've ever seen, and will become a stellar hardware designer for your efforts. Some of the "buzz": We are looking for High Speed Digital Designers, having some experience with PLD's, FPGA's (ASICS), complex designs (nothing simple at this place), understands timings, etc... Not a person who still needs a lot of instruction, we are hoping to find an individual who can stand alone and bring a project in from scratch to production. This is a great company! Our guarantee is this: If you go in and chat with these people, you WILL want to work there, especially if you can do this type of work. They are located on the North side of Chicago, near Skokie or Evanston, just off the Kennedy. Salary will be very nice, they're not cheap, as they're looking for the best we can bring in. Please E-mail or Fax us at: Hunter International E-mail: cleaner@starnetinc.com Fax: (815)356-9225 Thanks, Dave...Article: 10799
Simon Ramirez wrote: > > Rick, > Every Orcad product I ever used was riddled with bugs and problems. One > has to invent workarounds and even then, one has to be very careful about > what actually gets generated. > If the Orcad output to the Xilinx place and route tool was unroutable, > then it is intolerable. I would never tolerate such a tool, although I do > tolerate problems with tools, as we all do. But at least my suite of tools > always produced working designs that were very simulatable. > Thanks for warning me about Orcad. > -Simon ramirez > Consultant/Contractor > s_ramirez@msn.com The real shame is that I think the Orcad product has a better user interface in many respects than the Xilinx Foundation. If they got rid of all of the bugs and "rough edges" it would only have a single problem for doing FPGAs. It would still be a third party tool which is not tightly integrated with the backend tool. This shows up when you try to deal with things like timing or location constraints. For now I am using the Xilinx Foundation tool. It is a little less sophisticated in some respects and more in others, such as the state machine editor which Orcad doesn't even have. But the main point is that every problem I have had with the tool has been resolved in a half hour or less either by myself or Xilinx tech support! When they get FPGA Express integrated in the next release it should be an even better tool. If they could just get testbench simulation into the mix!!! -- Rick Collins rickman@XYwriteme.com remove the XY to email me.
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